CN100423070C - OLED display with reciprocating switching working current drive circuit and synchronous row scanning - Google Patents

Abstract

A display drive apparatus includes a selection circuit which sets display pixels in a plurality of specific rows of the display panel in a selected state simultaneously with selection signals of said rows at least overlapping each other. A gradation signal generation circuit generates a gradation signal which controls a luminance gradation of each OLED display pixel based on the display data and sequentially supplies the generated gradation signal in a ping pong manner. A plurality of signal distribution circuits sequentially distribute the gradation signal supplied by the gradation signal generation circuit in accordance with the plurality of display pixels in each column at the timing of time-series supply. A plurality of current holding circuits individually hold the distributed gradation signal and simultaneously supply as the gradation current a current having a current value based on the held gradation signal to the display pixels in the plurality of simultaneously scanned rows.

Description

OLED display with reciprocating switching working current drive circuit and synchronous row scanning

field of invention

The present invention relates to a display driving device, a display device and a driving control method thereof, and more particularly to a display driving device applicable to a display panel on which a plurality of display pixels are arranged, and each display pixel includes a current-controlled light emitting device. An element emitting light having a predetermined gradation of brightness by supplying a current corresponding to display data; and a display device including the display driving device; and a driving control method thereof.

technical background

Conventionally, a known light emitting element type display (display device) includes a display panel in which each display pixel includes a current control type light emitting element that emits light with a predetermined gradation of brightness depending on the current value of a supplied driving current. are two-dimensionally arranged, like organic electroluminescent elements (hereinafter will be referred to as "organic EL elements") or light emitting diodes (LEDs).

In particular, compared with the liquid crystal display device (LCD) widely used in recent years, the light-emitting element type display adopting the active matrix driving mode has a higher display response rate, has no field angle dependence, and can realize high luminance/ High contrast, high definition of display image quality, reduced power consumption and other advantages. In addition, a light emitting element type display includes a light emitting element type display pixel, and thus does not require a backlight like a liquid crystal display device. Therefore, the light-emitting element type display has excellent characteristics, can further reduce thickness and weight, and has been intensively researched and developed as a next-generation display.

FIG. 18 is a schematic diagram showing a structural example of a main part of a light emitting element type display employing an active matrix driving mode in the prior art.

19 is an equivalent circuit diagram showing an example of the structure of a display pixel applied to a light emitting element type display employing an active matrix drive mode in the prior art.

As shown in FIG. 18 , in the prior art, a light emitting element type display adopting an active matrix driving mode has a structure including: a display panel 110P in which a plurality of display pixels EMP are arranged in a matrix form (n rows×m columns). Each display pixel EMP includes, for example, near each intersection of a plurality of scanning lines SL and a plurality of data lines DL, a pixel driving circuit described later and a current control type light emitting element (such as an organic EL element), where SL and DL are substantially perpendicular to each other. The scan driver 120P is connected to the scan lines SL of the display panel 110P, and sets the display pixels EMP of each row to a selected state by sequentially applying the scan signal Vsel to each scan line SL at predetermined timing. The signal driver 200P is connected to the data lines DL of the display panel 110P, and acquires display data at a predetermined timing, and supplies a gradation current Ipix corresponding to the display data to each data line DL.

In this type of display, the operation states of the scan driver 120P and the signal driver 200P are controlled by, for example, a scan control signal, a data control signal, and the like, wherein these signals are generated based on timing signals supplied from the outside and correspond to display data. A gradation current is written to the display pixels in each row that are set to the selected state by application of the scan signal. As a result, each display pixel emits light having a predetermined gradation of brightness, thereby displaying desired image information.

In such a light-emitting element type display adopting an active matrix driving mode, various types of drive control mechanisms or control methods have been proposed, which control the light emission of the above-mentioned current-controlled light-emitting element. For example, a display is known that includes a pixel driving circuit that is composed of a plurality of switching devices that control the light emission of a light emitting element and the light emitting element in accordance with each display pixel constituting a display panel.

For example, as shown in FIG. 19, such a pixel driving circuit specifically includes: a pixel driving circuit DP1; and an organic EL element OEL having an anode terminal connected to a drain terminal of a transistor Tr124 of the pixel driving circuit DP1, and applied with Cathode terminal at ground potential. Near each intersection of a pair of scan lines SL1 and SL2 arranged in parallel with each other and a data line DL, the pixel drive circuit DP1 includes: a first transistor Tr121 having a gate terminal connected to the scan line SL1, and a gate terminal connected to the data line DL is connected to the source terminal and the drain terminal of the contact N121; the second transistor Tr122 has the source terminal and the drain terminal connected to the contact N121 and the contact N122; the third transistor Tr123 has the A gate terminal connected to the contact N122, a drain terminal connected to the contact N121, and a source terminal applied with a higher power supply voltage Vdd; a fourth transistor Tr124 having a gate terminal connected to the contact N122 terminal, and a source terminal to which a higher supply voltage Vdd is applied.

In this example, in FIG. 19 , the first transistor Tr121 includes an n-channel type field effect thin film transistor, and each of the second to fourth transistors Tr122 to Tr124 includes a p-channel type field effect thin film transistor. In addition, CP1 represents a parasitic capacitance formed between the gates and sources of the third and fourth transistors Tr123 and Tr124.

In the pixel drive circuit DP1 having such a structure, by turning on/off four transistors (switching means) including the transistors Tr121 to Tr124 at predetermined timing, the organic EL element OEL is subjected to light emission control as follows.

That is, in the pixel driving circuit DP1, when the scan driver 120P sets the display pixel to the selected state by applying the high-level scan signal Vsel1 to the scan line SL1 and the low-level scan signal Vsel2 to the scan line SL2 respectively, the transistor Tr121, Tr122, and Tr123 are turned on, and a layer current Ipix corresponding to display data flows through the transistors Tr121 and Tr123, wherein the signal driver 200P supplies the display data to the data line DL. At this time, since the portion between the gate and the drain of the transistor Tr123 is electrically short-circuited by the transistor Tr122, the Tr123 operates in a saturation region. As a result, the current level of the tier current Ipix is converted to a voltage level by the transistor Tr123, thereby generating a predetermined voltage between the gate and the source (writing operation). In accordance with the voltage generated between the gate and source of the transistor Tr123, the transistor Tr124 is turned on, and a predetermined drive current flows from the high power supply voltage Vdd, through the transistor Tr124 and the organic EL element OEL, into the ground potential, thereby emitting light (light emission) from the organic EL element. operate).

Subsequently, when, for example, the advanced scan signal Vsel2 is applied to the scan line SL2, the transistor Tr122 is turned off. As a result, the voltage generated between the gate and source of the transistor Tr123 is held by the parasitic capacitance CP1. Next, when the low-level scan signal Vsel1 is applied to the scan line SL1, the transistor Tr121 is turned off. As a result, the data line DL and the pixel driving circuit DP1 are electrically disconnected. Therefore, the fourth transistor Tr124 is continuously kept on-state by the potential difference based on the voltage held in the parasitic capacitance CP1, a predetermined drive current flows from the high power supply voltage Vdd, through the transistor Tr124 and the organic EL element OEL, into the ground potential , and thus continue the light emitting operation of the organic EL element OEL.

Here, the drive current supplied to the organic EL element OEL through the transistor Tr124 is controlled to have a current value based on the luminance gradation of display data, and the light emitting operation is controlled to last for a period of, for example, one frame until a gradation current corresponding to the next display data written to each display pixel.

The drive control method in the pixel drive circuit having such a circuit structure supplies a gradation current to each display pixel (the gate terminal of the third transistor Tr123), wherein the current has a specific current value corresponding to the display data, the method also A driving current, which is passed through the organic EL element, is controlled based on a voltage held in accordance with a current value, thereby affecting a light emitting operation with a predetermined gradation of luminance. Therefore, this method is called a current application mode (or a current specification mode).

Like FIG. 19, there is also known a drive control method employing a voltage application mode (or voltage designation mode) in which the method applies a gradation voltage having a designated voltage value corresponding to display data to each display pixel, wherein each display A pixel includes a pixel driving circuit and an organic EL element, and the method controls a driving current according to a voltage value of a gradation voltage, wherein the current passes through the organic EL element OEL, thereby affecting a light emitting operation with a predetermined gradation of brightness. In a pixel driving circuit employing such a voltage designation mode, irregularities or fluctuations (degeneration) occur in the element characteristics (channel resistance of transistors or others) of switching elements which depend on the external environment (ambient temperature or Others), use time and similar conditions, have a selection function or a light-emitting drive function, so that the drive current is affected. Thus, the pixel driving circuit has a problem that desired light emission characteristics (display with predetermined gradation of luminance) cannot be stably realized for a long time in time. Or, when each display pixel is finely formed, in order to achieve high definition of the display panel, irregularities in the operation characteristics (current between source and drain of transistors and others) of switching elements constituting the pixel drive circuit becomes large, and thus cannot perform proper hierarchical control. Therefore, the pixel driving circuit has a disadvantage that the occurrence of irregularities in the light emission characteristics of each display pixel leads to degradation of the display image quality.

On the contrary, the pixel driving circuit employing the current designation mode includes a third transistor Tr123 (current/voltage conversion transistor) which converts the current level of the layer current corresponding to the display data supplied to each display pixel into a voltage level and a fourth transistor Tr124 (light emission driving transistor) which supplies a driving current having a predetermined current value to the organic EL element OEL. By setting the current value of the drive current supplied to the organic EL element OEL, the pixel drive current can suppress the influence of irregularities in the operation characteristics of the respective transistors Tr123 and Tr124, and thus has an advantage that it can be solved using the voltage designation mode The problem of the pixel driving circuit.

However, the pixel drive circuit employing the current designation mode has the following problems.

In the case of writing the gradation current based on the display data with the lowest luminance or relatively low luminance in each display pixel (at the time of low-level display), the signal current with a smaller current value corresponding to the luminance gradation of the display data Must be provided for each display pixel.

Here, since the operation of writing the hierarchical current in each display pixel corresponds to charging the capacitive element (constituting the wiring capacitance and the holding capacitance of the display pixel) to a predetermined voltage, wherein the capacitive element is parasitic on the data line, the wiring of the data line The length becomes longer due to, for example, an increase in the size of the display panel. In addition, when the number of display pixels connected to the data line increases, when the current value of the layer current becomes smaller, that is, when a lower-level display is effected, the time required to charge the data line becomes longer, and thus the time required for a write operation per display pixel increases. The writing operation with respect to each display pixel cannot be completed within a preset writing time, and a so-called insufficient writing state occurs in which a steady state (saturation state) is not reached. As a result, display pixels cannot emit light with an appropriate gradation of brightness corresponding to display data, resulting in degradation of display image quality.

In addition, when the number of scan lines arranged on the display panel is increased in order to achieve high definition of the display panel, and the selection period (that is, the writing time) of each scan line is set to be short, due to the layer current The current value decreases, so that a sufficient writing operation cannot be performed with respect to each display pixel, and an insufficient writing state is generated, resulting in degradation of display image quality or limiting high definition of the display panel.

Contents of the invention

In a display driving device that drives display pixels of a display panel based on display data and a display device including the display driving device, the present invention has an advantage that insufficient The written state appears, and high definition of the display panel can be excellently realized.

In order to achieve the above advantages, according to one aspect of the present invention, a display driving device is provided, which drives a plurality of two-dimensionally arranged display pixels constituting a display panel based on display data, and the display driving device at least includes:

selection circuitry for setting display pixels in a plurality of specific rows of the display panel to a selected state, having periods that at least overlap each other;

a gradation signal generating circuit, which generates a gradation signal, and controls the brightness gradation of each display pixel based on the display data; and

The current writing circuit obtains the signal current corresponding to the display pixels in the plurality of specific rows, and provides the display pixels in the plurality of specific rows with a level-based The level current of the current value of the signal.

The current writing circuit is preferably formed in a configuration independent of the display panel, or is composed of a plurality of field effect thin film transistors each having an amorphous silicon semiconductor layer having a single channel polarity as a channel layer, or is composed of A plurality of field effect thin film transistors having a polysilicon semiconductor layer as a channel layer are formed and integrated with a display panel.

Preferably, the gradation signal generation circuit generates a signal current as a gradation signal to supply a luminance gradation corresponding to the display data to the display pixels, and the current writing circuit has means for generating and outputting a gradation current having the same gradation current as determined by The current polarity of the signal current supplied by the current generating part is opposite.

Preferably, the selection circuit has means for synchronously setting display pixels on a plurality of specific rows of the display panel to a selected state based on a single selection signal; the current writing circuit has a timing for setting the selection state according to the selection signal , a device for synchronously providing hierarchical currents to display pixels in a plurality of specific rows; the hierarchical current generation circuit has a device for sequentially providing hierarchical signals to the current writing circuit in time series, wherein the hierarchical signals correspond to the display in a plurality of specific rows a plurality of display pixels in each column of pixels; the current writing circuit includes a plurality of signal distribution circuits, the circuit is provided according to each column of display pixels in a plurality of specific rows, and the circuit is provided according to a plurality of display pixels in each column, The gradation signals provided by the gradation signal generating circuit are sequentially distributed at the timing of the time-series source, and a plurality of current holding circuits individually hold the gradation signals distributed by the signal distribution part, and simultaneously supply display pixels in a plurality of specific rows with The current based on the current value of the held tier signal is used as the tier current. In multiple stages, a multi-stage signal holding/output section is provided for each current holding circuit, and the signal holding/output section includes a signal holding section that holds a signal current distributed by a signal distribution circuit, and includes a hierarchical current output section, according to multiple Each of a plurality of display pixels in each column of display pixels in a specific row outputs a current as a gradation current, wherein the current corresponds to the signal current held in the signal holding portion. An operation of acquiring and holding a signal current performed by the signal holding section on one stage of the multi-stage signal holding/outputting section is controlled to be performed simultaneously with an operation of outputting a tier current by the tier current output section at any other stage.

Preferably, the selection circuit has means for sequentially setting display pixels corresponding to a plurality of specific rows to have overlapping periods by sequentially applying a selection signal to each specific row of the display panel with overlapping periods. A select state, wherein the select signal sets the display pixels in each row to the selected state. The current writing circuit has means for supplying the gradation current to each specific row at overlapping periods at a timing corresponding to application of a selection signal of the selection circuit. The gradation signal generation circuit has means for sequentially supplying a gradation signal corresponding to a plurality of display pixels in each column of display pixels in a plurality of specific rows to the current writing circuit in time series. The current writing circuit includes a plurality of current holding circuits, which are provided according to each column display pixel in a plurality of specific rows, and sequentially hold the layer signals provided by the layer signal generation circuit according to the timing of the time series source, and supply each specific The rows sequentially supply a current having a current value based on the tier signal as a tier current. According to a plurality of display pixels in each column of display pixels in a plurality of specific rows, each current holding circuit includes a plurality of current holding/output sections, and each current holding/output section has a signal distribution section according to timing distribution of a time series source The signal current; also includes a signal holding section holding the signal current distributed by the signal distribution section; and including a tier current output section outputting a current corresponding to the signal current held in the signal holding section as a tier current. The operation of outputting the hierarchical current based on the signal current held in the signal holding section performed by the hierarchical current output section of one of the current holding/output sections, and held in the signal holding section in the other current holding/output section by The signal current distributed by the signal distribution section, and the operation of outputting the tier current by the tier current output section based on the signal current held in the signal holding section are controlled to be performed synchronously in overlapping periods.

Preferably, the signal holding section includes a charge storage circuit that stores charges based on the signal current and holds the charges as voltage components, and the hierarchical current output section has a current mirror circuit structure that generates and outputs a current having a certain current value as the hierarchical current , wherein the current value has a predetermined current ratio relative to the current value corresponding to the gradation signal provided by the gradation signal generating circuit.

In order to obtain the above advantages, according to another aspect of the display device of the present invention, a display device is provided for displaying image information based on display data, the display device at least includes:

The display panel has a plurality of scanning lines arranged in the row direction and a plurality of data lines arranged in the column direction, and a plurality of display pixels arranged in a matrix near the intersections of the plurality of scanning lines and the plurality of data lines;

a scan driver, which sets display pixels corresponding to a plurality of specific scan lines to a selected state, wherein the scan line is at least a part of the plurality of scan lines of the display panel, and the selected states have at least periods overlapping each other; and

a signal driver including a gradation signal generation circuit that provides display data to the circuit, and that generates a gradation signal that controls the brightness gradation of each display pixel based on the display data; and a current writing circuit that acquires a signal current corresponding to the display pixel, wherein the display pixels correspond to a plurality of specific scan lines, and the circuit supplies the display pixels corresponding to the plurality of specific scan lines with the current value based on the level signal according to the timing at which the scan driver sets the display pixels to the selected state level current.

Preferably, the signal driver is formed in a configuration independent of the display panel, or by using a plurality of field effect thin film transistors in which each transistor has an amorphous silicon semiconductor layer having a single channel polarity as a channel layer, or a plurality of A field effect thin film transistor with a polysilicon semiconductor layer as a channel layer constitutes a current writing circuit in a signal driver and is integrated with a display panel on a single insulating substrate.

Preferably, the gradation signal generation circuit generates a signal current as a gradation signal to provide a luminance gradation corresponding to the display data to the display pixels. In addition, the current writing circuit in the signal driver has means for generating and outputting a layer current having a current polarity opposite to that of the signal current supplied from the current generating section.

The display pixel may include a pixel driving circuit that generates a predetermined driving current based on a gradation current output from the signal driver, and a current control type light emitting element that emits light having a predetermined luminance gradation based on a current value of the driving current.

The pixel driving can be constituted by using a plurality of field effect thin film transistors in which an amorphous silicon semiconductor layer having a single channel polarity is used as a channel layer, or using a plurality of field effect thin film transistors in which a polysilicon semiconductor layer is a channel layer circuit, and the light-emitting element is, for example, an organic electroluminescence element.

The display panel may have a plurality of data line groups, among which a plurality of data lines corresponding to the number of scan lines of each scan line group are determined as one group. Each data line group is arranged according to the area between multiple columns of display pixels arranged in a matrix in the display panel, and the display panel has a plurality of scan line groups, wherein a plurality of specific scan lines are determined as a group.

Preferably, the scan driver has means for synchronously setting display pixels corresponding to a particular plurality of scan lines to a selected state by applying a single scan signal to each scan line group, wherein the scan signal will Displays pixels set to selected state. The layer signal generating circuit in the signal driver has such a device for sequentially providing the layer signal corresponding to a plurality of display pixels to the current writing circuit in time series, wherein the display pixel corresponds to each data line group. Each scan line group in the data line. The current writing circuit in the signal driver includes: a plurality of signal distribution circuits, arranged according to each data line group, and according to the timing of the time series source, according to each data line in each data line group, sequentially distribute the hierarchical signals the gradation signal provided by the generation circuit; and a plurality of current holding circuits which individually hold the gradation signal distributed by the signal distribution section, and according to the timing of applying the scanning signal to each scanning line group, the synchronization will have a gradation signal based on the held gradation signal A current of the current value is supplied to each data line in each data line group as a layer current. A multi-stage signal holding/output section is provided for each current holding circuit, and each signal holding/output section includes a signal holding section that holds the layer signal distributed by the signal distribution circuit, and includes a layer current output section that depends on each data Each of the data lines in the line group outputs, as a tier current, a current having a current value based on the tier signal held in the signal holding section. An operation of acquiring and holding a gradation signal performed by the signal holding section on one stage of the multi-stage signal holding/outputting section, and an operation of outputting a gradation current by the gradation current output section on the other stage are controlled to be performed synchronously.

Preferably, the scan driver has means for sequentially setting the display pixels corresponding to the plurality of specific scan lines to a selected state with overlapping periods by sequentially applying a scan signal to each specific scan line with overlapping periods , where the scan signal sets the display pixels to the selected state. The current writing circuit in the signal driver has means for supplying the layer current to each data line of each data line group in an overlapping period sequentially at a timing corresponding to application of a scan signal by the scan driver.

Preferably, the scan driver has a means for setting the display pixels corresponding to the plurality of specific scan lines in an overlapping period to a selected state by sequentially applying a scan signal to each specific scan line in an overlapping period, wherein The scan signal sets the display pixels to a selected state. The level signal generating circuit in the signal driver has a device for sequentially providing level signals corresponding to a plurality of display pixels to the current writing circuit in time series, wherein the display pixels correspond to each of the data line groups Multiple specific scan lines in a data line. The current writing circuit includes a plurality of current holding circuits, which are provided according to each data line group, sequentially hold the layer signals provided by the layer signal generation circuit according to the timing of the time series source, and send each Each data line in the data line group sequentially supplies a current having a current value corresponding to the level signal as a level current. A plurality of signal holding/output sections are provided for each current holding circuit according to each data line in each data line group, and each signal holding/output section includes a signal distribution section which, at the timing of the time series source, according to each Each data line in a data line group sequentially distributes a hierarchy signal; a signal holding part which holds the hierarchy signal distributed by the signal distribution part; and a hierarchy current output part which outputs a current having a current value based on the hierarchy signal as a hierarchy current, where the level signal is held in the signal hold section. In one of the current holding/output sections, in the signal holding section the layer signal distributed by the signal distribution section is held, and the operation of outputting the layer current based on the layer signal by the layer current output section, and in any other current holding/output section In , the operation of outputting the layer current by the layer current output section, which is controlled to be performed synchronously in the overlapping period based on the layer signal held in the signal holding section, is performed.

The signal holding section may include a charge storage circuit, stores charges corresponding to the gradation signals, and holds the charges as voltage components. The tier current output section may have a current mirror circuit structure to generate and output a current having a current value having a predetermined current ratio with respect to a current value corresponding to the tier signal supplied from the current generating section as the tier current.

According to the driving method of a display device in still another aspect of the present invention that achieves the above object, display pixels corresponding to a plurality of specific scanning lines are set to a selected state having at least an overlapping period, thereby providing display data, wherein the specific The scan line is at least a part of the plurality of scan lines in the display panel. A gradation signal is generated based on the display data, wherein the gradation signal controls the brightness gradation of each display pixel. A level signal corresponding to a display pixel is obtained, wherein the display pixel corresponds to a plurality of specific scan lines. A gradation current having a current value based on the gradation signal is generated, and the generated gradation current is supplied to display pixels corresponding to a plurality of specific scan lines in accordance with timing of setting the display pixels to a selected state. The display pixels to which the gradation current is supplied and written operate with display luminance based on the current value of the gradation current.

The operation of generating the gradation signal generates, as the gradation signal, a signal current that provides a brightness gradation corresponding to the display data to the display pixels. The operation of generating and outputting a tier current having a current value based on the tier signal may include generating a current, and outputting the generated current as a tier current, wherein the generated current has a predetermined current value with respect to the current value corresponding to the tier signal ratio.

The operation of setting the display pixels to the selected state may include the operation of synchronously applying a single scan signal to a plurality of specific scan lines, so that the display pixels corresponding to the plurality of scan lines can be synchronously set to the selected state, wherein the The scan signal sets the display pixels to a selected state. The operation of supplying the gradation current may include an operation of synchronously supplying the gradation current to the display pixels corresponding to the plurality of scan lines. The operation of synchronously supplying the gradation current to the display pixels corresponding to the plurality of scanning lines may include synchronously performing an operation of acquiring and holding a gradation signal corresponding to each scanning line, and outputting based on the gradation signal acquired and held at the above-mentioned timing, Hierarchical current manipulation.

Preferably, the operation of setting the display pixels to the selected state sequentially applies the scan signal to each specific scan line with overlapping periods, so that the display pixels corresponding to the plurality of scan lines are sequentially set to the selected state with overlapping periods , where the scan signal sets the display pixels to the selected state. The operation of supplying the gradation current includes an operation of sequentially supplying the gradation current to display pixels corresponding to each scanning line in overlapping periods at the timing of application of the scanning signal. The operation of sequentially supplying the gradation current to the display pixels corresponding to the plurality of scanning lines, the operation of holding the gradation signal based on the gradation signal and outputting the gradation current, and the operation of outputting the gradation current based on the gradation signal held at the above timing, to overlap The cycles are executed synchronously.

Brief description of the drawings

1 is a schematic block diagram showing the complete structure of a display device according to one embodiment of the present invention;

FIG. 2 is a structural view showing a part of the display device shown in FIG. 1 according to the embodiment;

FIG. 3 is a block diagram showing a structural example of a current generating section that can be applied to the display device according to the embodiment shown in FIG. 1;

4 is a circuit configuration diagram showing a configuration example of a current holding/distribution section that can be applied to the display device according to the embodiment shown in FIG. 1;

5A and 5B are conceptual diagrams illustrating schematic operations of a current holding/distributing section that can be applied to the embodiment shown in FIG. 1;

6 is a timing chart illustrating a drive control operation (drive control method) in the display device according to the embodiment shown in FIG. 1;

FIG. 7 is a schematic configuration diagram of main parts showing another configuration example of the display device according to the embodiment shown in FIG. 1;

FIG. 8 is a schematic structural diagram showing a main part of still another example of the display device according to the embodiment shown in FIG. 1;

FIG. 9 is a structural view showing a part of a second embodiment of a display device according to the present invention;

FIG. 10 is a circuit configuration diagram showing a configuration example of a current holding/distribution section that can be applied to the display device according to the embodiment shown in FIG. 9;

11A and 11B are conceptual diagrams illustrating schematic operations of a current holding/distributing section that can be applied to the embodiment shown in FIG. 9;

FIG. 12 is a timing diagram showing a driving control method of the display device according to the embodiment shown in FIG. 9;

FIG. 13 is a schematic structural view showing a main part of another structural example in the second embodiment of the display device according to the present invention;

14 is a circuit configuration diagram showing a specific circuit example of a display pixel that can be applied to a display device according to the present invention;

15A and 15B are conceptual diagrams illustrating a driving control operation of a pixel driving circuit according to the embodiment shown in FIG. 9;

16 is a schematic block diagram showing a structural example of a display device to which display pixels according to the embodiment shown in FIG. 14 can be applied;

17 is a schematic block diagram showing another structural example of a display device to which display pixels according to the embodiment shown in FIG. 14 can be applied;

18 is a schematic diagram showing a structural example of a main part of a light emitting element type display adopting an active matrix driving mode in the prior art; and

FIG. 19 is an equivalent circuit diagram showing a structural example of a display pixel applied to a light emitting element type display employing an active matrix drive mode in the prior art.

Detailed description of the invention

Hereinafter, based on the illustrated embodiments, a display device and a driving control method thereof according to the present invention will be described.

<First Example of Display Device>

A schematic structure of a display device to which a display driver device according to the present invention can be applied will be described first.

FIG. 1 is a schematic block diagram showing the entire structure of a display device according to one embodiment of the present invention.

FIG. 2 is a structural diagram showing a main part of a display device according to this embodiment.

As shown in FIG. 1 , a display device 100 according to the present invention mainly has a display panel 110A, a scan driver (selection circuit) 120A, a current generation section (hierarchical signal generation circuit) 130, a current holding/distribution section (current writing circuit) 140A , the system controller 150 and the display signal generation part 160.

As shown in FIG. 2 , the display panel 110A basically has a plurality of display pixels EM arranged two-dimensionally (n rows×m columns) and connected to the selection transistor Trsel. A plurality of scan line groups SGi are arranged according to display pixels EM in multiple rows (two rows in this embodiment), and a plurality of (two in this embodiment) scan lines SLia and SLib (i is in the range 1 Positive integers within ≤i≤n′, for example, a divisor of the total number of rows n provided in the display panel 110A; n′ and n are positive integers) are determined as one group. According to the display pixels EM in each column corresponding to each scanning line group SGi, a plurality of data line groups DGj are arranged, and a plurality of (in this embodiment, two) data lines DLja and DLjb (j is within the range A positive integer within 1≤j≤m, where m is a positive integer and the total number of pixel columns set in the display panel 110 ) is determined as one group. Each display pixel EM is provided near the intersection of the scan lines SLia and SLib constituting each scan line group SGi, and the data lines DLja and DLjb constituting each data line group DGj.

The scan driver (selection circuit) 120A is generally connected to the scan line groups SGi of the display panel 110A, and sequentially applies the scan signal Vsel to each scan line group SGi at a predetermined timing to synchronously set the display pixels EM, wherein the display pixels EM This corresponds to a plurality of lines (two lines in this embodiment) connected to the scanning line group SGi.

The current generation section (gradation signal generation circuit) 130 usually acquires display data corresponding to display pixels supplied from a display signal generation section 160 described later, the display pixels corresponding to the rows of the scanning line group SGi (this embodiment Two lines in the middle), and in time series, signal currents (level signals) Ic with respect to a plurality of corresponding lines are supplied to the current holding/distributing section 140A.

A current holding/distributing section (current writing circuit) 140A is generally connected to each data line group DGj of the display panel 110A, and in time series at predetermined timing, distributes the data corresponding to a plurality of rows ( In this embodiment, the signal current Ic of two lines) is maintained for each line, and the level current Ipix based on the held signal current Ic is synchronously supplied to the multiple lines (two lines in this embodiment) Display pixels EM. In this embodiment, the current generating section 130 and the current holding/distributing section 140A constitute a signal driver 200A.

The system controller 150 generates and outputs a scan control signal and a data control signal to control at least the operation states of the scan driver 120A, the current generation portion 130 and the current holding/distributing portion 140A based on, for example, a timing signal provided by the display signal generation portion 160 .

The display signal generating section 160 generates display data (for example, digital data) based on, for example, a video signal supplied from the outside of the display device 100, and supplies the display data to the current generating section 130, and further generates or extracts a timing signal (system clock or the like). ) and provide the timing signal to the system controller 150, where the timing signal displays the display data as an image in the display panel 110A.

In the structure shown in FIG. 2, as a structural example, the current holding/distributing part 140A and the pixel array are integrated on an insulating substrate BASE, and a plurality of display pixels EM (that is, a pixel array) constituting the display panel 110A are formed on the substrate, But the present invention is not limited to this structure. For example, the signal driver 200A may have a configuration of a driver chip and be mounted (packaged) on a substrate BASE.

The specific configuration of each structure will now be described.

(display panel)

For example, as shown in FIG. 2 , the display panel 110A has a structure that can be applied to the display device according to this embodiment, and in this structure, each scanning line group SGi corresponding to two rows and Each data line group DGj corresponding to a pixel column is arranged perpendicular to each other, wherein in two rows, two separate scan lines SLia and SLib are determined as a group, and in a pixel column, two data lines DLja and DLjb were identified as a group. Each display pixel EM is connected to the intersection of each scan line SLia and each data line DLja, and the intersection of each scan line SLib and each data line Dljb.

In this embodiment, in the structure shown in FIG. 2 , display pixels EM in odd rows are connected to scan lines SLia in each scan line group SGi, and display pixels EM in even rows are connected to scan lines SLib.

As shown in FIG. 2, regarding the number of rows corresponding to the scanning lines constituting each scanning line group SGi, the present invention is not limited to the structure in which each scanning line group SGi corresponds to two rows of display pixels EM. For example, a structure may be adopted in which each scanning line group SGi corresponds to k rows of display pixels EM (k is a divisor of the total number of rows n provided in the display panel 110), and it optionally has n/k groups ( That is, the above-mentioned n′ group) of scanning line groups, for example, a structure may be used in which one (single) scanning line group is provided in accordance with the rows (n rows) constituting the display panel 110A, and all display pixels EM on one screen share a common Connect to scanline group. In this case, all display pixels EM on one screen are collectively set to a selected state by a single scan signal output from the scan driver 120A.

Each display pixel EM has a gate terminal connected to each scan line SLia or SLib, and a source terminal connected to a drain terminal of each selection transistor Trsel, wherein the selection transistor is connected to each data line DLja and DLjb connection. Each display pixel EM includes a current control type light emitting element, and emits light having a predetermined luminance gradation based on the gradation current Ipix supplied from the current holding/distributing part 140 through each data line DLja or DLjb and the selection transistor Trsel.

In the display panel 110A having such a structure, by applying the scanning signal Vsel to a specific scanning line group SGi from a scanning driver 120A described later, with a plurality of (two) scanning lines SLia and The selection transistor Trsel connected to SLib is turned on synchronously, and the display pixels EM corresponding to multiple rows (two rows) are set to the selected state together. In the state (selected state) in which the scanning signal Vsel is applied to a specific scanning line group SGi, by transferring the gradation current Ipix corresponding to the display data from the current generating section 130 and the current holding/distributing section 140A described later, all at once Supplied to each data line group DGj, display data is written in display elements EM corresponding to a plurality of rows (two rows), wherein the display elements are simultaneously set to a selected state by the selection transistor Trsel being turned on. A specific circuit example or circuit operation of the display pixel EM including the selection transistor will be described in detail later.

(scan driver)

The scan driver 120A performs an operation of sequentially applying the scan signal Vsel at a selection level (for example, high level) to each scan line group SGi based on a scan control signal supplied from the system controller 150, and will correspond to a plurality of rows (this embodiment The display pixels EM of two rows in the center) are simultaneously set to the selected state, wherein the display pixels are connected to the scan lines SLia and SLib constituting each scan line group SGi. That is, for example, as shown in FIG. 2 , the scan driver 120A includes shift modules SB1, SB2, ... SBi, ... SBn', each of which includes shift blocks in multiple stages according to each scan line group SGi. Bit registers and buffers (in FIG. 2, n'=n/2; n is the total number of rows provided in the display panel 110A). When sequentially shifting from the upper portion to the lower portion of the display panel 110A, the shift register outputs shift signals based on scan control signals (scan start signal SST, scan clock signal SCK, and the like) provided by the system controller 150 described later. ), the shift signal is sequentially applied to each scan line group SGi through a buffer as a scan signal Vsel having a predetermined selection level (high level).

As described above, for example, when a structure in which all display pixels EM constituting the display panel 110A are connected to a single line group SGi is adopted, such a shift module as shown in FIG. signal, by applying a single scan signal Vsel to the scan line group SGi, all the display pixels EM on one screen are set to the selected state together.

(current generating part)

The current generation section 130 sequentially acquires display data supplied from a display signal generation section 160 described later based on a data control signal input from the system controller 150 at predetermined timing, wherein the display data corresponds to a plurality of lines in the data line group DGj (this Two rows in the embodiment) display pixels, the data line group DGj corresponds to the scan line group SGi to generate a signal current (level signal) Ic having a current value corresponding to the level value of the display data, and according to each column in the time series , sequentially supply the signal current Ic of a plurality of rows to the current holding/distributing section 140A. The current generation section 130 sequentially and repeatedly performs this operation for one screen. The specific structure and operation of the current generating section 130 will be described in detail later.

(Current Hold/Distribution Section)

The current holding/distributing section 140A sequentially acquires the signal current Ic of a plurality of lines supplied from the current generating section 130 in time series based on a data control signal input from the system controller 150 at a predetermined timing, wherein the lines correspond to each scanning line group SGi, the current holding/distributing part individually holds the signal current Ic according to a plurality of display pixels EM in each column of each data line group DGj, and by using the above-mentioned scan driver 120, according to setting each scan line group SGi At the timing of the selected state, the layer current Ipix based on the held signal current Ic is synchronously supplied to the display pixels EM of a plurality of rows (two rows in this embodiment) of each data line group DGj.

Specifically, for example, as shown in FIG. 2, the current holding/distributing section 140A includes at least a plurality of current distributing circuits 141, each provided in accordance with each data line group DGj arranged in the display panel 110A, and in accordance with each Each of the plurality of (two in this embodiment) data lines DLja and DLjb of the data line group DGi, in time series, distributes the signal current Ic supplied from the current generating section 130; and the plurality of current holding circuits 142, Each is provided to be connected to each data line group DGi arranged in the display panel 110A, and holds a signal current Ic in parallel corresponding to a plurality of lines distributed by the current distribution circuit 141 (in this embodiment, two) data lines.

This current holding/distributing section 140A sequentially acquires the signal current Ic of a plurality of lines (two lines in this embodiment) that are connected to the scanning lines SLia and SLib constituting each scanning line group SGi at timing based on the data control signal. connected, the current holding/distributing section distributes and holds the signal current Ic according to each data line in each data line group SGi. The section 140A also generates the gradation current Ipix based on the held signal current Ic, and supplies the gradation current Ipix synchronously to the rows ( In this embodiment, two rows) display pixels EM. The specific structure and operation of the current holding/distributing section 140A will be described in detail later.

(system controller)

The system controller 150 allows the scan driver 120A, the current generating section 130, and the current holding/distributing section 140A to operate at a predetermined timing to output the scan control signal and the data control signal controlling the operating state to the scan driver 120A and the current generating section 130, And output to the current holding/distributing part 140 through the current generating part 130, generate/output the scanning signal Vsel, the signal current Ic and the level current Ipix, and write the display data generated by the display signal generating part 160 into each display pixel EM to Light is emitted therefrom, and the display panel 110A is controlled to display predetermined image information based on a video signal.

(Show signal generation part)

The display signal generation section 160 extracts luminance gradation signal components from, for example, video signals supplied from outside the display device 100 for each row of the display panel 110A, and supplies the luminance gradation signal components to the current generation section 130 as display data. In this embodiment, when the video signal includes a timing signal component that defines the display timing of image information like a television broadcast signal (composite video signal), the display signal generation section 160 may have a function of extracting the luminance gradation signal component , and the function of extracting the timing signal components and providing them to the system controller 150 . In this case, the system controller 150 generates a scan control signal and a data control signal supplied to the scan driver 120A, and the current generation part 130 or the current holding/distribution part 140 is based on a timing signal provided from the display signal generation part 160 .

<Concrete example of current generating part>

A specific structural example of the current generating section that can be applied to the display device according to this embodiment will now be described.

FIG. 3 is a block diagram showing a structural example of a current generating section that can be applied to the display device according to this embodiment.

For example, as shown in FIG. 3 , the current generation section 130 includes a shift register circuit 131 , a data register circuit 132 , a data latch circuit 133 , a D/A converter 134 , and a voltage-current conversion/current source circuit 135 . The shift register circuit 131 outputs a shift signal, and simultaneously shifts the sampling start signal STR sequentially based on the shift clock signal CLK provided by the system controller 150 as a data control signal. The data register circuit 132 sequentially acquires one line of display data D0 to Dm (digital data) supplied from the display signal generating section 160 based on the input timing of the shift signal. The data latch circuit 133 holds one row of display data D0 to Dm acquired by the data register circuit 132 based on the data latch signal STB. The D/A converter 134 converts the held display data D0 to Dm into predetermined analog signal voltages (gradation voltage Vpix) based on gradation reference voltages V0 to Vp supplied from an unillustrated power supply device. The voltage-current conversion/current source circuit 135 generates a signal current (gradation signal) Ic corresponding to display data converted into an analog signal voltage, and in time series, according to each data line group DGj arranged in the display panel 110 , based on the output enable signal OE supplied from the system controller 150, for a plurality of rows connected to each scanning line group SGi, the signal current Ic corresponding to the display pixel EM in each column is sequentially supplied to the current holding/distributing section 140A .

<Specific example of current holding/distributing section>

A specific example of the current holding/distributing section, which can be applied to the display device according to this embodiment, will now be described.

FIG. 4 is a circuit configuration diagram showing a configuration example of a current holding/distribution section that can be applied to the display device according to this embodiment.

In this example, only a structural example is explained, which can be applied to the display device according to this embodiment, and the present invention is not limited to this circuit structure.

For example, as shown in FIG. 4, each current distribution circuit (signal distribution section) 141 constituting the current holding/distribution section 140A includes a switching transistor Tr41a and a switching transistor Tr41b. In the switching transistor Tr41a, the signal current Ic output from the current generating portion 130 is supplied to one end (source terminal) of the current path, and the other end (drain terminal) of the current path is connected to the second end (drain terminal) extending to the current holding circuit 142. An output contact N41a is connected, and the first current acquisition signal WTodd supplied from the system controller 150 as a data control signal is applied to the control terminal (gate terminal). In the switching transistor Tr41b, the signal current Ic output from the current generating section 130 is supplied to one end (source terminal) of the current path, and the other end (drain terminal) of the current path is connected to the second output terminal extending to the current holding circuit 142. The contact N41b is connected, and the second current acquisition signal WTevn supplied as a data control signal is applied to the control terminal (gate terminal).

Each current holding circuit 142 constituting the current holding/distributing section 140A has a structure in which the latch sections (signal holding/output sections) 142a and 142c on two stages are commonly connected with the latch sections (signal holding/output sections) on two stages ) 142b and 142d are provided in parallel, wherein 142a and 142c are commonly connected in parallel with the data line DLja, and the signal current Ic provided by the current distribution circuit 141 through the first output contact N41a is commonly provided to 142a and 142c, and 142b and 142d are jointly The ground is connected in parallel with the data line DLjb, and the signal current Ic supplied by the current distribution circuit 141 through the second output contact N41b is commonly supplied to 142b and 142d.

For example, as shown in FIG. 4, each latch portion 142a (or 142c) includes: a transistor Tr42a (or Tr42c) having a current flow connected between the output contact N41a of the current distribution circuit 141 and the contact N42a (or N42c). path (source-drain), and has a control terminal (gate) to which the first latch signal LCup (or second latch signal LClw) is applied; N42c) and the current path between the contact N43a (or N43c), and has a control terminal applied with the first latch signal LCup (or the second latch signal LClw); the transistor Tr44a (or Tr44c), one end of the current path It is connected to the contact N42a (or N42c), while a predetermined low potential voltage (-Vcc) is applied to its other end, and the control terminal is connected to the contact N43a (or N43c); the transistor Tr45a (or Tr45c), in which the current path One end is connected to the contact N42a (or N42c), while the other end is connected to the data line DLja, and the second latch signal LClw (or the first latch signal LCup) is applied to the control terminal; and the storage capacitor Ca (or Cc), Connected between the contact N43a (or N43c) and the low potential voltage (-Vcc).

For example, as shown in FIG. 4, similar to the latch portions 142a and 142c, each of the latch portions 142b (or 142d) includes: a transistor Tr42b (or Tr42d), wherein the current path (source-drain) is connected to the current distribution circuit 141 Between the output contact N41b and the contact N42b (or N42d), and the first latch signal LCup (or the second latch signal LClw) is applied to the control terminal (gate); the transistor Tr43b (or Tr43c), where the current path Connected between the contact N42b (or N42d) and the contact N43b (or N43d), and the first latch signal LCup (or the second latch signal LClw) is applied to the control terminal (gate); the transistor Tr44b (or Tr44d) , where one end of the current path is connected to the contact N42b (or N42d), while a predetermined low potential voltage (-Vcc) is applied to the other end, and the control terminal is connected to the contact N43b (or N43d); the transistor Tr45b (or Tr45d ), wherein one end of the current path is connected to the contact N42b (or N42d), while the other end thereof is connected to the data line DLjb, and the second latch signal LClw (or the first latch signal LCup) is applied to the control terminal; and the storage capacitor Cb (or Cd) is connected between the contact N43b (or N43d) and the low potential voltage (-Vcc).

In this embodiment, although the respective transistors Tr41a, Tr41b in the current distribution circuit according to this embodiment, and the respective transistors Tr42a to Tr45a, Tr42b to Tr45b, Tr42c to Tr45c, and Tr42d to Tr45d in the current holding circuit 142 are not limited to As a specific type, for example, an n-channel type field effect thin film transistor having an amorphous silicon layer as a channel layer, or a field effect thin film transistor having a polysilicon layer as a channel layer can also be applied. In this case, as shown in FIG. 2 , the current holding/distributing part 140A can be integrated with the pixel array on the insulating substrate BASE to form the display panel 110A. In addition, each of the storage capacitances Ca to Cd provided in the respective latch portions 142a to 142d may be a parasitic capacitance formed between the gate and the source of each transistor Tr44a to Tr44d or a separately provided capacitance element.

In the above current holding circuit 142, storage capacitors Ca to Cd constitute a signal holding portion and a charge storage circuit according to the present invention, and transistors Tr44a to Tr44d and Tr45a to Tr45d constitute a hierarchical current output portion according to the present invention.

<Operation of current holding/distributing section>

The operation of the current holding/distributing section having such a structure will now be described.

5A and 5B are conceptual diagrams showing conventional operations of the current holding/distributing section that can be applied to this embodiment.

In this instance, for the latch portions 142a to 142d constituting each current holding circuit 142, for the sake of convenience, illustration and description will be given on the side provided with the latch portions 142a and 142c, but when provided with One side of the latch portions 142b and 142d does the same.

The operation of the current holding/distributing section 140A (the current distribution circuit 141 and the current holding circuit 142) according to this embodiment has a current distribution operation of distributing the signal current (level signal) Ic which is supplied by the current distribution circuit 141 in time series In this case, based on display pixels written in a plurality of lines (two lines in this embodiment), the current generating portion 130 is supplied to the side of the output contact N41a and the side of the output contact N41b, where the display pixel lines correspond to the lines constituting the scan. Each of the scanning lines SLia and SLib of the line group SGi; in synchronization with the current distribution operation, in the latch sections 142a and 142b or the latch sections 142c and 142d constituting the current holding circuit 142, acquiring and holding the current of the distributed signal current Ic is performed Hold operation; and synchronously with the current hold operation, based on the signal current Ic held in the current hold operation, proceed from the other of the latch portions 142a and 142b and the latch portions 142c and 142d constituting the current hold circuit 142 to the constituent data line The respective data lines DLja and DLjb of the group DGj synchronize the current output operation of the output stage current Ipix. The current holding operation and the current output operation are controlled to be selectively repeatedly performed between the latch portions 142a and 142b and the latch portions 42c and 142d constituting the current holding circuit 142, while being repeated in accordance with all scanning line groups SGi in the display panel 110A. current distribution operation.

That is, within a period in which the signal current Ic supplied from the current generation portion 130 is acquired and held on one side of the latch portion constituting the current holding circuit 142 based on the display data in accordance with each column, simultaneously on the other side of the latch portion Reads and outputs the stage current Ipix. Thus, operations of acquiring the signal current Ic based on the display data and outputting the gradation current Ipix to the data line group DGj of each column are basically performed.

Each operation will now be specifically described with reference to each circuit configuration of the current holding/distributing section.

(current distribution operation)

In the current distribution operation, in the current distribution circuit 141, the switches Tr41a and One of Tr41b is sequentially turned on, and corresponding to the signal current Ic of the display pixels EM in each row, in time series, is output from the current generating section 130 in synchronization with the timing of turning on the switches. As a result, the signal current Ic is distributed according to each row, and output to individual latch portions 142a and 142c or 142b and 142d constituting the current holding portion 142 described later through each output contact N41a or N41b.

(current hold operation/current output operation)

In the current holding circuit 142 (the latch sections 142a to 142d), by selectively setting the first and second latch signals LCup and LClw supplied from the system controller 150 to the upper stage as data control signals, the contact with the output trigger is performed. One of the latch portions 142a and 142c connected in parallel to the point N41a, and the latch portions 142b and 142d connected in parallel to the output contact N41b (the latch portions 142a and 142b or the latch portions 142c and 142d) is set to the current hold operation state, Whereas, the remaining latch portions (the latch portions 142c and 142d or the latch portions 142a and 142b) are set to a current output operation state described later.

In the current hold operation, as shown in FIG. 5A (the latch portions 142a and 142c are shown separately for convenience), the first latch signal LCup is set to a high level and the second latch signal LClw is set to a low level. As a result, in the latch portion 142a connected to the output contact N41a, the transistors Tr42a, Tr43a, and Tr44a are turned on, and the transistor Tr45a is turned off. At this time, since the portion between the gate and the drain of the transistor Tr44a is electrically short-circuited by the transistor Tr43a, the transistor Tr44a operates in a saturation region. Therefore, the signal current Ic supplied from the current generation section 130 and output to the output contact N41a through the switch Tr41a of the current distribution circuit 141 flows to the low potential voltage (-Vcc) side through the transistors Tr42a and Tr44a of the latch section 142a , and the current level of the signal current Ic is converted to a voltage level between the gate and source of the transistor Tr44a, so that the signal current Ic is stored in the storage capacitor Ca as charges.

In the current output operation, as shown in FIG. 5B , the first latch signal LCup is set to a low level, and the second latch signal LClw is set to a high level. As a result, in the latch portion 142a, the transistors Tr42a and Tr43a are turned off, and the transistor Tr45a is turned on. At this time, the potential (high voltage) based on the charge (signal current Ic) stored in the storage capacitor Ca by the current holding operation is held in the contact N43a, so the transistor Tr44a continues to operate on. Therefore, the data line DLja arranged in the display panel 110 (not shown) is connected to the low-potential voltage (-Vcc) through the transistors Tr45a and Tr44a of the latch portion 142a, and the layer current Ipix flows in such a manner that from the data The side of the line DLja (that is, the side of the display pixel EM) is pulled toward the latch portion 142a (the current holding circuit 142).

In addition, in a state where the first latch signal LCup is set to a low level and the second latch signal LClw is set to a high level (that is, the current output operation state of the above-mentioned latch portion 142a), the transistors Tr42c and Tr43c are turned on, and the transistor The portion between the gate and drain of Tr44c is electrically short-circuited by the transistor Tr43a, so that in the latch portion 142c connected in parallel to the output contact N41a, the transistor Tr44c is turned on in the saturation region, and the transistor Tr45c is turned off. Therefore, the signal current Ic output to the output contact N41a flows to the low potential voltage (-Vcc) side through the transistors Tr42c and Tr44c of the latch portion 142c, and the current level of the signal current Ic is switched to the gate and source of the transistor Tr44c The voltage level between makes the signal current Ic stored in the storage capacitor Cc as charge.

That is, during a period in which one of the latch portions 142a and 142c is set to the current holding operation state, the other is synchronously set to the current output operation state. Such an operation state is also performed in the unillustrated combination of the latch portions 142b and 142d.

The description has been given about an example in which a function (current polarity inversion section) is provided to generate (invert the current direction) the negative layer current Ipix corresponding to the signal current Ic having positive polarity supplied from the current generation section 130, and from The data line (display pixel) side pulls the layer current Ipix to cope with the circuit structure of a pixel driving circuit described later that is supplied to the display pixels EM in the current holding/distributing section 140A according to this embodiment. However, the present invention is not limited thereto, and may have a structure in which the tier current Ipix having positive polarity is generated, and the tier current Ipix passes through the data line (display pixel) depending on the circuit structure of the display pixel EM.

Note that almost all known current drive circuits (corresponding to the current generation part) distributed and available on the market have a structure that outputs a hierarchical signal (signal current) having a positive polarity, and thus by applying the current holding/distribution with the above structure part, the layer currents whose current direction is reversed can be easily generated by known current drivers.

<Drive Control Method of Display Device>

The drive control operation (drive control method) in the display device having the above structure will now be described.

FIG. 6 is a timing chart illustrating a drive control operation (drive control method) in the display device according to this embodiment.

In this example, a description will be given with reference to each structure of the display device described above.

In the display device having the above-mentioned structure, by using the display signal generation section 160, display data including digital data that allows each display pixel (light emitting element) EM constituting the display panel 110A is first extracted from the video signal Light having a predetermined brightness level is emitted, and the extracted display data is sequentially supplied to the current generation part 130 as serial data corresponding to each row of the display panel 110A.

The display data (digital data) supplied to the current generating section 130 is converted into a signal current (gradation signal) Ic corresponding to the display data at a timing based on a data control signal input by the system controller 150, and output to the display data according to the arrangement The current holding/distributing part 140A is provided for each data line group DGj in the display panel 110A.

In this instance, for example, according to each row of the respective display pixels EM connected to the respective data lines DLja and DLjb constituting the data line group DGj, the signal current Ic output from the current generating portion 130 is, in time series, corresponding to The data line group DGj of each column in the display panel 110A is output as a unit.

As shown in FIG. 6, the current distribution operation is performed in the current holding/distribution section 140A. In the current distribution operation, the signal current Ic corresponding to the display pixels EM arranged in a plurality of rows (two rows in this embodiment) according to each column is sequentially acquired based on data supplied from the system controller 150. Timing of control signals (first and second current acquisition signals WTodd and WTevn), selectively turning on transistors or switches Tr41a and Tr41b of the current distribution circuit 141, the signal current Ic is sequentially supplied to the latch portion 142a of the current holding circuit 142 (or 142c) and latch portion 142b (or 142d).

Next, in synchronization with this timing, the latch portions 142a and 142b of the current holding circuit 142 are set to current remain operational. As a result, the current holding operation is sequentially performed only during the period in which the signal current Ic is supplied to the respective latch portions 142a and 142b. In the current holding operation, charges based on the signal current Ic corresponding to the display pixels EM in the respective rows (for example, the first row and the second row) are stored in the respective storage capacitors Ca and Cb.

As shown in FIG. 6, along with appropriately setting the signal levels of the first and second current acquisition signals WTodd and WTevn and the first and second latch signals LCup and LClw, in the latch sections 142a and 142b and the latch sections 142c and 142d Such current distribution operation and current holding operation are optionally repeated. Therefore, the signal current Ic corresponding to the display pixels EM based on the display data in two rows is sequentially held in each current holding circuit 142 .

Subsequently, after the current holding operation, based on the data control signals (low-level first latch signal LCup and high-level second latch signal LClw) provided from the system controller 150, the latch portions 142a and 142b of the current holding circuit 142 are set to Current output operating status. As a result, current output operations are performed in the respective latch portions 142a and 142b. In the current output operation, the layer current Ipix is synchronously supplied to the display pixels EM in each row (for example, the first row and the second row) through the respective data lines DLja and DLjb constituting the data line group DGj, wherein the layer current Ipix Based on the charges stored in the respective storage capacitors Ca and Cb.

Therefore, the layer current Ipix is output from the current holding/distributing section 140A through the data line group DGj of each column, and the high-level scan signal Vsel is applied from the scan driver 120A to specific The scanline group SGi. As a result, all the selection transistors Trsel connected to the respective scan lines SLia and SLib constituting this scan line group SGi are turned on, and are supplied to multiple rows (for example, including the first row) through the data lines DLja and DLjb of each data line group DGj. The gradation current Ipix of the display pixels EM in two rows) is written into each display pixel EM, thereby performing a light emitting operation with a predetermined brightness gradation based on the gradation current Ipix.

In addition, in each of the latch sections 142a and 142b, during the period in which the current output operation is performed, as shown in FIG. signal LClw), the latch portions 142c and 142d of the current holding circuit 142 are set to the current holding operation state. As a result, current holding operations are sequentially performed. In this operation, in the respective latch portions 142c and 142d, the signal current Ic for each row continuously supplied from the current generation portion 130 is acquired, and charges based on the signal current Ic are stored in the respective storage capacitors Cc and Cd, wherein the signal current Corresponds to the display pixels EM in the respective rows (for example, the third row and the fourth row).

Next, after the current output operation in the latch parts 142a and 142b, the system controller 150 again sets the first latch signal LCup to a high level and the second latch signal LClw to a low level. As a result, the latch portions 142a and 142b are set again to the current hold operation state. Accordingly, a current output operation is performed in each of the latch portions 142a and 142b. In the current output operation, charges based on the signal current Ic corresponding to the display pixels EM in the respective rows (for example, the fifth row and the sixth row) are stored in the respective capacitors Ca and Cb.

In addition, at this time, when the latch portions 142c and 142d of the current holding circuit 142 are set to the current output operation state, a current output operation is performed in which the charge-based layer current Ipix passes through the respective data lines DLja constituting the data line group DGj. and DLjb, are synchronously supplied to the display pixels EM in the respective rows (for example, the third row and the fourth row), in which charges are stored in the respective storage capacitors Cc and Cd at the aforementioned timing.

As a result, in the latch sections 142a and 142b and the latch sections 142c and 142d on two stages constituting each current holding circuit 142 which is provided according to each column in the current holding/distributing section 140A, according to a predetermined operation cycle, The control to perform the current holding operation and the current output operation synchronously is repeated alternately. Accordingly, an operation is performed in which the signal current Ic corresponding to each row of display data output by the current generating section 130 is continuously acquired and held in the current holding circuit, and is synchronously supplied to display pixels in a plurality of rows as the gradation current Ipix.

Therefore, this embodiment is constructed in such a manner that by applying a single scan signal from a scan driver to a display panel in which a plurality of display pixels are two-dimensionally arranged, display in multiple lines (two lines in this embodiment) The pixels are collectively set to the selected state, and, at a predetermined timing (for example, one scanning period), display data corresponding to display pixels in a plurality of rows are sequentially acquired and held by a signal driver, while gradation currents corresponding to a plurality of rows are provided synchronously to each display pixel. Therefore, compared with the known drive control method of applying one scan signal to one scan line, the number of scan lines driven at a single scan timing (the number of rows of display pixels to be selected) becomes several times, and the display pixel The time required to write the gradation current in can basically be set several times (twice in this embodiment).

In addition, since the data lines arranged in each column are formed into a data line group in which a plurality of (two in this embodiment) data lines are determined as a group, compared to the known display in which one data line is arranged in one column The structure of the device can greatly reduce (1/2 in this embodiment) the capacitive component including the holding capacitor parasitic on each data line and existing in each display pixel, or the parasitic capacitance of the driving transistor. Therefore, the time required to write the layer current supplied to each data line in each display pixel can be reduced, or the delay in this writing time can be suppressed.

As a result, a sufficiently long time for writing display data in each display pixel can be secured. Therefore, when the display panel is increased in size or realizes high definition, or even when displaying an image at a low level, the wiring capacitance of the data line can be satisfactorily charged to a predetermined voltage, thereby eliminating insufficient writing of display data state. In addition, each display pixel can be allowed to emit light with an appropriate gradation of luminance corresponding to display data, and luminance gradation (display irregularity) generated in the display panel can be greatly reduced, thereby improving display image quality.

The present invention is constituted in such a manner that scanning lines arranged in rows are formed into a scanning line group in which a plurality of (two in this embodiment) scanning lines are determined as a group, and by using a single scanning signal, a plurality of rows The display pixels (two rows in this embodiment) are set to the selected state together. Therefore, the number of scan signals output from the scan driver to the display panel can be greatly reduced (1/2 in this embodiment), and the number of connection terminals between the display panel and the scan driver can be greatly reduced (in this embodiment is 1/2). As a result, even if high definition is realized in the display panel, the increase in the number of output terminals of the driver chip can be suppressed, and the pitch (gap) between the terminals can be prevented from becoming small, thereby simplifying the positional accuracy of the connection step of the driver chip, Or reduce the number of steps.

In addition, when a field effect thin film transistor with an amorphous silicon layer or a polysilicon layer as a channel layer is applied as each transistor constituting the current holding/distributing part, the current holding/distributing part can be integrated on the same substrate as the display panel (pixel array) , and an increase in the number of devices can be suppressed, thereby keeping the production cost of the display device down.

The example has been described above in which the scan line groups are arranged to correspond to, for example, display pixels in two rows, and the data line groups corresponding to the display pixels in two rows are arranged so that by using a single scan signal, two rows The display pixels in can be synchronously set to the selected state as a first embodiment of the display device according to this embodiment. However, the present invention is not limited thereto. Another structural example of the display device according to this embodiment will now be described.

FIG. 7 is a schematic configuration diagram of main parts showing another configuration example of the display device according to this embodiment.

FIG. 8 is a schematic configuration diagram of main parts showing still another configuration example of the display device according to this embodiment.

That is, for example, as shown in FIG. 7, the display panel 110A may be configured to have each scanning line group SGi arranged to correspond to two or more rows (four rows), and each data line group DLj, where The data line group includes a plurality (four) of data lines DLja to DLjd, the number (four) of which corresponds to a plurality of rows, and is arranged according to each pixel row. By using a single scan signal Vsel, display pixels EM in multiple rows (four rows) can be simultaneously set to the selected state.

In addition, as shown in FIG. 8 , as a structure (layout format of scanning lines) of one scanning line group arranged to correspond to a plurality of rows, for example, it may not be drawn (transition direction) within the display panel 110A One scan line SLi is commonly connected to display pixels EM in multiple rows (two rows).

<Second Example of Display Device>

A second embodiment of a display device according to the present invention will now be described with reference to the accompanying drawings.

FIG. 9 is a structural diagram showing a main part of a second embodiment of a display device according to the present invention.

Here, structures equivalent to those in the first embodiment are denoted by the same or similar reference numerals, and thus explanations thereof are omitted.

The display device according to the first embodiment described above includes: a display panel in which each scanning line group SGi corresponding to a plurality of rows and each data line group DGj including a plurality of data lines corresponding to a plurality of rows are arranged; In the peripheral circuit of the display panel (scan driver and signal driver including the current generating part and the current holding/distributing part). A display device according to the second embodiment includes: a display panel in which each scanning line provided in accordance with each row is arranged, and each data line group including a plurality of data lines corresponding to a plurality of rows; Peripheral circuits (scan driver and signal driver including current generating part and current holding/distributing part).

As shown in FIG. 9 , the display panel 110B according to this embodiment generally includes: a plurality of display pixels EM arranged two-dimensionally (n rows×m columns) and connected to each other through selection transistors Trsel; A plurality of scanning lines SLq arranged (q is a positive integer falling within the range of 1≤q≤n; n is a positive integer, and is the total number of rows of pixels set in the display panel 110); and a plurality of data line groups DGj , arranged according to the display pixels EM in each column, and wherein a plurality of (two in this embodiment) data lines DLja and DLjb (j is a positive integer falling within the range 1≤j≤m; m is a positive integer , and is the total number of columns of pixels set in the display panel 110 ) is determined as a group. Each display pixel EM is disposed at each intersection of the scan line SLq and the data lines DLja and DLjb constituting each data line group DGj.

The scan driver (selection circuit) 120B is generally connected to the scan lines SLq in the display panel 110B, and at a predetermined timing, sequentially applies the scan signal Vsel to each scan line SLq to connect each row (one row) to the scan line SLi. The display pixels EM in turn are set to the selected state.

The current generating section 130 generally generates a signal current (gradation signal) Ic having a current value corresponding to a luminance gradation value based on the display data according to display data supplied from the display signal generating section 160 .

The current holding/distributing part 140B is generally connected with each data line group DGj in the display panel 110B. The section 140B acquires the signal current Ic supplied from the current generating section 130 corresponding to each row (two rows in this embodiment) in time series, and sequentially applies the gradation current Ipix based on the signal current Ic to multiple rows at predetermined timing. The pixels EM are displayed in a row (two rows in this embodiment). In this embodiment, the current generating section 130 and the current holding/distributing section 140B constitute a signal driver 200B.

Note that, in the structure shown in FIG. 9 , the current holding/distributing portion 140B is integrated with the pixel array on the insulating substrate BASE, wherein a plurality of display pixels EM (that is, a pixel array) constituting the display panel 110B are formed on the insulating substrate BASE. substrate as an example of structure, but the present invention is not limited thereto. For example, the signal driver 200B may have the configuration of a driver chip and be mounted (packaged) on the substrate BASE. Details will be described later.

The specific configuration of each structure will now be described.

(display panel)

For example, as shown in FIG. 9, the display panel 110 has a structure that can be applied to the display device according to this embodiment, and in this structure, each scanning line corresponding to each pixel row SLq and each data line group DGj having two data lines DLja and DLjb are determined as a group and correspond to a pixel column, the above-mentioned scan lines and data lines are arranged to be perpendicular to each other, and the display pixels EM and the odd scan lines SLi and the intersections of the data lines DLja in each column, and the intersections of the even scan lines SLi and the data lines DLjb in each column.

In this embodiment, in the structure shown in FIG. 9, although the data line group DGj arranged in each column is configured to have two data lines DLja and DLjb determined as one group, the present invention is not limited thereto, and Two or more data lines can be identified as a group. In this case, when the number of data lines constituting the data line group DGj is q (that is, the number of data lines DLj1 to DLjq is q), a structure is provided in which the display pixels EM are connected to the scanning lines in each row. It is connected with the intersection point of the first data line DLj1 in each column, wherein the line can be calculated by dividing the number of lines with q and leaving 1 (the first, q+1, 2q+1, ... every line of the line scan lines), the display pixel EM is connected to the intersection of the scan line in each row and the second data line DLj2 in each column, wherein the row can be calculated in the same way with a remainder of 2 (the second, the qth +2, 2q+2, ... each scan line of the row), the display pixel and the data line are connected in the same relationship, and the display pixel EM is connected to the scan line in each row and the qth (last) in each column Intersection connections of data lines DLjq, which can be calculated in the same way with remainder 0 (each scan line of the qth, 2q, 3q, . . . row).

In addition, like the display pixel EM in FIG. 2, each display pixel EM generally has a structure in which a gate terminal is connected to each scanning line SLi, and a source terminal is connected to each data line DLja or DLjb. The drain terminal of the selection transistor Trsel is connected, and includes a current control type light emitting element in which light having a predetermined luminance gradation is emitted based on the gradation current Ipix supplied through the selection transistor Trsel.

In the display panel 110B having such a structure, by applying a scan signal Vsel to a scan line SLi in a specific row from a scan driver 120B described later, the selected transistor Trsel connected to this scan line SLi is turned on, and The display pixels EM in this row are collectively set to the selected state. In this selected state, when the gradation current Ipix corresponding to the display data is synchronously supplied to a specific data line in each data line group DGj, the display data is synchronously written into this through the selection transistor Trsel which has been turned on. Among the display pixels in the row that are set to the selected state.

(scan driver)

The scan driver 120B sequentially performs the application of the scan signal Vsel of the selection level (that is, high level) to each scan line SLq based on the scan control signal provided by the system controller 150, so that the display connected to each scan line SLi in each row The pixels EM are synchronously set to the selected state, and at least display pixels EM in adjacent rows are synchronously set to the selected state within a predetermined period. That is to say, for example, as shown in FIG. 9 , the scan driver 120 includes shift modules SB1, SB2, . . . , SBi, . n stages) each shift module includes a shift register and a buffer. Through the shift register, a shift signal output when sequentially shifted from the upper part to the lower part in the display panel 110 is applied to each scanning line SLq through each buffer as a scanning signal Vsel having a predetermined selection level (high level). , wherein the scan level is based on scan control signals provided by the system controller 150 (scan start signal SST, scan clock signal SCK and the like). Here, in this embodiment, in the scan driver having the above-mentioned structure, for example, the scan clock signal SCK is set to a regular time width, wherein the time width is set within a predetermined period (one horizontal scan period) per row The selected state (the selection time width of each row to which the scan signal Vsel is applied), and the scan start signal SST is set to the selection time width of two lines (two horizontal scan periods). As a result, a shift signal having a time width of two lines is shifted between the respective shift blocks SB1, SB2, ..., SBi, ... SBn, and within a predetermined period, the scan signal Vsel based on the shift signal , applied to at least adjacent scan lines SLi in an overlapping manner.

(current generating part)

The current generating section 130 has the same structure as the current generating section 130 in the first embodiment shown in FIG. 3, and performs operations repeatedly for one screen in sequence. In this operation, the current generating section 130 sequentially acquires display data corresponding to a plurality of rows (two rows in this embodiment) of display pixels in each data line group DGj at predetermined timing, based on the system controller The data control signal input by 150, the display data is provided by the display signal generation part 160, and a signal current (gradation signal) Ic having a current value corresponding to the brightness gradation value of the display data is generated, and is sent to The current holding/distributing section 140B sequentially supplies the signal current Ic of a plurality of lines.

(Current Hold/Distribution Section)

The current holding/distributing section 140B sequentially acquires and holds the multi-line signal current Ic corresponding to each data line group DGj at predetermined timing, wherein in time series, based on the data control signal input by the system controller 150, the current generating section 130 supply the signal current. The portion 140B synchronously supplies the signal current Ic as the layer current Ipix to the display pixels EM in each row, wherein the display pixels are set to the selected state by each data line group DGj.

Specifically, for example, as shown in FIG. 9 , the current holding/distributing section 140B includes at least a plurality of current holding/distributing circuits 143 provided in accordance with the respective data line groups DGj arranged in the display panel 110B. In addition, the current holding/distributing section 140B, at the timing of setting each scanning line SLq to the selected state, according to a plurality of (two in this embodiment) data lines DLja and DLjb in each data line group DGj , distributes and holds the signal current Ic supplied from the current generating part 130 in time series, and sequentially supplies the layer current Ipix based on the held signal current Ic to the display pixels EM of the respective data lines DLja and DLjb.

Note that the specific structure and operation of the current holding/distributing section 140B will be described in detail later.

<Specific example of current holding/distributing section>

A specific example of the current holding/distributing section that can be applied to the display device according to this embodiment will now be described.

FIG. 10 is a circuit configuration diagram showing a configuration example of a current holding/distributing section that can be applied to the display device according to this embodiment.

Note that only a structural example applicable to the display device according to this embodiment is described here, and the present invention is not limited to this example.

Each of the current holding/distributing circuits 143 constituting the current holding/distributing section 140B is configured, for example, as shown in FIG. Hold/output portion) 143a and latch portion (signal hold/output portion) 143b connected to data line DLjb, these portions 143a and 143b are commonly connected in parallel to supply signal current Ic output from current generating portion 130. The data lines DLja and DLjb constitute each data line group DGj.

For example, as shown in FIG. 10, the current holding/distributing section 143a includes a transistor Tr46a in which the signal current Ic output by the current generating section 130 is supplied to one end (source or drain) of the current path, and the other end thereof is connected to the contact N46a , the first current acquisition signal WTodd is applied to the control terminal (gate); the transistor Tr47a, wherein the current path is connected between the contact N46a and the contact N47a, the first current acquisition signal WTodd is applied to the control terminal; the transistor Tr48a, One end of the current path is connected to the contact N46a, the other end is connected to the low potential voltage (-Vcc), the control terminal is connected to the contact N47a; the transistor Tr49a, one end of the current path is connected to the low potential voltage (-Vcc) connection, the other end of which is connected to the data line DLja, the control terminal is connected to the contact N47a; and the storage capacitor Ce is connected between the contact N47a and the low potential voltage (-Vcc).

In addition, the current holding/distributing part 143b also includes, for example, as shown in FIG. The point N46b is connected, the second current acquisition signal WTevn is applied to the control terminal (gate); the transistor Tr47b, wherein the current path is connected between the contact N46b and the contact N47b, the second current acquisition signal WTevn is applied to the control terminal; Transistor Tr48b, one end of the current path is connected to the contact N46b, the other end is connected to the low potential voltage (-Vcc), and the control terminal is connected to the contact N47b; the transistor Tr49b, one end of the current path is connected to the low potential voltage (-Vcc). Vcc) connection, the other end of which is connected to the data line DLjb, the control terminal is connected to the contact N47b; and the storage capacitor Cf is connected between the contact N47b and the low potential voltage (-Vcc).

Here, in the current holding/distributing portion 140B according to this embodiment, for example, an n-channel type field effect thin film transistor having an amorphous silicon layer as a channel layer, or a field effect thin film transistor having a polysilicon layer as a channel layer, may be Applied as each of the transistors Tr46a to Tr49a and Tr46b to Tr49b. In this case, as shown in FIG. 9 , the current holding/distributing part 140B may be integrated with the pixel array on the insulating substrate BASE constituting the display panel 110B.

In addition, each storage capacitance Ce and Cf provided to the respective latch portions 143a and 143b may be a parasitic capacitance formed between the gate and source of each transistor Tr49a and 49b, or a capacitance element provided separately.

In the current holding/distributing circuit 143, storage capacitors Ce and Cf constitute a signal holding portion and a charge storage circuit according to the present invention, transistors Tr46a, Tr47a, Tr46b, and Tr47b constitute a signal distributing portion according to the present invention, and transistors Tr48a, Tr49a, Tr48b and Tr49b constitute the hierarchical current output section according to the present invention.

Now, the current holding/distributing portion of the present invention having the above structure will be explained.

11A and 11B are conceptual diagrams showing conventional operations of the current holding/distributing section that can be applied to this embodiment.

The operation of the current holding/distributing section 140B (current holding/distributing circuit 143) according to this embodiment has a current holding/output operation, which is sequentially acquired in time series by the respective latch sections 143a and 143b of the current holding/distributing circuit 143 The gradation current Ipix is generated based on the signal current Ic based on the display data corresponding to the display pixels in two rows supplied from the current generating section based on the signal current (gradation signal) Ic, and is supplied to the constituting data line group at a predetermined timing. The respective data lines DLja and DLjb of the DGj individually output the generated signal; and a current output hold operation, continuously outputting the layer current Ipix in the current hold/output operation for a predetermined period. The current holding/distributing section 140B is controlled to alternately repeat the current holding/output operation and the current output holding operation at partially overlapping periods between the parallel-connected latch sections 143a and 143b. As a result, the output periods of the layer current Ipix output from the respective latch portions 143a and 143b in the current holding/output operation can be set to partially overlap.

This operation will now be specifically described with reference to each circuit configuration in the current holding/distributing section.

In the current holding/dividing circuit 143 (latch sections 143a and 143b), the first and second current acquisition signals WTodd and WTevn supplied from the system controller 150 as data control signals are selectively set to high levels. As a result, one of the latch portions 143a and 143b (the latch portion 143a or 143b) is set to a current hold/output operation state in which the signal current Ic is acquired and the layer current Ipix corresponding to the signal current Ic is output, while the other latch portion (The latch portion 143b or 143a) is set to the current output hold operation state in which the output state of the layer current Ipix in the aforementioned timing current hold/output operation state is continued.

Specifically, in the current hold/output operation, as shown in FIG. 11A , the first current acquisition signal WTodd is set to a high level, and the second current acquisition signal WTevn is set to a low level. As a result, in the latch portion 143a, the transistors Tr46a and Tr47a are turned on, the portion between the gate and the drain of the transistor Tr48a is electrically short-circuited by the transistor Tr47a, and thus the transistor Tr48a is turned on in the saturation region. As a result, the signal current (gradation signal) Ic supplied from the current generation section 130 flows to the low potential voltage (-Vcc) side through the transistors Tr46a and Tr48a of the latch section 143a, and the current level of the signal current Ic is converted to that of the transistor Tr48a. The voltage level between the gate and the source, so that the signal current Ic is stored as charge in the storage capacitor Ce.

At this time, as charges are stored in the storage capacitor Ce, the transistors Tr48a and Tr49a constituting the current mirror circuit are turned on by an increase in the potential at the contact point N47a, and the layer current Ipix flows in such a manner that the layer current Ipix Through the transistor Tr49a, it is pulled from the data line D1ja side to the low potential voltage (-Vcc) direction (that is, from the display pixel EM side to the latch portion 143a), wherein the layer current has a current in the current relative to the signal current Ic. Predetermined current ratio set in the mirror circuit.

In the current output hold operation, as shown in FIG. 11B , the first current acquisition signal WTodd is set to a low level, and the second current acquisition signal WTevn is set to a high level. As a result, in the latch portion 143a, the transistors Tr46a and Tr47a are turned off. At this time, since the potential (high voltage) based on the charge (signal current Ic) stored in the storage capacitor Ca is held at the contact N47a by the current hold/output operation, the transistor Tr49a continues the ON state. Therefore, the operation state in which the layer current Ipix is pulled from the data line DLja side toward the latch portion 143a (current holding/distributing circuit 143) is maintained.

Also, in a state where the first current acquisition signal WTodd is set to a low level and the second current acquisition signal WTevn is set to a high level (that is, the current output of the above-described latch portion 143a maintains an operating state), the transistors Tr46b and Tr47b are Turning on, the portion between the gate and drain of the transistor Tr48b is electrically short-circuited by the transistor Tr47b, so that the transistor Tr48b is turned on in the saturation region in the latch portion 143b connected in parallel to the latch portion 143a. Therefore, a current hold/output operation is performed. In this operation, the signal current Ic flows to the low voltage potential (-Vcc) through the transistors Tr46b and Tr48b of the latch portion 143b, the current level of the signal current Ic is converted to a voltage level between the gate and source of the transistor Tr48b, The signal current Ic is stored as charge in the storage capacitor Cf. In addition, as the potential at the contact point N47b increases, the transistors Tr48b and Tr49b constituting the current mirror circuit are turned on, and the layer current Ipix flows in such a manner that the layer current Ipix is transferred from the data line DLjb through the transistor Tr49b. One side is pulled toward the low potential voltage (-Vcc) side (that is, from the display pixel EM side toward the latch portion 143b), where the layer current Ipix has a predetermined current ratio with respect to the signal current Ic.

That is, during a period in which one of the latch portions 143a and 143b is set to the current hold/output operation state, the other portion is simultaneously set to the current output hold operation state.

Note that the description has been given regarding the example in which the negative layer current Ipix corresponding to the signal current Ic having a positive polarity supplied from the current generating section 130 is generated, and is fed from the data line in the current holding/distributing section 140B. The (display pixel) side pulls the layer current Ipix to cope with the circuit structure of the pixel driving circuit provided in the display pixel EM described later. However, the current holding/distributing portion 140B may have a structure in which the tier current Ipix having positive polarity is generated, and the tier current Ipix passes through the data line (display pixel) depending on the circuit structure of the display pixel EM.

<Drive Control Method of Display Device>

The drive control operation in the display device having the above structure will now be explained.

FIG. 12 is a timing chart showing a driving control method of the display device according to this embodiment.

In the display device having the above structure, display data including digital data for making each display pixel (light emitting element) EM constituting the display panel 110B have a predetermined Brightness levels, the extracted display data are then sequentially supplied to the current generation part 130 as serial data corresponding to each row of the display panel 110B.

At the timing based on the data control signal input from the system controller 150, the display data supplied to the current generating section 130 is converted into a signal current (gradation signal) corresponding to the display data, and output to each of the display panels arranged in the display panel 110B according to the timing. The current holding/distributing part 140B is provided for the data line group DGj.

In the current holding/distributing section 140B, as shown in FIG. The latch portion 143a of 143 is set to a current hold/output operation state. As a result, a current hold/output operation is performed. In this operation, the signal current Ic corresponding to the display pixel EM in each column is acquired for one row (for example, the first row), and charges based on the signal current Ic are stored in the storage capacitor Ce. At the same time, based on the charge stored in the storage capacitor Ce and the current ratio set by the current mirror circuit (transistors Tr48a and Tr49a), a layer current Ipix having a predetermined current value is generated, and the generated layer current Ipix is passed through each data line DLja , provided to each display pixel EM in this row (the first row).

Then, after the current holding/output operation, based on the data control signals (the low-level first current acquisition signal WTodd and the high-level second current acquisition signal WTevn) supplied from the system controller 150, the latch portion 143a of the current holding/distributing circuit 143 is set to maintain the operating state of the current output. As a result, a current output hold operation is performed. In this operation, through each data line DLja in the latch portion 143a, the layer current Ipix based on the charge stored in the storage capacitor Ce (that is, the signal current Ic) is continuously supplied to the data lines in this row (the first row). Each display pixel EM.

On the other hand, as shown in FIG. 12, in the latch portion 143a, during the period in which the current output holding operation is performed, based on the data control signals (low-level first current acquisition signal WTodd and high-level second current acquisition signal WTodd) supplied from the system controller 150, current acquisition signal WTevn), the latch portion 143b of the current holding/distributing circuit 143 is set to the current holding/output operation. As a result, a current hold/output operation is performed. In this operation, the signal current Ic for the next row (for example, the second row) continuously supplied by the current generation part 130 is taken in the latch part 143b, and the charge is stored in the storage capacitor Cf. Simultaneously, based on the charge stored in the storage capacitor Cf and the current ratio set by the current mirror circuit (transistors Tr48b and Tr49b), a layer current Ipix having a predetermined current value is generated, and the generated layer current Ipix is then supplied to this row ( Each display pixel EM in the second row).

Next, the system controller 150 sets the first current acquisition signal WTodd to a high level and the second current acquisition signal WTevn to a low level again after the current output in the latch portion 143a maintains operation. As a result, the latch portion 143a is set again to the current hold/output operation state. Therefore, a current hold/output operation is performed. In this operation, charges based on the signal current Ic for the next row (for example, the third row) are stored in the storage capacitor Ce. At the same time, the layer current Ipix based on the charge stored in the storage capacitor Ce and the current ratio set by the current mirror circuit is supplied to each display pixel in this row (the third row) through each data line DLja.

In addition, at this time, when the latch portion 142b of the current holding/distributing portion 143 is set to the current output holding operation state, the current output holding operation is performed. In this operation, the layer current Ipix based on the charge stored in the storage capacitor Cf at the aforementioned timing is supplied to each display pixel EM of one row through each data line DLjb, which is an object of the current holding/output operation (second line).

As a result, in the current holding/distributing section 140B, the simultaneous execution of the current holding/output operation and the current output holding operation is alternately repeated with a predetermined operation period between the latch sections 143a and 143b on two stages provided in accordance with each column. control, wherein the latch portion constitutes each current holding/dividing circuit 143. As a result, an operation is performed in which, in the current holding circuit, the signal current Ic sequentially supplied from the current generating section 130 corresponding to each row of display data is continuously acquired and held, and at the same time, the signal current Ic is synchronously supplied to the display in each row pixel, as the layer current Ipix.

Therefore, the gradation current Ipix is output from the current holding/distributing section 140B through the data line group DLj of each column, and the high-level scanning signal Vsel, within a predetermined period, at timing based on the scanning control signal supplied from the system controller 150, at The overlap mode is applied from the scan driver 120 to at least adjacent scan lines SLq. As a result, the gradation current Ipix sequentially supplied through the data lines DLja and DLjb of each data line group DLj is written in a plurality of rows (for example, two rows including the first row and the second row) corresponding to the respective scanning lines SLi. ) in the display pixel EM, a light emitting operation is performed at a predetermined gradation of brightness based on the gradation current Ipix.

As described above, in this embodiment, each row The display pixels in each row are sequentially set to the selected state, and through the signal driver, the display data corresponding to the display pixels in each row is sequentially acquired and held in each latch part. Simultaneously, the level current of each row is sequentially supplied to each display pixel. Therefore, a gradation current based on display data can be synchronously written into display pixels in multiple rows having a simple structure including latch portions corresponding to a plurality of data lines constituting a data line group in each row, thereby dividing the gradation The current writing time is set to be relatively long basically.

Specifically, as shown in FIG. 9, in this structure, the data line group arranged in each column includes two data lines and two latch parts, which are provided in the current holding/distributing part according to each data line group , it is possible to set a period which is 1/2 of the period for selecting display pixels in a scan period in a particular row to overlap with the period for selecting display pixels in the next row. That is, it is possible to set the selection period to overlap in adjacent rows only within a period corresponding to the number of data lines constituting the data line group.

In addition, like the first embodiment, compared with the known display device in which one data line is arranged in one row, the number of display pixels connected to each data line constituting the data line group in each column can be greatly reduced (this In the embodiment, it is 1/2). Therefore, it is possible to reduce a capacitance component including a holding capacitance provided in a display element or a parasitic capacitance of a driving transistor, and thus it is possible to reduce a time required for writing a layer current supplied to a data line in a display pixel, or it is possible to Suppresses this write time delay.

Note that this embodiment is configured in such a way that the display data corresponding to the display pixels in each row is acquired and held in each latch section by the signal driver, and at the same time, the gradation current of each row is generated, and sequentially provided to each display pixel, so that the latch operation in the current holding/distributing circuit (latch section) can be quickly performed. If the timing of the latch operation deviates due to signal delay or the like, there is a possibility that the display operation is hindered.

Thus, in this embodiment, the latch operation of the display data (signal current) in the current holding/distributing circuit (latch section) is quickly performed with a small current, and the current mirror circuit structure is applied to the output stage of each data line . As a result, the current value (absolute value) of the layer current can be easily controlled to obtain a larger current, and delay in the latch operation can be suppressed.

As described above, in FIG. 9, each transistor constituting each current holding/distributing circuit 143A in the current holding/distributing section 140B includes an n-channel type field effect thin film transistor including an amorphous silicon semiconductor layer as a channel layer. , or polysilicon semiconductor layer as the field effect thin film transistor of the channel layer, and the current holding/distributing part 140B and the pixel array are integrated on the insulating substrate BASE, wherein a plurality of display pixels EM constituting the display panel 110B are formed on the substrate. However, the present invention is not limited to this structure.

For example, the present invention may have a configuration in which a signal driver including a current generating section and a current holding/distributing section is an independent driver chip, and this driver chip is mounted (packaged) on a substrate of a display panel.

A structural example in this case will now be briefly explained.

FIG. 13 is a schematic configuration diagram of main parts showing another configuration example in the second embodiment of the display device according to the present invention.

Here, structures equivalent to the structures of the aforementioned structural examples are denoted by similar or identical reference numerals, thus simplifying explanation.

In FIG. 13 , a signal driver 200C including a current holding/distributing section 140B and a current generating section 130 is configured as an independent driver chip. Here, for example, the current holding/distributing circuit 143 in FIG. 13 includes a plurality of field effect transistors or the like formed on a single-crystal silicon substrate. The driver chip constituting this signal driver 200C is configured to be mounted (packaged) on the base BASE constituting the display panel 110B.

<Concrete circuit example of display pixel>

A specific circuit example that can be applied to a display pixel of a display device according to the present invention will now be described with reference to the drawings.

FIG. 14 is a circuit configuration diagram showing a specific circuit example of a display pixel that can be applied to a display device according to the present invention.

15A and 15B are conceptual diagrams showing drive control operations of the pixel drive circuit according to this embodiment.

FIG. 16 is a schematic block diagram showing a structural example of a display device to which the display pixel according to this embodiment can be applied.

FIG. 17 is a schematic block diagram showing another structural example of a display device to which the display pixel according to this embodiment can be applied.

As shown in FIG. 14, the display pixel EM' (the structure including the display pixel EM and the selection transistor Trsel described in association with the first embodiment) is generally configured with a pixel drive circuit DC based on a scan signal applied by the scan driver 120A or 120B Vsel, sets the display pixel EM' to the selected state, in the selected state, acquires the layer current Ipix supplied by the current holding/distributing part 140A or 140B, and passes the driving current corresponding to the layer current Ipix to the light emitting element and a current-controlled light-emitting element, including an EL element or an OEL element, which emits light having a predetermined gradation of brightness based on a driving current supplied from the pixel driving circuit DC.

For example, as shown in FIG. 14, the pixel driving circuit DC includes: an n-channel type transistor Tr11, in which the control terminal (gate terminal) and the scanning line SLi (corresponding to those described in association with each of the foregoing embodiments, constitute the scanning The scanning line SLia of the line group SGi is connected with SLib or SLq), and the current path (source-drain) is connected with the power line VL and the contact N11; n-channel type transistor Tr12, wherein the control terminal is connected with the scanning line SLi , the current path is connected to the data line DLj (each data line DLja or DLjb constituting the data line group DGj described in association with each of the foregoing embodiments) and the contact N12; the n-channel type transistor Tr13, wherein the control terminal is connected to The contact N11 is connected, and the current path is connected to the power supply line VL and the contact N12; and a capacitor (holding capacitor) Cs is connected between the contact N11 and the contact N12. The anode terminal of the organic EL element OEL is connected to the contact N12, and the cathode terminal of the element is connected to the ground terminal. Here, the capacitance Cs may be a parasitic capacitance formed between the gate and the source of the transistor Trl3. In addition, the transistor Tr12 corresponds to the selection transistor Trsel described in association with each of the aforementioned embodiments.

The light emitting element (organic EL element OEL ), so that the selected states of the display pixels are overlapped within a predetermined period, and a selection period (write operation period) Tse is set in which the drive current Ipix corresponding to the display data is written and held as a voltage component, A non-selection period (emission operation period) Tnse is also set in which a driving current corresponding to display data is supplied to the organic EL element based on a voltage component written and held in the selection period Tse to emit light having a predetermined luminance gradation ( Tse=Tse+Tnse).

(select period)

That is, in the selection period Tse of the display pixels EM', by applying the advanced scan signal Vsel from the scan driver to a specific scan line SLi, the display pixels EM' in multiple rows are first synchronized (or overlapped in a predetermined period) ) is set to the selected state, and at the same time, the low-level power supply voltage Vsc is applied to the power supply lines VL of the display pixels in a plurality of rows. In addition, in synchronization with this timing, the gradation current Ipix having a negative polarity is supplied from the current holding/distributing portion to each data line DLj corresponding to the display data of the display pixels EM' in a plurality of rows.

As a result, as shown in FIG. 15A, the transistors TR11 and Tr12 constituting the pixel drive circuit DC are turned on, and the low-level power supply voltage Vsc is applied to the contact N11 (that is, the gate terminal of the transistor Tr13 and one end of the capacitor Cs). ). In addition, an operation of pulling the layer current Ipix to the current holding/distributing portion through the data line DL is performed. As a result, a voltage level lower in potential than the low-level power supply voltage Vsc is applied to the contact N12 (that is, the source terminal of the transistor Tr13 and the other end of the capacitor Cs).

In this way, a potential difference is generated between the contacts N11 and N12 (between the gate and the source of the transistor Tr13 ). As a result, the transistor Tr13 is turned on, and the write current Ia corresponding to the layer current Ipix flows from the power supply line VL to the current holding/distributing portion through the transistor Tr13, the contact N12, the transistor TR12, and the data line DL.

At this time, charges corresponding to the potential difference generated between the contacts N11 and N12 (between the gate and the source of the transistor Tr13 ) are stored in the capacitor Cs and held (charged) as voltage components. In addition, the power supply voltage Vsc having a voltage level not higher than the ground potential is applied to the power supply line VL, and the write current Ia is controlled to flow in the direction of the data line DL. Therefore, the potential applied to the anode terminal (contact N12) of the organic EL element becomes lower than the potential (ground potential) of the cathode terminal, and a reverse bias voltage is applied to the organic EL element OEL. Therefore, a driving current does not flow through the organic EL element OEL, and a light emitting operation is not performed.

(non-selection period)

Subsequently, in the non-selection period Tnsec after the selection period Tse is completed, the low-level scan signal Vsel is applied from the scan driver to a specific scan line SLi, so that the display pixels in multiple rows are set to a non-selected state, and the high-level power supply voltage Vsc The power supply line VL is applied to the display pixels in the rows. In addition, in synchronization with this timing, the operation of pulling the tier current Ipix performed by the current holding/distributing section is terminated.

As a result, as shown in FIG. 15B , the transistors Tr11 and Tr12 constituting the pixel drive circuit DC are turned off, and application of the power supply voltage Vsc to the contact N11 (ie, the gate terminal of the transistor Tr13 and one end of the capacitor Cs) is interrupted. In addition, application of the voltage level to the contact N12 (that is, the source terminal of the transistor Tr13 and the other end of the capacitor Cs) is interrupted due to the operation of pulling the layer current Ipix performed by the current holding/distributing portion. Therefore, the capacitor Cs holds the charge stored in the selection period.

When the capacitance Cs holds the charge voltage in the writing operation in this way, the potential difference between the contacts N11 and N12 (between the gate and the source of the transistor Tr13 ) is held, and thus the transistor Tr13 maintains the on state. In addition, since the power supply voltage Vsc having a voltage level higher than the ground potential is applied to the power supply line VL, the potential applied to the anode terminal (contact N12) of the organic EL element OEL becomes higher than the potential of the cathode terminal (ground potential) .

Accordingly, a predetermined driving current Ib flows from the power supply line VL to the organic EL element OEL in the forward bias direction through the transistor Tr13 and the contact N12, and the organic EL element OEL emits light. Here, since the potential difference (charge voltage) held by the capacitance Cs corresponds to the potential difference when the writing current Ia corresponding to the layer current Ipix is passed into the transistor Tr13, the drive current Ib flowing through the organic EL element OEL has the same voltage as the writing current Ia. current value.

As a result, in the non-selection period Tnse following the selection period Tse, based on the voltage component corresponding to the display data (layer current Ipix) written in the selection period Tse, the drive current is continuously supplied through the transistor Tr13, and the organic EL element OEL continues to operate. , emitting light with brightness levels corresponding to the display data.

Next, based on the above-described drive control operation of the display device, the above-described series of operations are sequentially and repeatedly performed for all the scanning lines SLi constituting the display panel 110A or 110B. As a result, display data for one screen of the display panel is written, light having predetermined gradations of brightness is emitted, and desired image information is displayed.

Here, in the image driving circuit DC according to this embodiment, since the transistors Tr11 to Tr13 can be constituted by using transistors having the same channel polarity (n-channel type), an amorphous silicon layer can be applied as the channel layer The n-channel type field effect thin film transistor, or the field effect thin film transistor with the polysilicon layer as the channel layer, similar to the circuit of the current holding/distributing part (current distribution circuit, current holding circuit, and current holding/distribution circuit) 140A and 140B structure. In this case, the current holding/distributing parts 140A and 140B and the display panels 110A and 110B may be integrated on a single insulating substrate. In particular, when the display panel and the current holding/distributing portion are constituted by applying an n-channel type field effect thin film transistor using an amorphous silicon semiconductor layer, it can be manufactured relatively inexpensively by applying a certain amorphous silicon manufacturing technology with stable operation characteristics Field Effect Thin Film Transistors. Therefore, even if high definition of the display panel is realized or the size of the display panel is increased, a display device with good display image quality can be realized easily and excellently.

Here, as a structure of applying a predetermined power supply voltage Vcs to the power supply line VL in the pixel drive circuit DC according to this embodiment, a structure as shown in FIG. 16, for example, may be excellently applied with respect to the structure described in FIG. , wherein a power driver 170A connected to each power supply line group VGi is provided in the peripheral area of the display panel 110C, and in this area, each power supply line group VGi including the power supply lines VLia and VLib is connected to each scan line group SGi The respective scanning lines SLia and SLib are arranged in parallel, and, in synchronization with the timing of outputting the scanning signal Vsel from the scanning driver 120A, based on the power supply control signal input from the system controller 150, the power supply voltage Vcs having a predetermined voltage value is applied from the power supply driver 170A. for each power cord group VGi.

In addition, with respect to the structure described in FIG. 13, for example, as shown in FIG. In this region, each power supply line VLi is arranged in parallel with each scan line SLi in each row, and, in synchronization with the timing of outputting the scan signal Vsel from the scan driver 120B, has a predetermined A power supply voltage Vcs of a voltage value is applied to each power supply line VLi from the power supply driver 170B.

Note that a description has been given regarding the circuit configuration corresponding to the current application scheme, in which three transistors are included as the pixel drive circuit DC, and in the display pixel EM', through the data line DLj, the current holding The layer current Ipix is pulled in the direction of the /distribution section (ie, the direction of the signal driver), but the invention is not limited to this embodiment. As long as the display device has an emission control transistor that controls supply of a drive current to a light emitting element, and a write control transistor that controls a gradation current writing operation, and that the display device maintains a gradation current corresponding to display data (writing current), and then based on the level current, turning on the light emission control transistor to supply the level current, thereby allowing the light emitting element to emit light with a predetermined brightness level, it is possible to use a display including a pixel driving circuit and having another circuit structure A device wherein at least a current application mode is applied to the pixel driving circuit. For example, the present invention may have a circuit structure including, for example, four transistors, or have a circuit structure, through the data line, in the direction of the display pixel (pixel driving circuit), from the side of the current holding/distributing portion (also That is, the signal driver side) conducts layer current.

In addition, although the description has been given regarding the structure in which an organic EL element is applied as the light emitting element constituting the display pixel in the foregoing embodiments, the display device according to the present invention is not limited thereto. As long as it is a current control type light emitting element that emits light with a predetermined gradation of luminance depending on the current value of the supplied driving current, it is possible to be excellently applied to, for example, a light emitting diode or any other light emitting element like the organic EL element described above.

Claims (47)

1. A display driver, which drives a plurality of two-dimensionally arranged display pixels constituting a display panel based on display data, the display driver at least comprising: A level signal generation circuit generates a level signal based on the display data, and the level signal is used to control the brightness level of each display pixel; a selection circuit for setting each of the display pixels in a plurality of specific rows of the display panel to a selected state for writing a gradation current based on the gradation signal, and setting at least a part of periods to overlap with each other a period, the at least a portion of the period is at least a portion of the period in which the display pixels of each of the plurality of specific rows are set to a selected state; and a current writing circuit, which extracts the level signals corresponding to the display pixels in the plurality of specific rows, and provides the display pixels in the plurality of specific rows with A layer current based on the current value of the layer signal is provided simultaneously during the overlapping period. 2. The display driving device according to claim 1, wherein at least the current writing circuit has a structure independent of the display panel. 3. The display driving device according to claim 1, wherein at least the current writing circuit is integrated with the display panel. 4. The display driving device according to claim 1, wherein at least the current writing circuit has a plurality of field effect thin film transistors, each of which has a single channel polarity, and has an amorphous silicon layer as a channel layer . 5. The display driving device according to claim 1, wherein at least the current writing circuit has a plurality of field effect thin film transistors, each of which has a polysilicon layer as a channel layer. 6. The display driving device according to claim 1 , wherein the gradation signal generating circuit generates a signal current as the gradation signal, and the signal current provides the display pixel with a brightness gradation corresponding to the display data. 7. The display driving device according to claim 1 , wherein the current writing circuit has means for generating and outputting the gradation current, wherein the gradation current has a current opposite to the signal current supplied by the current generating portion polarity. 8. The display driving device according to claim 1 , wherein the selection circuit has means for simultaneously setting the display pixels in the plurality of specific rows of the display panel to the selected state based on a single selection signal, and The current writing circuit has means for simultaneously supplying the level current to the display pixels in the plurality of specific rows according to the timing of setting the display pixel to the selected state according to the selection signal. 9. The display driving device according to claim 8, wherein the hierarchical signal generation circuit has a function of sequentially providing a plurality of display elements in the display pixels of each column in the plurality of specific rows to the current writing circuit in time series. pixel corresponding to the level signal device, and This current write circuit has: a plurality of signal distribution circuits that sequentially distribute the gradation signal provided by the gradation signal generation circuit according to the plurality of display pixels in each column at the timing of the time-series source; and a plurality of current holding circuits that individually hold the gradation signal distributed by the signal distribution section, and simultaneously supply currents having current values based on the holding gradation signals to the display pixels in the plurality of specific rows as the gradation current; The signal distribution circuit and the current holding circuit are provided according to each column of the display pixels in the plurality of specific rows. 10. The display driving device according to claim 9, wherein each current holding circuit has a signal holding/output section on multiple stages, and the signal holding/output section includes: a signal holding section according to the Each of the plurality of display pixels in each column of the display pixels holds a signal current distributed by the signal distribution circuit; and a hierarchical current output section that outputs a current corresponding to the signal current held in the signal holding section , as the level current, wherein the operation of acquiring and holding the signal current performed by the signal holding section on one of the multiple stages of the signal holding/output section is controlled to be the same as outputting the stage by the stage current output section on any other stage Current operations are performed synchronously. 11. The display driving device according to claim 10, wherein the signal holding section includes a charge storage circuit that stores charges based on the signal current and holds the charges as voltage components. 12. The display driving device according to claim 10 , wherein the layer current output portion has a current mirror circuit structure, which generates and outputs a current having a current value relative to the layer current as the layer current. The current value corresponding to the level signal provided by the signal generation circuit has a predetermined current ratio. 13. The display driving device according to claim 1, wherein the selection circuit has a means for sequentially applying a selection signal to each of the plurality of specific rows of the display panel with the overlapping period, wherein The selection signal sets the display pixels in each row to the selected state, so that the display pixels corresponding to the plurality of specific rows are sequentially set to the selected state with the overlapping period. 14. The display driving device according to claim 13 , wherein the current writing circuit has a means for, at the timing when the selection circuit applies the selection signal, to the plurality of specific rows in the overlapping period. Each in turn provides that level of current. 15. The display driving device according to claim 13 , wherein the gradation signal generating circuit has a device for sequentially supplying the gradation signal to the current writing circuit in time series, wherein the gradation signal corresponds to a plurality of the display pixels in each column of the display pixels in the plurality of specific rows, and The current writing circuit includes a plurality of current holding circuits provided according to each column of the display pixels in the plurality of specific rows, which sequentially hold the layer signal provided by the layer signal generating circuit according to the timing of the time series source , and sequentially supply a current having a current value based on the gradation signal to each of the plurality of specific rows as a gradation current. 16. The display driving device according to claim 15, wherein each of the current holding circuits comprises: a signal distribution section that distributes the signal current according to the timing of the time series source; and According to a plurality of current holding/output sections of the plurality of display pixels in each column of the plurality of specific rows, each of the current holding/output sections has: a signal holding section held by the signal distribution section the signal current distributed; and a tier current output section which outputs a current corresponding to the signal current held in the signal holding section as a tier current; Wherein, two operations are controlled to be performed simultaneously in the overlapping period, that is, output by the hierarchical current output section of one of the current holding/output sections based on the signal current held in the signal holding section operation of the hierarchical current, and the signal current distributed by the signal distribution section is held in the signal holding section of another current holding/output section, and output by the hierarchical current output section based on the holding in the signal holding section operation of the level current of the signal current. 17. The display driving device according to claim 16 , wherein the signal holding section includes a charge storage circuit that stores charges based on the signal current and holds the charges as voltage components. 18. The display driving device according to claim 16 , wherein the hierarchical current output portion has a current mirror circuit structure that generates and outputs a current having a current value relative to the hierarchical current as the hierarchical current. The current value corresponding to the level signal provided by the level signal generation circuit has a predetermined current ratio. 19. A display device for displaying image information based on display data, the display device comprising at least: A display panel, which has a plurality of scanning lines arranged in the row direction and a plurality of data lines arranged in the column direction, and a plurality of display pixels; a scan driver, which sets the display pixels corresponding to a plurality of specific scan lines, which are at least a plurality of scans of the display panel, to a selected state for writing a hierarchical current based on the display data a part of the line, and at least a part of the period is set as a period overlapping with each other, and the at least part of the period is at least a part of the period in which the display pixels of each row of the plurality of specific rows are set to the selected state; and A signal driver including: a gradation signal generation circuit to which display data is supplied and which generates a gradation signal for controlling a brightness gradation of each display pixel based on the display data; and a current writing circuit which acquires a gradation corresponding to The level signal of the display pixel, wherein the display pixel corresponds to the plurality of specific scan lines, and the current writing circuit supplies the current writing circuit to the corresponding to the plurality of specific scan lines according to the period set to the selected state by the scan driver Display pixels supply gradation currents having current values based on the gradation signal and simultaneously during the overlapping period. 20. The display device according to claim 19, wherein at least the signal driver has a configuration independent of the display panel. 21. The display device according to claim 19, wherein the display panel and at least the current writing circuit in the signal driver are formed on a single insulating substrate. 22. The display device according to claim 19 , wherein the current writing circuit in the signal driver has means for generating and outputting the gradation current, wherein the gradation current has the same signal as that provided by the current generation part. The opposite current polarity of the current. 23. The display device according to claim 19, wherein at least the current writing circuit has a plurality of field effect thin film transistors, each of which has a single channel polarity, and has an amorphous silicon layer as a channel layer. 24. The display device according to claim 19, wherein at least the current writing circuit has a plurality of field effect thin film transistors, wherein each transistor has a polysilicon layer as a channel layer. 25. The display device according to claim 19 , wherein the gradation signal generating circuit generates a signal current as the gradation signal, and the signal current provides the display pixel with a luminance gradation corresponding to the display data. 26. The display device according to claim 19, wherein the display pixels comprise: a pixel driving circuit generating a predetermined driving current based on the level current output from the signal driver; and The current-controlled light-emitting element emits light having a predetermined gradation of brightness based on the current value of the driving current. 27. The display device according to claim 26, wherein the pixel driving circuit has a plurality of field effect thin film transistors, each transistor has a single channel polarity, and an amorphous silicon layer as the channel layer. 28. The display device according to claim 26, wherein the driving circuit has a plurality of field effect thin film transistors, each transistor having a polysilicon layer as a channel layer. 29. The display device according to claim 26, wherein the light emitting element is an organic electroluminescence element. 30. The display device according to claim 19, wherein the display panel has a plurality of data line groups, each data line group has a plurality of data lines, and the plurality of data lines correspond to the plurality of data lines determined as a set. The number of scanlines per scanline group in the dataline. 31. The display device according to claim 30, wherein each data line group is arranged in each region between columns of a plurality of display pixels arranged in a matrix in the display panel. 32. The display device according to claim 30, wherein the display panel has a plurality of scan line groups, and each scan line group has a plurality of specific scan lines determined as a set, The scan driver has means for applying a single scan signal to each scan line group to simultaneously set the display pixels corresponding to the plurality of specific scan lines to a selected state, wherein the single scan signal sets the display pixels to a selected state. as selected, The hierarchical signal generating circuit in the signal driver has a device for sequentially supplying the hierarchical signal corresponding to a plurality of display pixels to the current writing circuit in time series, wherein the plurality of display pixels correspond to each Each scan line group in each data line of data line groups, and The current writing circuit in the signal driver includes: a plurality of signal distribution circuits, at the timing of the time series source, according to each data line in each data line group, sequentially distribute the signal generation circuit provided by the layer a gradation signal; and a plurality of current holding circuits which individually hold the gradation signal distributed by the signal distribution section, and will have a current value based on the holding gradation signal depending on the timing at which the scanning signal is applied to each scanning line group The current is synchronously provided to each data line in each data line group as a hierarchical current, and the signal distribution circuit and the current holding circuit are provided according to each data line group. 33. The display device according to claim 32, wherein each of the current holding circuits has a multi-stage signal holding/output section, and each of the signal holding/output sections includes: a signal holding section, which is based on each data line group each of the data lines, holding the gradation signal distributed by the signal distribution circuit; and a gradation current output section, which outputs a current having a current value based on the gradation signal as the gradation current, wherein the gradation signal is held in the signal holding section, An operation in which the signal holding section acquires and holds the gradation signal at one of the multiple stages of the signal holding/outputting section, and an operation in which the gradation current is output by the tier current output section at the other stages, is controlled for synchronous execution. 34. The display device according to claim 33 , wherein the signal holding section includes a charge storage circuit that stores charges corresponding to the hierarchical signals and holds the charges as voltage components. 35. The display device according to claim 33 , wherein the hierarchical current output portion has a current mirror circuit structure that generates and outputs a current having a current value relative to and generated by the hierarchical current as the hierarchical current. The current value corresponding to the level signal provided by the signal generating circuit has a predetermined current ratio. 36. The display device according to claim 30 , wherein the scan driver has a means for applying a scan signal to each of the plurality of specific scan lines in sequence with the overlapping period, thereby sequentially applying the scanning signal to the display pixels corresponding to the plurality of specific scan lines are set to the selected state, wherein the scan signal sets the display pixels to the selected state, and The current writing circuit in the signal driver has means for sequentially supplying the layer current to each data line of each data line group with the overlapping period at the timing at which the scan driver applies the scan signal. 37. The display device according to claim 30 , wherein the scan driver has a means for applying a scan signal to each of the plurality of specific scan lines sequentially with the overlapping period, thereby sequentially applying the scanning signal to the plurality of specific scanning lines with the overlapping period the display pixels corresponding to the plurality of specific scan lines are set to the selected state, wherein the scan signal sets the display pixels to the selected state, The level signal generation circuit in the signal driver has a device for sequentially providing the level signal corresponding to the plurality of display pixels to the current writing circuit in time series, wherein the plurality of display pixels correspond to the plurality of specific scan lines in each data line of each data line group, and The current writing circuit has a plurality of current holding circuits, and each current holding circuit is provided according to each data line group, and according to the timing of the time series source, sequentially holds the layer signal provided by the layer signal generating circuit, and A current having a current value corresponding to the gradation signal is sequentially supplied as the gradation current to each data line of each data line group at a timing corresponding to application of the scan signal. 38. The display device according to claim 37 , wherein each current holding circuit includes a plurality of current holding/output sections according to each data line in each data line group, the current holding/output section having: signal distribution part, at the timing of the time series source, according to each data line in each data line group, sequentially distribute the level signal; a signal holding part, which holds the level signal distributed by the signal distribution part; and level current output a section that outputs, as a tier current, a current having a current value based on the tier signal held in the signal holding section, Wherein, there are two operations controlled to be performed simultaneously in the overlapping period, that is, the hierarchical signal distributed by the signal distribution part is held in the signal holding part in one of the current holding/output parts, and the an operation in which the tier current output section outputs the tier current based on the tier signal, and an operation in which the tier current output section outputs the tier current based on the tier signal held in the signal holding section in any other current holding/output section . 39. The display device according to claim 38 , wherein the signal holding section includes a charge storage circuit that stores charges corresponding to the hierarchical signals and holds the charges as voltage components. 40. The display device according to claim 38 , wherein the hierarchical current output portion has a current mirror circuit structure that generates and outputs a current having a current value as the hierarchical current, wherein the current value is relative to the current value obtained by the hierarchical current. The current value corresponding to the level signal provided by the current generating part has a predetermined current ratio. 41. A driving method of a display device, displaying image information based on display data, The display device has a display panel having a plurality of scanning lines arranged in a row direction and a plurality of data lines arranged in a column direction and arranged near intersections of the plurality of scanning lines and the plurality of data lines, and A plurality of display pixels are arranged in a matrix, The driving method includes at least: receiving the display data, and generating a level signal for controlling the brightness level of each display pixel based on the display data; setting the display pixels corresponding to a plurality of specific scan lines, which are at least a part of a plurality of scan lines in the display panel, to a selected state for writing a level current based on the display data ; The operation of setting the selected state includes the operation of setting at least a part of the period as overlapping periods, and the at least part of the period is a period of setting the display pixels of each row in the plurality of specific rows to the selected state at least a portion of the period; acquiring the level signal corresponding to the display pixel corresponding to the plurality of specific scan lines, generating the level current having a current value based on the level signal, and according to the period set to the selected state, providing the level current to display pixels corresponding to the plurality of specific scan lines; providing the level current to display pixels corresponding to the plurality of specific scan lines simultaneously during the overlapping period; and The display pixel is operated with a display brightness based on the current value of the gradation current supplied and written into the display pixel. 42. The driving method of a display device according to claim 41 , wherein the operation for generating the gradation signal generates a signal current as the gradation signal, and the signal current provides the display pixel with a brightness gradation corresponding to the display data. 43. The driving method of a display device according to claim 41 , wherein the operation of generating and outputting the gradation current having a current value based on the gradation signal comprises: generating a current with a current value having a predetermined current ratio relative to a current value corresponding to the level signal, and outputting the generated current as an operation of the level current. 44. The driving method of a display device according to claim 41 , wherein the operation of setting the display pixel to the selected state comprises the operation of applying a single scanning signal to the plurality of specific scanning lines simultaneously, so that the corresponding The display pixels of the plurality of scan lines are simultaneously set to the selected state, wherein the single scan signal sets the display pixels to the selected state, and The operation of supplying the gradation current includes an operation of simultaneously supplying the gradation current to the display pixels corresponding to the plurality of scan lines according to the timing of applying the scan signal. 45. The driving method of a display device according to claim 44, wherein the operation of synchronously providing the hierarchical current to the display pixels corresponding to the plurality of scan lines includes the operation of synchronously performing the following operations: operations to acquire and hold signals of the hierarchy corresponding to each scan line; and Based on the gradation signal acquired and held at the above-mentioned timing, the operation of the gradation current is output. 46. The driving method of a display device according to claim 41 , wherein the operation of setting the display pixel to the selected state sequentially applies a scan signal to each of the plurality of specific scan lines with an overlapping period, so that the an overlapping period sequentially sets the display pixels corresponding to the plurality of scan lines to the selected state, wherein the scan signal sets the display pixels to the selected state, and The operation of supplying the gradation current includes an operation of sequentially supplying the gradation current to the display pixels corresponding to each of the plurality of scanning lines at the timing of applying the scanning signal in the overlapping period. 47. The driving method of a display device according to claim 46, wherein the operation of providing the hierarchical current to the display pixels corresponding to the plurality of scan lines in sequence is performed synchronously in the overlapping period: an operation of holding the gradation signal and outputting the gradation current based on the gradation signal; and an operation of outputting the gradation current based on the gradation signal held at the aforementioned timing.

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