JP2008186031A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device in which the deterioration in display image quality due to writing deficiency can be suppressed when performing writing operation of display data (gradation current) to a display pixel and further satisfactory dealing with the resolution refining is made possible. <P>SOLUTION: The display device 100 includes a display panel 110A which is arrayed with a display pixel EM connected to each intersection point of data lines DLia, DLib constituting a data line DGj with scanning lines SLia, SLib constituting a scanning line group SGi, a scanning driver 120A which sets the display pixels for a plurality of line components at a selection state all at once by successively applying a scanning signal Vsel to each scanning line group SGi, and a current latch/distribution section 140A which supplies a gradation current Ipix all at once to the plurality of the selected display pixels EM. At least the current latch/distribution section 140A is integrally formed together with the display panel 110A on an insulating substrate BASE. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device, and more particularly, to a display panel in which a plurality of display pixels each including a current control type light emitting element that emits light at a predetermined luminance gradation by supplying a current according to display data. The present invention relates to a display device.

  Conventionally, a current that emits light at a predetermined luminance gradation in accordance with a current value of a supplied drive current, such as an organic electroluminescence element (hereinafter abbreviated as “organic EL element”) or a light emitting diode (LED). 2. Description of the Related Art A light emitting element type display (display device) including a display panel in which display pixels each having a control type light emitting element are two-dimensionally arranged is known.

  In particular, a light-emitting element type display using an active matrix driving method has a higher display response speed and no viewing angle dependency compared to a liquid crystal display (LCD) which has been widely used in recent years. And display image quality, low power consumption, etc., and because it is composed of light emitting element type display pixels, it does not require a backlight as in the case of a liquid crystal display device. It is extremely advantageous in that it can be made thinner and lighter, and research and development are actively conducted as a next-generation display.

FIG. 16 is a schematic diagram illustrating a configuration example of a main part of a light-emitting element type display according to the conventional technique, and FIG. 17 is an equivalent circuit diagram illustrating a configuration example of display pixels applied to the light-emitting element type display according to the conventional technique. .
As shown in FIG. 16, the light emitting element display according to the prior art is roughly described in the vicinity of the intersections of a plurality of scanning lines SL and a plurality of data lines DL arranged so as to be orthogonal to each other. A display panel 110P in which a plurality of display pixels EM each provided with a light emission driving circuit (pixel driving circuit) and a current control type light emitting element (organic EL element) are arranged in a matrix (n rows × m columns), and the display panel A scanning driver 120P that is connected to the scanning line SL of 110P and sequentially applies the scanning signal Vsel to each scanning line SL at a predetermined timing to set (scan) the display pixels EM for each row; and a display panel 110P is connected to the data line DL of the 110P, and the display data is taken in, and the gradation current (level) corresponding to the display data is input to each data line DL at a predetermined timing. It has a structure in which and a data driver 130P which supplies a signal) IPpix.

  In such a display, for example, the operation state of the scan driver 120P and the data driver 130P is controlled by a scan control signal and a data control signal generated based on a timing signal supplied from the outside, and the scan signal is applied. By writing a gradation current corresponding to the display data to the display pixels in each row set in the selected state, each display pixel emits light with a predetermined luminance gradation, and desired image information is displayed.

  In such a light emitting element type display, various drive control mechanisms and control methods for controlling light emission of the above-described current control type light emitting element have been proposed. For example, as described in Patent Document 1 and the like, for each display pixel constituting the display panel, in addition to the light-emitting element, a drive circuit including a plurality of switching means for controlling light emission of the light-emitting element ( Hereinafter, a device provided with a “light emission drive circuit” for convenience is known.

  Specifically, as shown in FIG. 17, the display pixels described in Patent Document 1 and the like are near the intersections of a pair of scanning lines SL1 and SL2 and a data line DL arranged in parallel to each other. The gate terminal is connected to the scan line SL1, the source terminal and the drain terminal are connected to the data line DL and the contact N121, the thin film transistor Tr121 is connected to the scan line SL2, the source terminal and the drain terminal are connected to the contact N121 and the contact N122, respectively. The thin film transistor Tr122 connected to each other, the gate terminal connected to the contact N122, the drain terminal connected to the contact N121, the thin film transistor Tr123 applied with the high power supply voltage Vdd to the source terminal, the gate terminal connected to the contact N122, the source Thin film transistor Tr124 having a high power supply voltage Vdd applied to its terminal And an organic EL element OEL in which the anode terminal is connected to the drain terminal of the thin film transistor Tr124 of the lower pixel driving circuit DP1 and the ground potential is applied to the cathode terminal. Yes.

Here, in FIG. 17, the thin film transistor Tr121 is configured by an n-channel field effect transistor, and the thin film transistors Tr122 to Tr124 are configured by p-channel field effect transistors. CP1 is a parasitic capacitance formed between the gate and source of the thin film transistors Tr123 and Tr124.
In the light emission drive circuit DP2 having such a configuration, the four transistors (switching means) composed of the thin film transistors Tr121 to Tr124 are turned on and off at a predetermined timing, so that an organic EL is provided as shown below. The element OEL is controlled to emit light.

  That is, in the light emission drive circuit DP1, a high-level scanning signal Vsel1 is applied to the scanning line SL1 and a low-level scanning signal Vsel2 is applied to the scanning line SL2 by a scanning driver (not shown) to set the display pixel in a selected state. Then, the thin film transistors Tr121, Tr122, and Tr123 are turned on, and the gradation current Ipix that is supplied to the data line DL by the data driver (not shown) flows through the thin film transistors Tr121 and Tr123. At this time, since the gate and drain of Tr123 are electrically short-circuited by Tr122, Tr123 operates in the saturation region. As a result, the current level of the gradation current Ipix is converted into a voltage level by the thin film transistor Tr123, and a predetermined voltage is generated between the gate and the source (writing operation). The thin film transistor Tr124 is turned on according to the voltage generated between the gate and the source of the thin film transistor Tr123, and a predetermined light emission drive current flows from the high power supply voltage Vdd to the ground potential via the thin film transistor Tr124 and the organic EL element OEL. The EL element OEL emits light (light emission operation).

  Next, for example, when a high level scanning signal Vsel2 is applied to the scanning line SL2, the thin film transistor Tr122 is turned off, whereby the voltage generated between the gate and the source of the thin film transistor Tr123 is held by the parasitic capacitance CP1, and then the scanning is performed. When the low level scanning signal Vsel1 is applied to the line SL1, the thin film transistor Tr121 is turned off, thereby electrically disconnecting the data line DL and the pixel driving circuit DP1. Thereby, the thin film transistor Tr124 is continuously turned on by the potential difference based on the voltage held in the parasitic capacitance CP1, and a predetermined light emission driving current is supplied from the high power supply voltage Vdd to the ground potential via the thin film transistor Tr124 and the organic EL element OEL. The organic EL element OEL continues to emit light.

Here, the light emission drive current supplied to the organic EL element OEL via the thin film transistor Tr124 is controlled to have a current value based on the luminance gradation of the display data, and this light emission operation depends on the next display data. Until the gradation current is written to each display pixel, for example, control is performed so as to continue for one frame period.
The drive control method in the pixel drive circuit having such a circuit configuration supplies each display pixel (the gate terminal of the thin film transistor Tr123) with a grayscale current specifying a current value corresponding to display data, and according to the current value. Based on the held voltage, the light emission drive current that flows through the organic EL element OEL is controlled so that the light emission operation is performed at a predetermined luminance gradation. Therefore, this is called a current application method (or current designation method). Yes.

  Although not shown, as in FIG. 17, a gradation signal voltage designating a voltage value corresponding to display data is applied to a display pixel including a pixel driving circuit and an organic EL element, There is also known a voltage application method (or voltage designation method) drive control method in which a light emission drive current passed through the organic EL element OEL is controlled in accordance with a voltage value to cause a light emission operation at a predetermined luminance gradation.

  Here, in the light emission drive circuit adopting the voltage designation method, the element characteristics (channel resistance of the thin film transistor, etc.) of the switch element responsible for the selection function and the light emission drive function are affected by the external environment (ambient temperature, etc.) When the variation or fluctuation (deterioration) occurs depending on the light emission, the light emission drive current is affected, and the desired light emission characteristic (display with a predetermined luminance gradation) is stably realized over a long period of time. In other words, if each display pixel is miniaturized in order to increase the definition of the display panel, the operating characteristics of the switch elements (such as the current between the source and drain of the thin film transistor) vary. Therefore, there is a problem that appropriate gradation control cannot be performed, and the light emission characteristics of each display pixel vary, resulting in deterioration of display image quality.

  On the other hand, in the above-described current designating light emission driving circuit, the thin film transistor Tr123 (current / voltage conversion transistor) that converts the current level of the grayscale current corresponding to the display data supplied to each display pixel into a voltage level. ) And a thin film transistor Tr124 (light emission drive transistor) for supplying a drive current having a predetermined current value to the organic EL element OEL, and setting the current value of the light emission drive current to be supplied to the organic EL element OEL. Since the influence of variation in the operation characteristics of Tr 124 can be suppressed, there is an advantage that the problem of the light emission drive circuit of the voltage designation system can be solved.

JP 2001-147659 A (pages 7 to 8, FIG. 1)

However, the light emission drive circuit adopting the current designating method as described above has the following problems.
(1) That is, when a gradation current based on the display data having the lowest or relatively low luminance is written to each display pixel (at the time of low gradation display), a signal current having a small current value corresponding to the luminance gradation of the display data Must be supplied to each display pixel.

  Here, the operation of writing display data (gradation current) to each display pixel is equivalent to charging a capacitance component parasitic in the data line (a wiring capacitor and a storage capacitor constituting the display pixel) to a predetermined voltage. For example, when the wiring length of the data line is increased due to an increase in the size of the display panel and the number of display pixels connected to the data line is increased, the current value of the gradation current becomes smaller (that is, the lower order). The data line charging time becomes longer and the writing operation to the display pixel takes a long time, and the display written to the display pixel at a preset (default) writing time. Insufficient writing occurs, in which data does not reach a sufficiently stable state (saturated state). As a result, a display pixel that cannot emit light with an appropriate luminance gradation according to display data is generated, and there is a problem in that a luminance difference occurs in the display panel, resulting in deterioration of display image quality.

(2) Further, in order to increase the definition of the display panel, the number of scanning lines arranged on the display panel is increased and the selection period (ie, writing time) of each scanning line is set short. However, as the current value of the gradation current becomes smaller, the sufficient writing operation to each display pixel will not be performed, resulting in insufficient writing, resulting in deterioration of display image quality, and high definition of the display panel is restricted. Had the problem of being.

(3) Further, as shown in FIG. 16, a scanning driver or a data driver having the form of an IC chip is terminal-connected to a peripheral area (for example, on a panel substrate) of a display panel in which display pixels are two-dimensionally arranged. In this case, the scanning signals and gradation currents output from the scanning driver and the data driver correspond one-to-one for each row (n scanning lines) and each column (m data lines) of the display panel. Therefore, when the display panel is made high-definition, the number of output terminals of the driver chip (that is, the number of connection terminals between the display panel and the scan driver or the data driver) increases, and the pitch (interval) between the terminals becomes narrower. There has been a problem that the product cost of the display rises due to increased precision of alignment in the chip connection process and increased man-hours.

  Therefore, in view of the above-described problems, the present invention enables a light emitting element to emit light with stable light emission characteristics over a long period of time in a display that controls light emission of a light emitting element provided in a display pixel by a current application method. In the display data (gray scale current) writing operation to the display pixel, the display image quality can be prevented from being deteriorated due to insufficient writing, and the display panel can cope with high definition. An object is to provide an apparatus.

  According to the first aspect of the present invention, the gradation current based on the display data is supplied to the two-dimensionally arranged display pixels constituting the display panel, so that each display pixel has a predetermined luminance scale based on the display data. In a display device that performs desired light emission operation and displays desired image information on the display panel, at least a specific plurality of rows of display pixels arranged in the display panel are simultaneously selected for at least a predetermined period. Scan driving means for setting, signal driving means for generating a gradation signal for controlling the luminance gradation of the display pixel for each row based on the display data, and the gradation signal output from the signal driving means The gray scale current having a current value based on the gray scale signal is generated, and is applied to each of the display pixels of the plurality of rows set to the selected state by the scan driving means. Current writing means for writing the gradation current through individual data lines, and the display pixels arranged in the display panel are arranged to output the gradation current output from the current writing means. A light emission drive circuit that generates a predetermined light emission drive current based on the light emission drive circuit, a current control type light emitting element that emits light at a predetermined luminance gradation based on a current value of the light emission drive current supplied from the light emission drive circuit, and , And at least the display panel and the current writing means are provided on a single insulating substrate.

  According to a second aspect of the present invention, in the display device according to the first aspect, the display panel includes a plurality of scanning lines commonly connected to the display pixels of the plurality of rows, and the scanning driving means A plurality of rows of display pixels are simultaneously set to a selected state by applying a single scanning signal to each.

  According to a third aspect of the present invention, in the display device according to the first aspect, the display panel includes a plurality of scan lines connected to the display pixels for each row, and the scan driving means is provided for each of the scan lines. In addition, by applying individual scanning signals that overlap in time only for a predetermined period, the display pixels of the plurality of rows are simultaneously set in a selected state in the predetermined period.

  According to a fourth aspect of the present invention, in the display device according to any one of the first to third aspects, the signal driving unit sets the gradation signal generated for each display pixel to the selected state. For each of a plurality of rows of display pixels in the same column, time series data is sequentially output to the current writing means.

  According to a fifth aspect of the present invention, in the display device according to any one of the first to fourth aspects, the current writing unit outputs the gradation signal supplied as the time-series data for each column to each row. A signal holding unit for holding each of the display pixels individually, and a current corresponding to the gradation signal held in the signal holding unit for each of the display pixels in the plurality of rows via the individual data lines. And a gradation current output section that outputs the gradation current.

  According to a sixth aspect of the present invention, in the display device according to the fifth aspect, the current writing means includes a plurality of sets of the signal holding unit and the grayscale current output unit arranged in parallel for each column. And a signal distribution unit that distributes and supplies the gradation signal supplied as the time series data to the plurality of signal holding / output units, and the plurality of sets The signal holding / output unit outputs the gradation current to each of the display pixels in the plurality of rows via the individual data lines.

  According to a seventh aspect of the present invention, in the display device according to the sixth aspect, the current writing means includes a plurality of stages of the plurality of sets of signal holding / output units for each column, and the signal holding of one stage. The operation of fetching and holding the gradation signal by the output unit and the operation of outputting the gradation current from the signal holding / output unit at any other stage are executed in parallel at the same time. .

  According to an eighth aspect of the present invention, in the display device according to the sixth aspect, the current writing means includes one stage of the plurality of sets of signal holding / outputting units for each column. The operation of outputting the gradation current based on the gradation signal at the same time as capturing and holding the gradation signal by the output unit, and the operation based on the gradation signal by any other set of the signal holding / output unit The operation of outputting the grayscale current is performed simultaneously in parallel for a predetermined period.

  According to a ninth aspect of the present invention, in the display device according to any of the fifth to eighth aspects, the gradation signal is a signal current having a current value corresponding to the display data, and the signal holding unit is And charge storage means for storing charges based on the signal current and holding them as voltage components.

  According to a tenth aspect of the present invention, in the display device according to the ninth aspect, the current writing unit generates the gradation current obtained by inverting a current polarity with respect to the gradation signal supplied from the signal driving unit. It has a current polarity reversal unit that generates and outputs to the display pixels in the plurality of rows.

  According to an eleventh aspect of the present invention, in the display device according to the ninth aspect, the gradation current output unit has a current mirror circuit configuration, and the gradation signal supplied from the signal driving means is predetermined. The gradation current having a current value of the current ratio is generated and output to the display pixels in the plurality of rows.

  According to a twelfth aspect of the present invention, in the display device according to the first aspect, at least the current writing unit and the light emission driving circuit have a single channel polarity in which the amorphous silicon semiconductor layer is a channel layer. It is characterized by using a type transistor.

According to a thirteenth aspect of the present invention, in the display device according to the first aspect, at least the current writing unit and the light emission driving circuit have a single channel polarity with a polysilicon semiconductor layer as a channel layer. It is characterized by using a type transistor.
A fourteenth aspect of the present invention is the display device according to any one of the first to thirteenth aspects, wherein the light emitting element is an organic electroluminescent element.

  In other words, the display device according to the present invention applies a gradation current corresponding to a display signal (display data) to each display pixel, whereby a light emitting element (organic EL element, current control type light emitting element) of each display pixel. In a display device that displays desired image information on a display panel by performing a light emission operation with a predetermined luminance gradation, a scanning signal from a scanning driver (scan driving means) is applied to display pixels that are two-dimensionally arranged on the display panel. Is applied to set the display pixels for a plurality of rows at the same time for at least a predetermined period, and the data driver (signal driving means) sequentially captures the display data corresponding to the display pixels of the plurality of rows, Data is generated by a current latch / distribution unit (current writing means) that generates a gradation signal (signal current) for each row and outputs it as time-series data (serial data) for each column. The gray scale signal output from the driver is fetched for each row, a gray scale current is generated based on the gray scale signal, and the display pixels of the plurality of rows set in the selected state are individually provided for each row. It is configured to write via a data line.

  Here, the scanning driver and the data driver are formed as driver chips separately from the insulating substrate on which the display panel is provided, and the current latch / distribution unit is provided integrally with the display panel on the insulating substrate. It has been. Therefore, at least the display pixels (light emission drive circuit) constituting the current latch / distribution unit and the display panel are constituted by, for example, thin film transistors (field effect transistors) having the same channel polarity, in particular, an amorphous silicon semiconductor layer or A thin film transistor having a polysilicon semiconductor layer as a channel layer is applied.

  Further, as a method of simultaneously setting the display pixels for a plurality of rows by the scan driver to a selected state for at least a predetermined period, a single scan signal is applied to a scan line commonly connected to the display pixels of the plurality of rows. Is applied to the display pixels in a plurality of rows at the same time in a selected state, or each of the scanning lines individually connected to the display pixels for each row is overlapped in time only for a predetermined period (overlapping). It is possible to apply a method in which individual scanning signals are applied and the display pixels in a plurality of rows are shifted in time and set in a selected state simultaneously in a predetermined period.

  Thus, by sequentially applying a single scanning signal or a plurality of scanning signals from the scanning driver, display pixels for a plurality of rows (k rows) can be set in a selected state at the same scanning timing. Compared with a known display device and a drive control method in which one scanning signal is applied to one scanning line to set one row of display pixels to a selected state, the writing time of gradation current to the display pixels is substantially reduced. Can be set to a multiple of (k times) longer.

  In addition, by setting the number of data lines arranged in each column according to the number (k) of rows set in the selected state at the same scanning timing, the display pixels connected to each data line Since the number is reduced, the capacitance component parasitic on each data line is reduced by a fraction (1 / k) as compared with the configuration of a known display device in which only one data line is provided in each column. Therefore, it is possible to shorten the writing time of the gradation current supplied to the display pixel via each data line, or to suppress the delay.

  Therefore, it is possible to ensure a sufficiently long writing time of display data to each display pixel and to suppress a signal delay of gradation current, so that the display panel is increased in size or increased in definition. In this case, or even during low gradation display, insufficient writing of display data can be solved, and each display pixel is operated to emit light at an appropriate luminance gradation according to the display data. Improvements can be made.

  In addition, even when the display panel has a higher definition, it is possible to suppress an increase in the number of output terminals of the driver chip (especially a scanning driver) and to suppress a reduction in the pitch (interval) between terminals. Therefore, it is possible to simplify position accuracy and reduce man-hours in the driver chip connection process. Furthermore, since the current latch / distribution unit can be formed on the same substrate integrally with the display panel (pixel array), it is possible to suppress the increase in the number of components and the product cost of the display device. it can.

  In the display device according to the present invention, the current latch / distribution unit has a current distribution circuit (signal distribution unit) that distributes, for each row, a gradation signal supplied as time-series data for each row from the data driver. ) And the distributed gradation signals are individually held in the storage capacitors (charge storage means) for each row, and the current corresponding to the gradation signals is set to the selected state via the individual data lines. A plurality of (for example, two sets) latch units (a signal holding / output unit including a signal holding unit and a gray level current output unit) that output as gradation currents to a plurality of rows of display pixels; The configuration can be applied.

Furthermore, the current latch / distribution unit has a configuration including a plurality of latch units for each column, and the plurality of latch units are provided in a plurality of stages (for example, two stages). An operation for capturing and holding a grayscale signal of a specific row and an operation for outputting a grayscale current based on the grayscale signal of the previous row to the display pixel of the row at the same time by the latch unit at the other stage A control operation to be performed, or a plurality of latch portions are provided in one stage, and one set of latch portions captures and holds a gradation signal of a specific row, and at the same time, a gradation current based on the gradation signal is supplied to the row. The operation of outputting to the display pixel and the operation of outputting the grayscale current based on the grayscale signal of the previous row to the display pixel of the previous row by the other set of latch units simultaneously in a predetermined period. It is also possible to perform a control operation to be executed.
As a result, the gradation signal supplied from the data driver corresponding to each column can be continuously taken in and held by the current latch / distribution unit, and the gradation current can be simultaneously supplied to the display pixels. .

  In addition, the latch unit generates a gradation current in which the polarity of the current is inverted with respect to the gradation signal supplied from the data driver (for example, a negative gradation current for the positive gradation signal). In addition, it may have a function (current polarity inversion unit) that outputs to a plurality of rows of display pixels, or a current mirror circuit is applied to the output stage (gradation current output unit) of the latch unit. In response to the grayscale signal supplied from the data driver, a grayscale current having a current value of a predetermined current ratio set by the current mirror circuit is generated and output to the display pixels in a plurality of rows. There may be.

Hereinafter, a display device according to the present invention will be described in detail with reference to embodiments.
<First Embodiment>
<Display device>
FIG. 1 is a schematic block diagram showing an overall configuration of a display device according to the present invention, and FIG. 2 is a schematic configuration diagram of a main part showing a first embodiment of a display device according to the present invention.

  As shown in FIG. 1 and FIG. 2, the display device 100 according to the present embodiment is roughly arranged corresponding to a plurality of (two) pixel rows, and a plurality (two in FIG. 2). Scan lines SLia and SLib (i is a positive integer in the range of 1 ≦ i ≦ n ′, for example, a divisor of the total number n of pixel rows set in the display panel 110A; n ′ and n are positive A plurality of (two in FIG. 2) data lines DLja and DLjb (j is 1), which are arranged corresponding to the scanning line group SGi having a set of integers) and each column (one column) of pixel columns. A positive integer in the range of ≦ j ≦ m; m is a positive integer, and the total number of pixel columns set in the display panel 110) and a set of scanning line groups SGi Each of the scan lines SLia, SLib constituting the data lines and the data lines DLja, DLjb constituting the respective data line groups DGj In the vicinity of the point, a plurality of display pixels EM connected via a selection transistor Trsel are connected to a display panel 110A in which a plurality of two-dimensional arrays (n rows × m columns) are arranged, and a scanning line group SGi of the display panel 110A. By sequentially applying the scanning signal Vsel to the line group SGi at a predetermined timing, the scanning pixels EM for a plurality of rows (two rows in FIG. 2) connected to the scanning line group SGi are simultaneously set to a selected state. A gradation signal (signal current) Ic of each row connected to the driver (scan driving means) 120A and the data line group DGj of the display panel 110A and sequentially supplied from the data driver 130 described later is given to each row at a predetermined timing. A current latch / distribution unit (current writing unit) 140A that distributes and holds the data for each of the plurality of rows (two rows in FIG. 2), and a display signal generation unit to be described later A data driver (signal driving means) 130 that captures the display data supplied from 60 and supplies it simultaneously to the current latch / distribution unit 140A as a gradation signal Ic for each display pixel in each row, for example, a display signal generation unit 160 A system controller 150 that generates and outputs at least a scan control signal and a data control signal for controlling the operation state of the scan driver 120A, the data driver 130, and the current latch / distributor 140A based on the timing signal supplied from For example, display data (for example, digital data) is generated based on a video signal supplied from the outside of the display device 100 and supplied to the data driver 130, and the display data is displayed on the display panel 110A. Generate or extract timing signals (system clock, etc.) And it is configured to include a display signal generation unit 160 supplies to the system controller 150 to the.

  In the display device according to the present embodiment, particularly, as shown in FIG. 2, on the insulating substrate BASE on which the plurality of display pixels EM (that is, the pixel array) forming the display panel 110A is formed, Along with the pixel array, at least a current latch / distribution unit 140A is integrally formed. The circuit configuration and element characteristics of each display pixel EM and current latch / distribution unit 140A will be described in detail later.

Hereafter, each said structure is demonstrated concretely.
(Display panel 110A)
For example, as shown in FIG. 2, the display panel 110A applicable to the display device according to the present embodiment includes a pair of scanning lines SLia and SLib branched into two, and corresponds to two pixel rows. The scanning line group SGi and two data lines DLja and DLjb each constitute a set, and the data line group DGj corresponding to one pixel column is arranged so as to be orthogonal to each other. A display pixel EM is connected to each intersection with the data line DLja and each intersection with each scanning line SLib and the data line DLjb.
In the configuration shown in FIG. 2, the odd-numbered display pixels EM are connected to the scan lines SLia of each scan line group SGi, and the even-numbered display pixels EM are connected to the scan lines SLib. Yes.

  Note that the number of rows corresponding to the scanning lines constituting each scanning line group SGi is not limited to that having each scanning line group SGi having a configuration corresponding to two rows of display pixels EM, as shown in FIG. For example, n / k sets (that is, the above n ′ sets) of scanning line groups corresponding to display pixels EM corresponding to k rows (k is a divisor of the total number n of pixel rows set in the display panel 110). SGi may be provided, or one set (single) of scanning line groups is provided corresponding to all pixel rows (n rows) constituting the display panel 110A, and all display pixels EM for one screen are provided. It may have a configuration commonly connected to the scanning line group. In the latter case, all the display pixels EM for one screen are collectively set to a selected state by a single scanning signal output from the scanning driver 120A.

  Each display pixel EM has a configuration in which a gate terminal is connected to each scanning line SLia or SLib, and a source terminal is connected to a drain terminal of a selection transistor Trsel connected to each data line DLja or DLjb. Based on the gradation current Ipix supplied from the current latch / distribution unit 140A via each data line DLja or DLjb and the selection transistor Trsel, a current control type light emitting element that emits light at a predetermined luminance gradation is provided. I have.

  In the display panel 110A having such a configuration, by applying a scanning signal Vsel to a specific scanning line group SGi from a scanning driver 120A described later, a plurality of (two) scanning lines SLia constituting the scanning line group SGi. The selection transistors Trsel connected to SLib are turned on, and the display pixels EM for two rows are collectively set to the selected state. In a state in which the scanning signal Vsel is applied to the specific scanning line group SGi (selected state), the gradation current Ipix corresponding to the display data is applied to each data line group DGj from the data driver 130 and the current latch / distribution unit 140A described later. By supplying all at once, the display data is collectively written to the display pixels EM for two rows set to the selected state via the selection transistor Trsel that is turned on. A specific circuit example and circuit operation of the display pixel EM including the selection transistor will be described in detail later.

(Scanning driver 120A)
The scan driver 120 sequentially executes the operation of applying the scan signal Vsel of the selection level (for example, high level) to each of the scan line groups SGi based on the scan control signal supplied from the system controller 150, thereby The display pixels EM for two rows connected to the scanning lines SLia and SLib constituting the scanning line group SGi are simultaneously set to the selected state, and the display supplied via the data line groups DGj by the data driver 130 described later. Control is performed so that the gradation current Ipix based on the data is simultaneously written in the display pixels EM.

  For example, as shown in FIG. 2, the scan driver 120A includes a plurality of stages (shift blocks SB1, SB2,... SBi,... SBn ′ each including a shift register and a buffer corresponding to each scan line group SGi. In FIG. 2, n ′ = n / 2; where n is the total number of pixel rows set in the display panel 110A, and scanning control signals (scanning start signal SST, scanning clock signal SCK, etc.) supplied from the system controller 150 to be described later ), A shift signal output while being sequentially shifted from the top to the bottom of the display panel 110A by the shift register is used as each scanning line group SGi as a scanning signal Vsel having a predetermined selection level (high level) via the buffer. To be applied.

  As described above, when all the display pixels EM constituting the display panel 110A have a configuration connected to the single scanning line group SGi, the shift block as shown in FIG. By applying a single scanning signal Vsel to the scanning line group SGi at a predetermined timing based on the scanning control signal, all the display pixels EM for one screen are collectively set to a selected state.

(Data driver 130)
Based on the data control signal supplied from the system controller 150, the data driver 130 sequentially captures and holds display data supplied from the display signal generation unit 160 described later for each row at a predetermined timing. The operation of simultaneously supplying gradation signals (signal currents) Ic having current values corresponding to the gradation values to the current latch / distribution unit 140A, which will be described later, in units of rows is sequentially repeated for one screen. The specific configuration and operation of the data driver 130 will be described later in detail.

(Current latch / distribution unit 140A)
Based on the data control signal supplied from the system controller 150, the current latch / distribution unit 140A generates the gradation signal Ic based on the display data supplied from the data driver 130 for each data line group DGi at a predetermined timing. Sequentially capture and hold each display pixel EM connected to a specific scan line group SGi in each column, and hold the above-mentioned hold at the timing when the scan driver 120 described above sets the specific scan line group SGi to the selected state. The gradation signal Ic is supplied as a gradation current Ipix to the display pixels EM in a plurality of rows (two rows in FIG. 2) through each data line group DGj.

  Specifically, for example, as shown in FIG. 2, the current latch / distribution unit 140A is generated corresponding to each column (each data line group DGj) based on display data at least by the data driver 130. A plurality of current distribution circuits 141 that sequentially capture the gradation signal Ic and distribute it for each row (display pixel EM) corresponding to the specific scanning line group SGi, and each data line group DGj disposed on the display panel 110A. A plurality of current latch circuits 142 that hold the grayscale signals Ic for each row of each column distributed by the current distribution circuit 141 in parallel, and each current distribution circuit 141 and current latch Two rows connected to the scanning lines SLia and SLib constituting each scanning line group SGi at the timing based on the data control signal by the configuration comprising the circuit 142 Are sequentially acquired, distributed and held for each row, and at the timing when the scanning line group SGi is set to the selected state, two rows of data are passed through each data line group DGi. A gradation current Ipix based on the held gradation signal Ic is generated and supplied to all display pixels EM in a batch. The specific configuration and operation of the current latch / distributor 140A will be described later in detail.

(System controller 150)
The system controller 150 outputs the scanning control signal and the data control signal for controlling the operation state to the scanning driver 120A, the data driver 130, and the current latch / distribution unit 140A described above. The latch / distribution unit 140A is operated at a predetermined timing to generate and output the scanning signal Vsel, the gradation signal Ic, and the gradation current Ipix, and the display data generated by the display signal generation unit 160 is written to each display pixel EM. Is controlled to display the predetermined image information based on the video signal on the display panel 110A.

(Display signal generator 160)
For example, the display signal generation unit 160 extracts a luminance gradation signal component from a video signal supplied from the outside of the display device 100, and supplies it to the data driver 130 as display data for each row of the display panel 110A. Here, when the video signal includes a timing signal component that defines the display timing of image information, such as a television broadcast signal (composite video signal), the display signal generation unit 160 displays the luminance gradation signal component. In addition to the function of extracting the timing signal component, the timing signal component may be extracted and supplied to the system controller 150. In this case, the system controller 150 performs scanning control signals and data supplied to the scanning driver 120A, the data driver 130, and the current latch / distribution unit 140A based on the timing signal supplied from the display signal generation unit 160. Generate a control signal.

<Specific examples of data driver>
Next, a configuration example of the data driver applicable to the display device according to the present embodiment will be specifically described.
FIG. 3 is a block diagram illustrating an example of a data driver applicable to the display device according to the present embodiment.

  For example, as shown in FIG. 3, the data driver 130 is a shift register circuit that outputs a shift signal while sequentially shifting the sampling start signal STR based on a shift clock signal CLK supplied as a data control signal from the system controller 150. 131, based on the data latch circuit STB, a data register circuit 132 for sequentially fetching display data D0 to Dm (digital data) for one row supplied from the display signal generator 160 based on the input timing of the shift signal. Based on the data latch circuit 133 that holds the display data D0 to Dm for one row captured by the data register circuit 132 and the gradation reference voltages V0 to Vp supplied from the power supply means (not shown), The stored display data D0 to Dm are stored in a predetermined analog A D / A converter 134 for converting the signal voltage (grayscale voltage Vpix) and a grayscale signal (signal current) Ic corresponding to the display data converted to the analog signal voltage are generated and supplied from the system controller 150. On the basis of the output enable signal OE, each data line group DGj arranged in the display panel 110, and for each display pixel EM of a plurality of rows (two rows) connected to each scanning line group SGi. And a voltage / current conversion / current supply circuit 135 that sequentially supplies the current latch / distribution unit 140A (each current distribution circuit 141 and the current latch circuit 142).

<Specific examples of current latch / distribution unit>
Next, a specific example of a current latch / distribution unit applicable to the display device according to the present embodiment will be described.
FIG. 4 is a circuit configuration diagram showing a configuration example of a current latch / distribution unit applicable to the data driver of the display device according to the present embodiment. Here, only one configuration example applicable to the display device according to the present embodiment is shown, and the circuit configuration is not limited to this.

  As shown in FIG. 4, for example, each current distribution circuit (signal distribution unit) 141 constituting the current latch / distribution unit 140A receives the gradation signal Ic output from the data driver 130 described above on one end side of the current path ( Source terminal), the other end side (drain terminal) of the current path is connected to the first output contact N41a to the current latch circuit 142, and the first current supplied as a data control signal from the system controller 150 The switch Tr41a made of a thin film transistor to which the capture signal WTodd is applied to the control terminal (gate terminal) and the gradation signal Ic output from the data driver 130 are supplied to one end side (source terminal) of the current path, and the current path Is connected to the second output contact N41b to the current latch circuit 142 and supplied as a data control signal. Current capturing signal WTevn of has a switch Tr41b consisting TFT is applied to the control terminal (gate terminal), a configuration with a. Here, in the current distribution circuit 141 according to the present embodiment, as each of the switches Tr41a and Tr41b, for example, an n-channel field effect transistor having an amorphous silicon semiconductor layer or a polysilicon semiconductor layer as a channel layer is used. Applied.

  Each of the current latch circuits 142 is connected in common to the data lines DLja constituting the data line group DGj, and is a gradation signal output from the above-described current distribution circuit 141 via the first output contact N41a. The latch units (signal holding / output units) 142a and 142c to which Ic is commonly supplied are connected in common to the data line DLjb, and are output from the current distribution circuit 141 via the second output contact N41b. And a latch unit (signal holding / output unit) 142b and 142d to which the gradation signal Ic is commonly supplied.

  For example, as shown in FIG. 4, each latch unit 142a (or 142c) has a current path (source-drain) between the output contact N41a and the contact N42a (or N42c) of the current distribution circuit 141 described above. A thin film transistor Tr42a (or Tr42c) connected to the control terminal (gate) to which the first latch signal LCup (or second latch signal LClw) is applied, a contact N42a (or N42c), and a contact N43a (or , N43c), a thin film transistor Tr43a (or Tr43c) in which the first latch signal LCup (or the second latch signal LClw) is applied to the control terminal, and one end side of the current path is Connected to the contact N42a (or N42c), a predetermined low potential voltage (−Vcc) is applied to the other end, and the control terminal is connected to the contact N43a (or , N43c), one end of the current path is connected to the contact N42a (or N42c), the other end is connected to the data line DLja, and the second latch signal is connected to the control terminal. The thin film transistor Tr45a (or Tr45c) to which the LClw (or the first latch signal LCup) is applied, the storage capacitor Ca (connected between the contact N43a (or N43c) and the low potential voltage (−Vcc). Or Cc).

  Similarly to the latch portions 142a and 142c, for example, as shown in FIG. 4, each latch portion 142b (or 142d) is connected between the output contact N41b and the contact N42b (or N42d) of the current distribution circuit 141. A thin film transistor Tr42b (or Tr42d) in which a current path (source-drain) is connected between them and a first latch signal LCup (or second latch signal LClw) is applied to a control terminal (gate), and a contact N42b (Or N42d) and a contact point N43b (or N43d), a current path is connected, and the first latch signal LCup (or second latch signal LClw) is applied to the control terminal of the thin film transistor Tr43b (or Tr43d) and one end of the current path are connected to the contact N42b (or N42d), and a predetermined low potential voltage (-Vcc) is connected to the other end. Applied to the thin film transistor Tr44b (or Tr44d) whose control terminal is connected to the contact N43b (or N43d), one end of the current path is connected to the contact N42b (or N42d), and the other end is connected to the data line DLjb The thin film transistor Tr45b (or Tr45d) to which the second latch signal LClw (or the first latch signal LCup) is applied to the control terminal, the contact N43b (or N43d), and the low potential voltage (−Vcc) Storage capacitor Cb (or Cd) connected between the two.

Here, in the current latch circuit 142 according to the present embodiment, each of the thin film transistors Tr42a to Tr45a, Tr42b to Tr45b, Tr42c to Tr45c, Tr42d to Tr45d is, for example, an amorphous silicon semiconductor layer, similar to the current distribution circuit 141 described above. Alternatively, an n-channel field effect transistor using a polysilicon semiconductor layer as a channel layer is applied. Further, the storage capacitors Ca to Cd provided in the latch units 142a to 142d may be parasitic capacitors formed between the gate and the source of the thin film transistors Tr44a to Tr44d, respectively.
In the current latch circuit 142 described above, the storage capacitors Ca to Cd constitute the signal holding unit and the charge storage unit according to the present invention, and the thin film transistors Tr44a to Tr44d and Tr45a to Tr45d serve as the gradation current output unit according to the present invention. Constitute.

<Operation of current latch / distribution unit>
Next, the operation in the current latch / distribution unit having the above-described configuration will be described.
FIG. 5 is a conceptual diagram showing a schematic operation of a current latch / distributor applicable to the present embodiment. Here, of the latch units 142a to 142d constituting each current latch circuit 142, for the sake of convenience, only the latch units 142a and 142c are illustrated and described. However, similar operations are performed on the latch units 142b and 142d. Executed.

  The operation in the current latch / distribution unit 140A (current distribution circuit 141, current latch circuit 142) according to the present embodiment is supplied in time series from the data driver 130, and each of the scan lines SLia, SLib constituting the scan line group SGi. Current distribution operation for distributing the gradation signal (time-series data) Ic based on the display data to be written to the two rows of display pixels corresponding to the current distribution circuit 141 to the output contacts N41a side and N41b side, and the current distribution operation. A current latching operation in which the distributed gradation signal Ic is captured and held in either one of the latch portions 142a and 142b or 142c and 142d constituting the current latch circuit 142 in synchronization with each other, and the current In synchronization with the latch operation (current distribution operation), the latch units 142a and 142b constituting the current latch circuit 142 are provided. Or the current that simultaneously outputs the gradation current Ipix based on the gradation signal Ic held in the previous current latch operation to the data lines DLja and DLjb constituting the data line group DGj from the other side of 142c and 142d. Output operation, and repeatedly executing the current distribution operation for every scanning line group SGi of the display panel 110A, while holding the latch portions 142a and 142b and the latch portions 142c and 142d that constitute the current latch circuit 142 The current latching operation and the current output operation are controlled to be alternately executed.

  That is, in a period in which the gradation signal Ic supplied from the data driver 130 corresponding to each column based on the display data is fetched and held in one of the latch units constituting the current latch circuit 142, simultaneously. The gradation current Ipix is read out from the other latch side and is output, and the gradation current Ipix is substantially continuously acquired while acquiring the gradation signal Ic based on the display data in each column. The operation of outputting to the data line group DGj is executed.

The above operations will be specifically described below with reference to each circuit configuration of the current latch / distribution unit.
(Current distribution operation)
In the current distribution operation, the first and second current capture signals WTodd and WTevn supplied as data control signals from the system controller 150 are selectively set to a high level in the current distribution circuit 141 described above. Either one of the switches Tr41a or Tr41b is sequentially turned on, and in synchronization with the timing of the on operation, the grayscale signal Ic corresponding to the display pixel EM of each row is continuously output from the data driver 130, thereby The adjustment signal Ic is distributed for each row and is output to the individual latch portions 142a, 142c or 142b, 142d constituting the current latch circuit 142 described later via the output contacts N41a or N41b.

(Current latch operation / current output operation)
In the above-described current latch circuit 142 (latch units 142a to 142d), the first and second latch signals LCup and LClw supplied as data control signals from the system controller 150 are selectively set to a high level to output Among the latch portions 142a and 142c connected in parallel to the contact N41a, or the latch portions 142b and 142d connected in parallel to the output contact N41b, either one of the latch portions (latch portions 142a, 142b, or , The latch units 142c and 142d) are set to a current latch operation state, and the other latch unit (latch units 142c and 142d or latch units 142a and 142b) is set to a current output operation state described later.

  In the current latch operation, as shown in FIG. 5A (for convenience, only the latch units 142a and 142c are shown), the first latch signal LCup is set to the high level, and the second latch signal By setting Lclw to the low level, the thin film transistors Tr42a, Tr43a, Tr44a are turned on and the thin film transistor Tr45a is turned off in the latch unit 142a connected to the output contact N41a. At this time, the Tr 44a operates in the saturation region because the gate and the drain are electrically short-circuited by the Tr 43a. Thereby, the gradation signal Ic supplied from the data driver 130 and output to the output contact N41a via the switch Tr41a of the current distribution circuit 141 is supplied to the low potential voltage (−Vcc) via the thin film transistors Tr42a and Tr44a of the latch unit 142a. ) Side, the current level of the gradation signal Ic is converted into a voltage level between the gate and source of the thin film transistor Tr44a, and is stored as a charge in the storage capacitor Ca.

  In the current output operation, as shown in FIG. 5B, the first latch signal LCup is set to a low level and the second latch signal LClw is set to a high level. In the portion 142a, the thin film transistors Tr42a and Tr43a are turned off, and the thin film transistor Tr45a is turned on. At this time, the potential (high voltage) based on the charge (gradation signal Ic) accumulated in the storage capacitor Ca by the current latching operation is held at the contact N43a, so that the thin film transistor Tr44a continues to be turned on. As a result, the data line DLja disposed on the display panel 110 (not shown) is connected to the low potential voltage (−Vcc) via the thin film transistors Tr45a and Tr44a of the latch part 142a, and the data line DLja side (ie, The grayscale current Ipix flows so as to be drawn from the display pixel EM side toward the latch portion 142a (current latch circuit 142).

  Further, in the state where the first latch signal LCup is set to the low level and the second latch signal LClw is set to the high level (that is, the current output operation state of the latch unit 142a described above), the output contact point In the latch portion 142c connected in parallel to N41a, the thin film transistors Tr42c and Tr43c are turned on, the Tr44c is electrically shorted between the gate and the drain by the Tr43a, turned on in the saturation region, and the thin film transistor Tr45c is turned off. Therefore, the gradation signal Ic output to the output contact N41a flows to the low potential voltage (−Vcc) side through the thin film transistors Tr42c and Tr44c of the latch unit 142c, and the current level of the gradation signal Ic is the gate of the thin film transistor Tr44c. -Converted to voltage level between sources and stored Current latch operation that is stored as a charge on the amount Cc is performed.

  That is, during the period when either one of the latch units 142a and 142c is set to the current latch operation state, the other side is set to the current output operation state simultaneously. Such an operation state is similarly executed in the combination of the latch units 142b and 142d (not shown).

  In the current latch / distribution unit 140A according to the present embodiment, a positive tone signal Ic supplied from the data driver 130 to correspond to a circuit configuration of a pixel driving circuit provided in the display pixel EM described later. Has been described that has a function (current polarity reversal unit) that generates a negative gradation current Ipix (converts the current direction) and draws the gradation current Ipix from the data line (display pixel) side. The present invention is not limited to this, and a configuration in which a positive polarity grayscale current Ipix is generated according to the circuit configuration of the display pixel EM and the grayscale current Ipix is supplied to the data line (display pixel). It may have. Note that most of the known data drivers that are generally distributed and available on the market have a configuration that outputs a positive signal current (gradation signal Ic), and thus have the configuration described above. By applying the current latch / distribution unit, it is possible to easily generate a grayscale current whose current direction is converted using a known data driver.

<Display device drive control method>
Next, the drive control operation (drive control method) in the display device having the above-described configuration will be specifically described.
FIG. 6 is a timing chart for explaining a drive control operation (drive control method) in the display device according to the present embodiment. Here, the description will be made with reference to each configuration of the display device described above as appropriate.

  In the display device having the above-described configuration, first, the display signal generation unit 160 performs digital operation for causing each display pixel (light emitting element) EM constituting the display panel 110A to emit light with a predetermined luminance gradation from the video signal. Display data consisting of data is extracted and sequentially supplied to the data driver 130 as serial data for each row of the display panel 110A.

  The display data (digital data) supplied to the data driver 130 is converted into a gradation signal Ic corresponding to the display data at a timing based on the data control signal supplied from the system controller 150, and arranged on the display panel 110A. Is output to the current latch / distribution unit 140A provided corresponding to the data line group DGj of each column. Here, the gradation signal Ic output from the data driver 130 is a data line group DGj unit corresponding to each column of the display panel 110A. For example, the data lines DLja and DLjb constituting the data line group DGj are provided. Are output in time series so as to correspond to each row of each display pixel EM connected to.

  In the current latch / distribution unit 140A, as shown in FIG. 6, the grayscale signals Ic corresponding to the display pixels EM arranged in a plurality of rows (two rows) for each column are sequentially fetched, and the current is output from the system controller 150. The switches Tr41a and Tr41b of the current distribution circuit 141 are selectively turned on at a timing based on the supplied data control signals (first and second current capture signals WTodd and WTevn at a high level), and a current latch circuit A current distribution operation is sequentially performed in which the gradation signal Ic is sequentially supplied to the latch unit 142a (or 142c) and the latch unit 142b (or 142d) of 142.

  In synchronization with this timing, the current latch circuit 142 is based on the data control signals (the high-level first latch signal LCup and the low-level second latch signal LClw) supplied from the system controller 150. When the latch portions 142a and 142b are set in the current latch operation state, the respective storage capacitors Ca and Cb are provided with the respective rows (for example, the respective storage capacitors Ca and Cb only during the period in which the gradation signal Ic is supplied in the respective latch portions 142a and 142b. A current latch operation in which charges are accumulated based on the gradation signal Ic corresponding to the display pixels EM in the first and second rows) is sequentially executed.

  As shown in FIG. 6, the current distribution operation and the current latch operation are performed by changing the signal levels of the first and second current capture signals WTodd and WTevn and the first and second latch signals LCup and LClw. The gradation signal Ic corresponding to the two rows of display pixels EM based on the display data is supplied to each current latch circuit 142 by appropriately setting and repeating alternately on the latch units 142a and 142b side and the latch units 142c and 142d side. It is kept sequentially.

  Next, after the current latch operation, the current latch circuit 142 is based on the data control signals (the low-level first latch signal LCup and the high-level second latch signal LClw) supplied from the system controller 150. Since the latch units 142a and 142b are set in the current output operation state, the gray level current Ipix based on the charges stored in the storage capacitors Ca and Cb is converted into the data line group DGj in each latch unit 142a and 142b. A current output operation is performed in which the display pixels EM in each row (first row and second row) are supplied all at once via the data lines DLja and DLjb constituting the.

  Therefore, the gray level current Ipix is output from the current latch / distribution unit 140A via the data line group DGj of each column, and the scanning driver 120A performs high-level scanning at a timing based on the scanning control signal supplied from the system controller 150. By applying the signal Vsel to a specific scanning line group SGi, all the selection transistors Trsel connected to the scanning lines SLia and SLib constituting the scanning line group SGi are turned on, and a plurality of rows (first row) The gradation current Ipix supplied simultaneously through the data lines DLja and DLjb of each data line group DGj is written to each display pixel EM and the display pixels EM of the second row). The light emission operation is executed at a predetermined luminance gradation based on the adjustment current Ipix.

  Further, in the period in which the current output operation is being performed in each of the latch units 142a and 142b, as shown in FIG. 6, the data control signal (the first latch signal LCup at the low level, In addition, the latch units 142c and 142d of the current latch circuit 142 are set to the current latch operation state based on the high-level second latch signal LClw), so that each row continuously supplied from the data driver 130 The gradation signal Ic is captured by the latch units 142c and 142d, and is stored in the storage capacitors Cc and Cd based on the gradation signal Ic corresponding to the display pixel EM in each row (for example, the third row and the fourth row). A current latch operation for accumulating electric charge is sequentially performed.

  Next, after the current output operation in the latch units 142a and 142b, the system controller 150 sets the first latch signal LCup to the high level and the second latch signal LClw to the low level again. The latch units 142a and 142b are again set to the current latch operation state, so that the grayscale signals corresponding to the display pixels EM in the respective rows (for example, the fifth row and the sixth row) in each of the latch portions 142a and 142b. A current latch operation in which charges based on Ic are stored in the storage capacitors Ca and Cb is sequentially executed.

  At this time, since the latch units 142c and 142d of the current latch circuit 142 are set to the current output operation state, the gradation current Ipix based on the charges accumulated in the storage capacitors Cc and Cd at the previous timing is generated. A current output operation is performed in which the display pixels EM in each row (the third row and the fourth row) are simultaneously supplied via the data lines DLja and DLjb constituting the data line group DGj.

  As a result, in the current latch / distribution unit 140A, the current latch operation is performed on the two-stage latch units 142a and 142b and the latch units 142c and 142d that constitute each current latch circuit 142 provided corresponding to each column. The gradation signal Ic output from the data driver 130 corresponding to the display data of each row is continuously latched by current latching by repeating the control for executing the current output operation simultaneously in parallel every predetermined operation cycle. An operation is performed in which the signals are fetched and held in the circuit and supplied to the display pixels in a plurality of rows as the gradation current Ipix all at once.

  Therefore, in this embodiment, a single scanning signal is applied from a scanning driver to a display panel in which a plurality of display pixels are two-dimensionally arranged, so that display pixels for a plurality of rows (for two rows) are displayed. The plurality of display data corresponding to the display pixels of the plurality of rows are sequentially fetched and held by the data driver, and are set at a predetermined timing (for example, one scanning period). Since gradation currents for rows are supplied to each display pixel all at once, a single scanning timing is provided as compared with a known drive control method in which one scanning signal is applied to one scanning line. The number of scanning lines driven by (the number of selected display pixel rows) can be doubled, and the writing time of the gradation current to the display pixels is set to be substantially multiple times (doubled). can do.

  Further, the data lines arranged in each column are constituted by a data line group including a plurality (two) of data lines, so that a capacitance component parasitic on each data line (particularly provided in a display pixel described later). Storage capacity and parasitic capacitance) can be reduced to a fraction (1/2) compared to the configuration of a known display device in which one data line is arranged in one column. It is possible to shorten the writing time of the gradation current supplied to the data line to the display pixel or to suppress the delay.

  As a result, it is possible to ensure a sufficiently long writing time of display data to each display pixel. Therefore, even when the display panel is enlarged or high-definition or at the time of low gradation display. , Sufficiently charge the wiring capacity of the data line to a predetermined voltage, it is possible to eliminate the insufficient writing of display data, each display pixel is allowed to emit light at an appropriate luminance gradation according to the display data, It is possible to greatly reduce the luminance gradient (display unevenness) generated in the display panel and improve the display image quality.

  Further, the scanning lines arranged in each row are constituted by a scanning line group including a plurality (two) as a set, and a plurality of rows (two rows) of display pixels by a single scanning signal. Are collectively set to the selected state, so that the number of scanning signals output from the scanning driver to the display panel can be reduced to one-fifth (1/2). It is possible to reduce the number of connection terminals with the scanning driver to one-fifth (1/2).

  As a result, even when the display panel has a high definition, it is possible to suppress an increase in the number of output terminals of the driver chip and to suppress a reduction in the pitch (interval) between the terminals. It is possible to simplify position accuracy and reduce man-hours in the chip connection process. Furthermore, since the current latch / distribution unit can be formed on the same substrate integrally with the display panel (pixel array), it is possible to suppress the increase in the number of components and the product cost of the display device. it can.

  In the present embodiment, for convenience of explanation, a scan line group is provided so as to correspond to display pixels for two rows, and a data line group corresponding to the display pixels for two rows is provided. Although the case where two rows of display pixels are simultaneously set to a selected state by a single scanning signal has been described, the present invention is not limited to this.

  FIG. 7 is a main part schematic configuration diagram showing another configuration example of the display apparatus according to the present embodiment, and FIG. 8 is a main part schematic configuration diagram showing still another configuration example of the display apparatus according to the present embodiment. It is. That is, for example, as shown in FIG. 7, as a configuration of the display panel 110A, a scanning line group SGi disposed so as to correspond to two or more (four) pixel rows (display pixels EM). And a data line group DGj, which is composed of the number (4) of data lines DLja to DLjd corresponding to the plurality of rows and arranged so as to correspond to the pixel columns of each column, and a single scanning signal The display pixels EM for a plurality of rows (four rows) may be simultaneously set to the selected state by Vsel.

  Further, as shown in FIG. 8, as a configuration of a scanning line group (a layout shape of the scanning lines) arranged so as to correspond to a plurality of pixel rows (display pixels EM), for example, one scanning line Instead of branching SLi, it may be routed (turned back) in the display panel 110A and commonly connected to the display pixels EM of a plurality of rows (two rows).

<Second Embodiment>
Next, a second embodiment of the display device according to the present invention will be described in detail with reference to the drawings.
<Display device>
FIG. 9 is a main part schematic configuration diagram showing a second embodiment of the display device according to the present invention, and FIG. 10 is a circuit configuration showing one configuration example of a current latch / distribution unit applicable to the present embodiment. FIG. Here, about the structure equivalent to 1st Embodiment mentioned above, the same or same code | symbol is attached | subjected, and the description is simplified or abbreviate | omitted.

  In the first embodiment described above, a scanning line group SGi corresponding to a plurality of (two) pixel rows and a data line group DGj including a plurality of data lines corresponding to the plurality of rows are arranged. In this embodiment, the display panel and the peripheral circuit (scan driver, data driver, and current latch / distribution unit) corresponding to the display panel are provided. A display panel having a scan line and a data line group including a plurality of data lines corresponding to a plurality of rows (two rows), and peripheral circuits (scan driver, data driver and current latch) corresponding to the display panel -It has the structure provided with the distribution part.

As shown in FIG. 9, the display device according to the present embodiment is roughly divided into scan lines SLq (q is in a range of 1 ≦ q ≦ n) arranged corresponding to each pixel row (one row). A positive integer) and each of the data line groups DGj arranged corresponding to the pixel columns of each column (one column) and including a plurality of (two in FIG. 9) data lines DLja and DLjb. At a crossing point, a plurality of display pixels EM connected via a selection transistor Trsel are connected to a display panel 110B in which a plurality of display pixels EM are two-dimensionally arranged, and a scanning line SLq of the display panel 110B. By applying a signal Vsel, the display pixels EM of each row (one row) connected to the scan line SLq are sequentially connected to the scan driver (scan driving means) 120B and each data line group DLj. And The gradation signal (signal current) Ic of each row sequentially supplied from the data driver 130 described above is fetched for each row at a predetermined timing, and at the same time, the gradation current Ipix is applied to the data lines DLja and DLjb corresponding to each row of each column. And a current latch / distribution unit (current writing unit) 140B that sequentially outputs.
In the display device according to the present embodiment, the data driver 130, the system controller 150, and the display signal generation unit 160 are the same as those in the first embodiment (see FIG. 1) described above, and thus description thereof is omitted. To do.

  In the display device according to the present embodiment, as shown in FIG. 9, in particular, on an insulating substrate BASE on which a plurality of display pixels EM (that is, a pixel array) constituting the display panel 110B is formed, Along with the pixel array, at least a current latch / distribution unit 140B is integrally formed.

  Here, the scanning driver 120B sequentially executes an operation of applying a scanning signal Vsel of a selection level (for example, high level) to each of the scanning lines SLq based on the scanning control signal supplied from the system controller 150. The display pixels EM of each row connected to each scanning line SLq are simultaneously set to the selected state, and the display pixels EM of at least adjacent rows are simultaneously set to the selected state for a predetermined period of time. The grayscale current Ipix based on the display data supplied via the data line group DGj by the data driver 130 is controlled so as to be partially written in parallel to the display pixels EM of each row.

  For example, as shown in FIG. 9, the scan driver 120 includes a plurality of stages (FIG. 9) of shift blocks SB1, SB2,... SBi,. In this case, the shift signal is sequentially shifted from the upper side to the lower side of the display panel 110B by the shift register based on the scanning control signals (scanning start signal SST, scanning clock signal SCK, etc.) supplied from the system controller 150. The shift signal is output simultaneously (overlapping for a fixed period) for a predetermined period to at least adjacent scanning lines SLq, and applied to each scanning line SLq as a scanning signal Vsel via a buffer.

  Further, for example, as shown in FIG. 9, the current latch / distribution unit 140B includes at least a plurality of current latch / distribution circuits 143 individually connected to each data line group DGj. Specifically, as shown in FIG. 10, a latch unit (signal holding / output unit) 143a connected to the data line DLja constituting each data line group DGj and a latch unit (connected to the data line DLjb ( Signal holding / output unit) 143b.

  For example, as shown in FIG. 10, the latch unit 143a is configured such that the gradation signal Ic output from the data driver 130 described above is supplied to one end side of the current path (source-drain) and the other end side is connected to the contact N46a. The current path is connected between the thin film transistor Tr46a to which the first current capture signal WTodd is applied to the control terminal (gate) and the contact N46a and the contact N47a, and the first current capture signal WTodd is applied to the control terminal. The thin film transistor Tr47a to be applied, one end side of the current path is connected to the contact N46a, the other end side is connected to the low potential voltage (−Vcc), and the control terminal is connected to the contact N47a, and one end side of the current path is A thin film transistor connected to the low potential voltage (-Vcc), connected to the data line DLja at the other end, and connected to the contact N47a at the control terminal. And registers Tr49a, has a configuration provided with a storage capacitor Ce connected between the contact point N47a and a low level voltage (-Vcc).

  Similarly to the latch unit 143a, for example, as shown in FIG. 10, the latch unit 143b also supplies the gradation signal Ic output from the data driver 130 to one end side of the current path (source-drain). The other end is connected to the contact N46b, the current path is connected between the thin film transistor Tr46b to which the second current capture signal WTevn is applied to the control terminal (gate), and the contact N46b and the contact N47b, and the control terminal The thin film transistor Tr47b to which the current capture signal WTevn of 2 is applied, the thin film transistor whose one end side of the current path is connected to the contact N46b, the other end side is connected to the low potential voltage (−Vcc), and the control terminal is connected to the contact N47b. Tr48b, one end of the current path is connected to the low potential voltage (-Vcc), the other end is connected to the data line DLjb, the control terminal is a contact A thin film transistor Tr49b connected to 47b, and has a configuration including a storage capacitor Cf connected between the contact point N47b and the low level voltage (-Vcc).

Here, in the current latch / distribution unit 140B according to the present embodiment, each of the thin film transistors Tr46a to Tr49a and Tr46b to Tr49b is, for example, an amorphous silicon semiconductor layer or polysilicon as in the first embodiment described above. An n-channel field effect transistor using a semiconductor layer as a channel layer is used.
In the above-described current latch / distribution circuit 143, the storage capacitors Ce and Cf constitute the signal holding unit and the charge storage unit according to the present invention, and the thin film transistors Tr46a, Tr47a and Tr46b and Tr47b serve as the signal distribution unit according to the present invention. The thin film transistors Tr48a, Tr49a and Tr48b, Tr49b constitute a grayscale current output unit according to the present invention.

Next, the operation in the current latch / distribution unit having the above-described configuration will be described.
FIG. 11 is a conceptual diagram showing a schematic operation of a current latch / distributor applicable to the present embodiment.
The operation of the current latch / distribution unit 140B (current latch / distribution circuit 143) according to the present embodiment is a gradation signal based on display data corresponding to two rows of display pixels supplied in time series from the data driver 130. Ic is sequentially captured by the latch units 143a and 143b of the current latch / distribution circuit 143 connected in parallel, and at the same time, a gradation current Ipix based on the gradation signal (signal current) Ic is generated to generate a data line. Current latch / output operation for outputting individually to each data line DLja, DLjb constituting the group DGj at a predetermined timing, and current output for continuing the output of the gradation current Ipix in the current latch / output operation for a predetermined period Holding operation, and the current latching / output operation and the current output holding operation are alternately repeated between the latch unit 143a side and the 143b side. To be controlled. As a result, the output period of the gradation current Ipix from the latch units 143a and 143b in the current latch / output operation is set so as to partially overlap (overlap) each other.

The above operation will be specifically described below with reference to each circuit configuration of the current latch / distribution unit.
In the above-described current latch / distribution circuit 143 (latch units 143a and 143b), the first and second current capture signals WTodd and WTevn supplied as data control signals from the system controller 150 are selectively set to a high level. As a result, either one of the latch units 143a and 143b connected in parallel (the latch unit 143a or 143b) captures the gradation signal Ic and simultaneously corresponds to the gradation signal Ic. The output state of the gradation current Ipix is set to the current latch / output operation state that outputs the gradation current Ipix, and the other latch unit (latch unit 143b or 143a) is in the current latch / output operation state at the previous timing. The current output holding operation state is set to continue.

  Specifically, in the current latch / output operation, as shown in FIG. 11A, the first current capture signal WTodd is set to the high level and the second current capture signal WTevn is set to the low level. By setting the level, in the latch unit 143a, the thin film transistors Tr46a and Tr47a are turned on, and the Tr48a is electrically shorted between the gate and the drain by the Tr47a, and is turned on in the saturation region. Accordingly, the gradation signal (signal current) Ic supplied from the data driver 130 flows to the low potential voltage (−Vcc) side through the thin film transistors Tr46a and Tr48a of the latch unit 143a, and the current level of the gradation signal Ic is increased. It is converted into a voltage level between the gate and source of the thin film transistor Tr48a, and is stored as a charge in the storage capacitor Ce.

  At this time, the potential of the contact N47a rises with the accumulation of charges in the storage capacitor Ce, so that the thin film transistors Tr48a and Tr49a constituting the current mirror circuit are turned on, and the gradation signal Ic The gradation current Ipix having a predetermined current ratio set in the current mirror circuit is supplied from the data line DLja side through the thin film transistor Tr49a in the low potential voltage (−Vcc) direction (that is, from the display pixel EM side to the latch unit 143a direction). It flows to be drawn into.

  In the current output holding operation, as shown in FIG. 11 (b), the first current capture signal WTodd is set to a low level and the second current capture signal WTevn is set to a high level. Thus, the thin film transistors Tr46a and Tr47a are turned off in the above-described latch portion 143a. At this time, since the potential (high voltage) based on the electric charge (signal current Ic) accumulated in the storage capacitor Ca by the current latch / output operation is held at the contact N47a, the thin film transistor Tr49a continues to be on. Thus, the operation state in which the gradation current Ipix is drawn from the data line DLja side toward the latch unit 143a (current latch / distribution circuit 143) is maintained.

  Further, the first current capture signal WTodd is set to a low level and the second current capture signal WTevn is set to a high level (that is, the current output holding operation state of the latch unit 143a described above). In the latch section 143b connected in parallel to the latch section 143a, the thin film transistors Tr46b and Tr47b are turned on, and the Tr48b is electrically shorted between the gate and the drain by the Tr47b and is turned on in the saturation region. The gradation signal Ic flows to the low potential voltage (−Vcc) side through the thin film transistors Tr46b and Tr48b of the latch unit 143b, and the current level of the gradation signal Ic is converted to the voltage level between the gate and the source of the thin film transistor Tr48b. Is stored as a charge in the storage capacitor Cf and the potential of the contact N47b. Along with the rise, the thin film transistors Tr48b and Tr49b that constitute the current mirror circuit are turned on, and the grayscale current Ipix having a predetermined current ratio with respect to the grayscale signal Ic passes through the thin film transistor Tr49b from the data line DLjb side. Thus, a current latch / output operation that flows so as to be drawn in the low potential voltage (−Vcc) direction (that is, from the display pixel EM side toward the latch unit 143b) is performed.

That is, during the period when either one of the latch units 143a and 143b is set to the current latch / output operation state, the other side is set to the current output holding operation state simultaneously.
Note that also in the current latch / distribution unit 140B according to the present embodiment, in order to correspond to a circuit configuration of a pixel driving circuit provided in the display pixel EM, which will be described later, a positive tone signal Ic supplied from the data driver 130. In the above description, the negative gradation current Ipix corresponding to the above is generated and the gradation current Ipix is drawn from the data line (display pixel) side. However, depending on the circuit configuration of the display pixel EM, It may have a configuration in which the regulated current Ipix is generated and flows into the data line (display pixel).

<Display device drive control method>
Next, a drive control operation in the display device having the above-described configuration will be described.
FIG. 12 is a timing chart showing the drive control method for the display device according to the present embodiment.

  In the display device having the above-described configuration, first, the display data extracted by the display signal generation unit 160 is displayed on the display panel 110B at a timing based on the data control signal supplied from the system controller 150 by the data driver 130. Each row is sequentially fetched, converted into a gradation signal (signal current) Ic corresponding to the display data, and output to a current latch / distribution unit 140B provided corresponding to the data line group DGj of each column. .

  In the current latch / distributor 140B, as shown in FIG. 12, a data control signal (a high-level first current capture signal WTodd and a low-level second current capture) supplied from the system controller 150 Based on the signal WTevn), the latch unit 143a of the current latch / distribution circuit 143 is set to the current latch / output operation state, so that one row (for example, the first row) of display pixels EM is provided for each column. The corresponding gradation signal Ic is taken in, and the charge based on the gradation signal Ic is stored in the storage capacitor Ce. At the same time, the charge stored in the storage capacitor Ce and the current mirror circuit (thin film transistors Tr48a and Tr49a) are set. On the basis of the current ratio, a gradation current Ipix having a predetermined current value is generated, and the row (1) is transmitted through each data line DLja. Supplied to each of the display pixels EM of the eye) current latch output operation is performed.

  Next, after the current latch / output operation, based on the data control signals (the low-level first current capture signal WTodd and the high-level second current capture signal WTevn) supplied from the system controller 150. Thus, when the latch unit 143a of the current latch / distribution circuit 143 is set to the current output holding operation state, the gray level based on the electric charge (that is, the signal current Ic) stored in the storage capacitor Ce in the latch unit 143a. A current output holding operation is performed in which the current Ipix is continuously supplied to each display pixel EM in the row (first row) via each data line DLja.

  Further, in the period in which the current output holding operation is performed in the latch unit 143a, as shown in FIG. 12, the data control signal supplied from the system controller 150 (low-level first current capture signal WTodd, Further, the latch unit 143b of the current latch / distribution circuit 143 is set to the current latch / output operation state based on the high-level second current capture signal WTevn), so that it is continuously supplied from the data driver 130. The gradation signal Ic of the next row (for example, the second row) is captured by the latch unit 143b and charges are accumulated in the storage capacitor Cf. At the same time, the charges accumulated in the storage capacitor Cf, and The gradation current Ipix having a predetermined current value based on the current ratio set by the current mirror circuit (thin film transistors Tr48b, Tr49b) Generating and, via the respective data lines DLjb, supplied to each of the display pixels EM in the row (second row) current latch output operation is performed.

  Next, after the current output holding operation in the latch unit 143a, the system controller 150 sets the first current capture signal WTodd again to the high level and the second current capture signal WTevn to the low level again. As a result, the latch unit 143a is set to the current latch / output operation state again, and at the same time, charges based on the gradation signal Ic of the next row (for example, the third row) are stored in the storage capacitor Ce. The gradation current Ipix based on the charge accumulated in the storage capacitor Ce and the current ratio set by the current mirror circuit is supplied to each display pixel EM in the row (third row) via each data line DLja. The current latch / output operation supplied to is performed.

  At this time, since the latch unit 142b of the current latch / distribution circuit 143 is set to the current output holding operation state, the gradation current Ipix based on the charge accumulated in the storage capacitor Cf at the previous timing is The current output holding operation supplied to each display pixel EM in the row (second row) subjected to the current latch / output operation is executed via the data line DLjb.

  Thus, in the current latch / distribution unit 140B, the current latch / output operation and the current between the two-stage latch units 143a and 143b constituting each current latch / distribution circuit 143 provided corresponding to each column. The grayscale signal Ic corresponding to the display data of each row sequentially supplied from the data driver 130 is continuously latched by alternately repeating the control for executing the output holding operation in parallel at predetermined operation cycles. At the same time as being captured and held in the circuit, an operation is performed in which the gradation current Ipix is simultaneously supplied to the display pixels in each row.

  Accordingly, the gray level current Ipix is output from the current latch / distribution unit 140B via the data line group DLj of each column, and the scan driver 120 performs high-level scanning at a timing based on the scanning control signal supplied from the system controller 150. By applying the signal Vsel to at least the adjacent scanning lines SLq so as to overlap for a predetermined period, a plurality of rows corresponding to each scanning line SLi (for example, the first row and the second row) The gray scale current Ipix sequentially supplied via the data lines DLja and DLjb of each data line group DLj is written in the display pixel EM of the above-mentioned data line group DLj, and the light emission operation is performed at a predetermined luminance gray scale based on the gray scale current Ipix. Is executed.

  As described above, in the present embodiment, a scanning signal is overlapped on a display panel in which a plurality of display pixels are two-dimensionally arranged by a scanning driver so as to overlap at least a neighboring scanning line for a predetermined period. , The display pixels in each row are sequentially set to the selected state, and the display data corresponding to the display pixels in each row is sequentially fetched and held in the individual latch units by the data driver, and at the same time, the gradation current of each row is Are sequentially supplied to each display pixel, so that a simple configuration including latches for the number of data lines constituting the data line group of each column can be simultaneously applied to a plurality of rows of display pixels. On the other hand, the gradation current based on the display data can be written, and the writing time of the gradation current can be set to be substantially long.

  Specifically, as described above, the data line group arranged in each column is composed of two data lines, and two latch units are provided in the current latch / distribution unit corresponding to the data lines. In the above configuration, it is possible to set so that a half period of the selection period of the display pixel in the specific row by the scanning signal overlaps with the selection period of the display pixel in the next row. That is, the selection period can be set to overlap between adjacent rows only during the period corresponding to the number of data lines constituting the data line group.

  Further, as in the first embodiment described above, the number of display pixels connected to each data line constituting the data line group of each column is set to a known display in which one data line is arranged in one column. Since it can be reduced to a fraction (1/2) compared to the device, the writing time of the gradation current supplied to each data line to the display pixel is shortened or the delay is suppressed. can do.

  In the present embodiment, as described above, the display data corresponding to the display pixels in each row is captured and held in the latch unit by the data driver, and at the same time, the gradation currents in each row are generated and sequentially applied to the display pixels. Since it is configured to supply, it is necessary to quickly execute the latch operation in the current latch / distribution circuit (latch unit), and if there is a shift in the timing of the latch operation due to signal delay etc., display operation May cause trouble.

  Therefore, in this embodiment, the display data (grayscale signal) is latched quickly with a small current in the current latch / distribution circuit (latch unit), and the current stage is connected to the output stage to each data line. By applying the mirror circuit configuration, it is possible to easily control the current value (absolute value) of the gradation current to increase the current, thereby suppressing the delay of the latch operation.

<Specific circuit example of display pixel>
Next, specific circuit examples of display pixels applicable to the display device according to the present invention will be described with reference to the drawings.
FIG. 13 is a circuit configuration diagram illustrating a specific circuit example of a display pixel (pixel driving circuit, light emitting element) applicable to the display device according to the present invention, and FIG. 14 illustrates driving of the pixel driving circuit according to the present embodiment. It is a conceptual diagram which shows control operation. FIG. 15 is a schematic block diagram illustrating a configuration example of a display device to which the display pixel according to the present embodiment is applied.

  As shown in FIG. 13, the display pixel EM ′ according to the present example (configuration including the display pixel EM and the selection transistor Trsel described in each of the above embodiments) is roughly the above-described scan driver 120A (or 120B). The display pixel EM ′ is set to a selected state based on the scanning signal Vsel applied from the pixel, and the gradation current Ipix supplied from the current latch / distribution unit 140A (or 140B) is captured in the selected state, and the gradation is Based on a pixel drive circuit (including the above-described selection transistor Trsel; light emission drive circuit) DC that sends a light emission drive current corresponding to the current Ipix to the light emitting element, and a predetermined light emission drive current supplied from the pixel drive circuit DC And a current-controlled light-emitting element such as an organic EL element OEL that emits light at a luminance gradation.

  For example, as shown in FIG. 13, the pixel drive circuit DC has a control terminal (gate terminal) that is a scanning line SLi (each scanning line SLia, SLib that constitutes the scanning line group SGi shown in each of the above embodiments, or SLq), an n-channel thin film transistor Tr11 having a current path (source-drain) connected to the power supply line VL and the contact N11, a control terminal to the scanning line SLi, and a current path to the data line DLj (each of the above-described implementations). N-channel type thin film transistor Tr12 connected to each data line DLja, DLjb) and contact N12 constituting the data line group DGj shown in the embodiment, a control terminal to the contact N11, a current path to the power supply line VL and the contact N12. Are connected between the n-channel thin film transistor Tr13 and the contact N11 and the contact N12. Comprising a capacitor (holding capacitance) Cs that is, a structure having a, the contact point N12 is the anode terminal of the organic EL element OEL, a cathode terminal are respectively connected to the ground potential. Here, the capacitor Cs may be a parasitic capacitance formed between the gate and the source of the thin film transistor Tr13. The thin film transistor Tr12 corresponds to the selection transistor Trsel shown in each of the above embodiments.

  The light emission drive control of the light emitting element (organic EL element OEL) in the pixel drive circuit DC having such a configuration is performed, for example, with one scan period Tsc as one cycle, and a plurality of rows of display pixels EM within the one scan period Tsc. ′ Is set to the selected state so as to overlap at the same time or for a predetermined period, and the gradation current Ipix corresponding to the display data is written and held as a voltage component (writing operation period) Tse; A non-selection period (light emission operation period) in which a light emission drive current corresponding to the display data is supplied to the organic EL element OEL based on the voltage component written and held in the selection period Tse, and a light emission operation is performed at a predetermined luminance gradation. ) Tnse is set (Tsc = Tse + Tnse).

(Selection period)
That is, in the selection period Tse of the display pixel EM ′, first, the high-level scanning signal Vsel is applied to the specific scanning line SLi from the scanning driver, and the display pixels EM ′ in a plurality of rows are simultaneously (or predetermined). In addition, the low-level power supply voltage Vsc is applied to the power supply lines VL of the display pixels in the plurality of rows. In synchronization with this timing, a negative gradation current Ipix corresponding to display data is supplied to each data line DLj from the current latch / distribution unit to the plurality of rows of display pixels EM ′.

  As a result, as shown in FIG. 14A, the thin film transistors Tr11 and Tr12 constituting the pixel drive circuit DC are turned on, and the low-level power supply voltage Vsc becomes the contact N11 (that is, the gate terminal of the thin film transistor Tr13 and the capacitor Cs). Is applied to one end of the power supply voltage), and the gradation current Ipix is drawn in the direction of the current latch / distribution unit via the data line DL, so that a voltage level lower than the low-level power supply voltage Vsc is contacted. N12 (that is, the source terminal of the thin film transistor Tr13 and the other end of the capacitor Cs).

  As described above, the potential difference is generated between the contacts N11 and N12 (between the gate and the source of the thin film transistor Tr13), so that the thin film transistor Tr13 is turned on, and the thin film transistor Tr13, the contact N12, the thin film transistor Tr12, and the data line DL are Thus, a write current Ia corresponding to the gradation current Ipix flows in the direction of the current latch / distribution unit.

  At this time, a charge corresponding to a potential difference generated between the contacts N11 and N12 (between the gate and the source of the thin film transistor Tr13) is accumulated in the capacitor Cs and held (charged) as a voltage component. Further, the power supply line VL is applied with a power supply voltage Vsc having a voltage level equal to or lower than the ground potential, and the write current Ia is controlled to flow in the direction of the data line DL, so that the organic EL element OEL Since the potential applied to the anode terminal (contact N12) is lower than the potential of the cathode terminal (ground potential) and a reverse bias voltage is applied to the organic EL element OEL, the organic EL element OEL emits light. No drive current flows and no light emission operation is performed.

(Non-selection period)
Next, in the non-selection period Tnse after the end of the selection period Tse, the low-level scan signal Vsel is applied to the specific scan line SLi from the scan driver, and a plurality of rows of display pixels are set to the non-selection state. At the same time, a high-level power supply voltage Vsc is applied to the power supply lines VL of the display pixels in the plurality of rows. In synchronism with this timing, the gradation current Ipix drawing operation by the current latch / distributor is stopped.

  Accordingly, as shown in FIG. 14B, the thin film transistors Tr11 and Tr12 constituting the pixel drive circuit DC are turned off, and the power supply voltage to the contact N11 (that is, the gate terminal of the thin film transistor Tr13 and one end of the capacitor Cs). While the application of Vsc is cut off, the application of the voltage level due to the drawing operation of the gradation current Ipix by the current latch / distribution unit to the contact N12 (that is, the source terminal of the thin film transistor Tr13 and the other end of the capacitor Cs) is cut off. Therefore, the capacitor Cs holds the charge accumulated in the selection period described above.

  In this manner, the capacitor Cs holds the charging voltage during the writing operation, whereby the potential difference between the contacts N11 and N12 (between the gate and the source of the thin film transistor Tr13) is held, and the thin film transistor Tr13 is turned on. To maintain. Further, since the power supply voltage Vsc having a voltage level higher than the ground potential is applied to the power supply line VL, the potential applied to the anode terminal (contact N12) of the organic EL element OEL is the potential of the cathode terminal (ground potential). ).

  Therefore, a predetermined light emission drive current Ib flows in the forward bias direction from the power supply line VL to the organic EL element OEL via the thin film transistor Tr13 and the contact N12, and the organic EL element OEL emits light. Here, the potential difference (charge voltage) held by the capacitor Cs corresponds to the potential difference when the write current Ia corresponding to the gradation current Ipix is caused to flow in the thin film transistor Tr13. Therefore, the light emission drive current flowing down to the organic EL element OEL. Ib has a current value equivalent to the write current Ia.

Thereby, in the non-selection period Tnse after the selection period Tse, the light emission drive current continues via the thin film transistor Tr13 based on the voltage component corresponding to the display data (gradation current Ipix) written in the selection period Tse. Thus, the organic EL element OEL continues to emit light with a luminance gradation corresponding to display data.
Then, the above-described series of operations are sequentially executed for all the scanning lines SLi constituting the display panel 110A (or 110B) based on the above-described drive control operation of the display device. The display data is written, light is emitted at a predetermined luminance gradation, and desired image information is displayed.

  Here, in the pixel drive circuit DC according to the present embodiment, since all the thin film transistors Tr11 to Tr13 can be configured using thin film transistors having the same channel polarity (n-channel type), the current latch / distribution unit described above is used. (Current distribution circuit, current latch circuit, current latch / distribution circuit) n-channel field effect transistor having an amorphous silicon semiconductor layer or a polysilicon semiconductor layer as a channel layer, similar to the circuit configuration of 140A and 140B Can be applied.

  According to this, together with the display panel (pixel array) in which the display pixels are two-dimensionally arranged, the above-described current latch / distribution unit can be integrally formed on a single insulating substrate. In particular, when the display panel and the current latch / distribution unit are configured by applying an n-channel field effect transistor using an amorphous silicon semiconductor layer, the already established amorphous silicon manufacturing technology is applied. Thus, a field effect transistor with stable operating characteristics can be manufactured at a relatively low cost, so that a display device with excellent display image quality can be obtained easily and easily even when the display panel is increased in definition or size. It can be realized well.

  In addition, according to the pixel driving circuit DC having the circuit configuration as described above, a gray current Ipix having a relatively large current value corresponding to the luminance gradation of the display data is caused to flow by the data driver 130 to be organic. Since the capacitor Cs provided between the gate and the source of the light emission control transistor (thin film transistor Tr13) for causing the EL element OEL to perform a light emission operation can be charged (written) with a voltage corresponding to the gradation current Ipix. In addition to being able to set the writing time of the gradation current to the display pixel to be long by the display device drive control method, the writing speed can be improved to further improve the display response characteristics and the display image quality. .

  Here, in the pixel drive circuit DC according to the present embodiment, as a configuration for applying a predetermined power supply voltage Vcs to the power supply line VL, for example, as shown in FIG. 15, the power supply line VLi is parallel to the scanning line SLi of each row. Is provided in the peripheral region of the display panel 110C where the power supply line VLi is connected, and the scanning driver 120A outputs the scanning signal Vsel based on the power control signal supplied from the system controller 150. A configuration in which the power supply voltage Vcs having the predetermined voltage value is applied to each power supply line VLi from the power supply driver 170 in synchronization with the timing can be favorably applied.

  The display pixel EM ′ described above includes three thin film transistors as the pixel drive circuit DC, and draws the gradation current Ipix in the direction of the current latch / distribution unit (that is, the data driver direction) via the data line DLj. Although the circuit configuration corresponding to the current application method is shown, the present invention is not limited to this embodiment, and is at least a display device including a pixel driving circuit to which the current application method is applied, and a light emitting element Has a light emission control transistor that controls the supply of light emission drive current to the light source and a write control transistor that controls the write operation of the gray scale current, and holds the gray scale current (write current) according to the display data Thereafter, based on the gradation current, the light emission control transistor is turned on to supply a light emission driving current, and the light emitting element emits light with a predetermined luminance gradation. Any other circuit configuration may be used, for example, it may have a circuit configuration including four thin film transistors, and further, a current latch / distribution unit (that is, the data driver side). The circuit configuration may be such that a gray-scale current flows in the direction of the display pixel (pixel drive circuit) via the data line.

  In the above-described embodiments, the configuration in which the organic EL element is applied as the light emitting element constituting the display pixel is shown. However, the display device according to the present invention is not limited to this, and the supplied light emission driving current is used. In addition to the organic EL element described above, for example, a light-emitting diode or other light-emitting element can be favorably applied as long as it is a current-controlled light-emitting element that emits light with a predetermined luminance gradation according to the current value of it can.

It is a schematic block diagram which shows the whole structure of the display apparatus which concerns on this invention. It is a principal part schematic block diagram which shows 1st Embodiment of the display apparatus which concerns on this invention. It is a block diagram which shows an example of the data driver applicable to the display apparatus which concerns on this embodiment. It is a circuit block diagram which shows the example of 1 structure of the current latch and distribution part applicable to the data driver of the display apparatus which concerns on this embodiment. It is a conceptual diagram which shows schematic operation | movement of the current latch and distribution part applicable to this embodiment. 5 is a timing chart for explaining a drive control operation (drive control method) in the display device according to the embodiment. It is a principal part schematic block diagram which shows the other structural example of the display apparatus which concerns on this embodiment. It is a principal part schematic block diagram which shows the further another structural example of the display apparatus which concerns on this embodiment. It is a principal part schematic block diagram which shows 2nd Embodiment of the display apparatus which concerns on this invention. It is a circuit block diagram which shows one structural example of the current latch and distribution part applicable to this embodiment. It is a conceptual diagram which shows schematic operation | movement of the current latch and distribution part applicable to this embodiment. 4 is a timing chart illustrating a drive control method for the display device according to the embodiment. It is a circuit block diagram which shows the specific circuit example of the display pixel (pixel drive circuit, light emitting element) applicable to the display apparatus which concerns on this invention. It is a conceptual diagram which shows the drive control operation | movement of the pixel drive circuit which concerns on a present Example. It is a schematic block diagram which shows one structural example of the display apparatus to which the display pixel which concerns on a present Example is applied. It is the schematic which shows the principal part structural example of the light emitting element type display in a prior art. It is an equivalent circuit diagram which shows the structural example of the display pixel applied to the light emitting element type display in a prior art.

Explanation of symbols

100 Display devices 110A to 110C Display panel 120A, 120B Scan driver 130 Data driver 140A, 140B Current latch / distribution unit 141 Current distribution circuit 142 Current latch circuit 142a, 142b Latch unit 143 Current latch / distribution circuit 143a, 143b Latch unit 150 System Controller 160 Display signal generator EM, EM ′ Display pixel SGi Scan line group DGj Data line group DC Pixel drive circuit

Claims (14)

By supplying a gradation current based on display data to the two-dimensionally arranged display pixels constituting the display panel, each display pixel is caused to perform a light emission operation at a predetermined luminance gradation based on the display data. In a display device that displays desired image information on a display panel,
at least,
Scanning drive means for simultaneously setting the display pixels in a plurality of rows arranged in the display panel to a selected state for at least a predetermined period;
Signal driving means for generating a gradation signal for controlling the luminance gradation of the display pixel for each row based on the display data;
The gradation signal output from the signal driving means is captured to generate the gradation current having a current value based on the gradation signal, and the plurality of rows set in the selected state by the scan driving means Current writing means for writing the gradation current to each of the display pixels via a separate data line;
With
The display pixels arranged in the display panel include a light emission drive circuit that generates a predetermined light emission drive current based on the gradation current output from the current writing unit, and the light emission supplied from the light emission drive circuit. A current-controlled light-emitting element that emits light with a predetermined luminance gradation based on a current value of a drive current, and at least the display panel and the current writing unit are on a single insulating substrate A display device characterized in that the display device is provided. The display panel includes a plurality of scanning lines commonly connected to the plurality of rows of display pixels,
The display device according to claim 1, wherein the scan driving unit simultaneously sets the display pixels of the plurality of rows to a selected state by applying a single scan signal to each of the scan lines. The display panel includes a plurality of scanning lines connected to the display pixels for each row,
The scan driving means applies the individual scan signals that overlap in time only to a predetermined period to each of the scan lines, so that the display pixels of the plurality of rows are simultaneously selected in the predetermined period. The display device according to claim 1, wherein the display device is set as follows.   The signal driving means sequentially outputs the gradation signal generated for each display pixel as time-series data to the current writing means for each of the plurality of rows of display pixels in the same column set in the selected state. The display device according to claim 1, wherein the display device is a display device. The current writing means is for each column,
A signal holding unit that holds the gradation signals supplied as the time-series data individually for each row;
A gray scale current that outputs a current corresponding to the gray scale signal held in the signal holding section as the gray scale current to each of the display pixels in the plurality of rows via the individual data lines. An output section;
The display device according to claim 1, further comprising: The current writing means includes a signal holding / output unit composed of a plurality of sets of the signal holding unit and the gradation current output unit arranged in parallel for each column,
A signal distribution unit that distributes and supplies the gradation signals supplied as the time-series data to the plurality of sets of signal holding / output units,
6. The plurality of sets of signal holding / outputting units output the gradation current to each of the plurality of rows of display pixels via the individual data lines. Display device.   The current writing means includes a plurality of stages of the signal holding / outputting units of the plurality of sets for each column, and an operation of taking in and holding the gradation signal by the signal holding / outputting unit of one stage; The display device according to claim 6, wherein the operation of outputting the gradation current from the signal holding / output unit in any one of the stages is executed in parallel at the same time.   The current writing means is provided with a plurality of sets of signal holding / output units for each column, and the gray level signals are simultaneously captured and held by the signal holding / output units of one set. The operation of outputting the grayscale current based on the above and the operation of outputting the grayscale current based on the grayscale signal by any one of the other signal holding / outputting units are simultaneously performed in parallel during a predetermined period. The display device according to claim 6, wherein the display device is executed. The gradation signal is a signal current having a current value corresponding to the display data,
The display device according to claim 5, wherein the signal holding unit includes a charge storage unit that stores charges based on the signal current and holds the charges as a voltage component.   The current writing means generates the gradation current having a current polarity inverted with respect to the gradation signal supplied from the signal driving means, and outputs the gradation current to the display pixels in the plurality of rows. The display device according to claim 9, further comprising a portion.   The gradation current output unit has a current mirror circuit configuration, generates the gradation current having a current value of a predetermined current ratio with respect to the gradation signal supplied from the signal driving unit, The display device according to claim 9, wherein the display device outputs the display pixels to the plurality of rows.   2. The current writing unit and the light emission drive circuit are configured by using a field effect transistor having an amorphous silicon semiconductor layer as a channel layer and having a single channel polarity. The display device described.   2. The device according to claim 1, wherein at least the current writing means and the light emission drive circuit are configured using a field effect transistor having a single channel polarity and having a polysilicon semiconductor layer as a channel layer. The display device described.   The display device according to claim 1, wherein the light emitting element is an organic electroluminescent element.

Images