JP4513129B2 - Manufacturing method of multilayer ceramic electronic component and multilayer ceramic electronic component - Google Patents

Manufacturing method of multilayer ceramic electronic component and multilayer ceramic electronic component Download PDF

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JP4513129B2
JP4513129B2 JP2005194753A JP2005194753A JP4513129B2 JP 4513129 B2 JP4513129 B2 JP 4513129B2 JP 2005194753 A JP2005194753 A JP 2005194753A JP 2005194753 A JP2005194753 A JP 2005194753A JP 4513129 B2 JP4513129 B2 JP 4513129B2
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健一 鴛海
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Murata Manufacturing Co Ltd
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本発明は積層セラミックコンデンサ等の積層セラミック電子部品の製造方法、及び該製造方法により製造された積層セラミック電子部品に関する。   The present invention relates to a method for manufacturing a multilayer ceramic electronic component such as a multilayer ceramic capacitor, and a multilayer ceramic electronic component manufactured by the manufacturing method.

積層セラミックコンデンサ等の積層セラミック電子部品は、セラミックス素体の内部に内部電極が埋設され、さらに前記セラミック素体の両端面に下地電極が形成されると共に該下地電極はめっき皮膜で被覆され、下地電極とめっき皮膜とで外部電極を構成している。   A multilayer ceramic electronic component such as a multilayer ceramic capacitor has an internal electrode embedded in a ceramic body, and ground electrodes are formed on both end faces of the ceramic body, and the ground electrode is covered with a plating film. The electrode and the plating film constitute an external electrode.

そして、下地電極の形成方法としては、従来より、ディップ方式が広く使用されている。   As a base electrode forming method, a dip method has been widely used conventionally.

このディップ方式では、図5(a)に示すように、セラミック素体101の一方の端面101aを下にして定板103上に形成された導電性ペースト層104に前記セラミック素体101を浸漬し、次いで、図5(b)に示すように、セラミック素体101を上方に引き上げて乾燥させ、その後セラミック素体101を上下反転し、他方の端面101bにも導電性ペースト層104に浸漬して導電性ペーストを塗布し、乾燥させ、その後、焼付け処理を行い、これにより下地電極を形成している。   In this dip method, as shown in FIG. 5A, the ceramic body 101 is immersed in a conductive paste layer 104 formed on the surface plate 103 with one end face 101a of the ceramic body 101 facing down. Then, as shown in FIG. 5B, the ceramic body 101 is pulled upward and dried, and then the ceramic body 101 is turned upside down and immersed in the conductive paste layer 104 also on the other end face 101b. A conductive paste is applied and dried, and then a baking process is performed, thereby forming a base electrode.

しかしながら、この下地電極形成方法では、導電性ペースト層104に浸漬した直後は、図6(a)に示すように、導電性ペーストはセラミック素体101の端面101a近傍部分が濡れ上がり(図中、濡れ寸法eで示す。)、導電膜105が形成されるが、セラミック素体101を上方に引き上げると、引き上げ直後は図6(b)に示すように、導電膜105は自重により矢印d方向に垂れ下がる。このとき導電膜105はセラミック素体101と接触しているため濡れ寸法eに大きな変動は生じない。しかしながら、この状態を放置して導電膜105を乾燥させると、時間の経過と共に導電膜105は略中央部の厚みlが厚くなり、それ以外の部分、特に端面角部近傍の厚みwは薄くなる。そして、この状態で導電膜105は焼付け処理され、固形化されて下地電極が形成される。   However, in this base electrode forming method, immediately after being immersed in the conductive paste layer 104, as shown in FIG. 6A, the conductive paste wets the vicinity of the end surface 101a of the ceramic body 101 (in the drawing, As shown in FIG. 6B, when the ceramic body 101 is pulled upward, the conductive film 105 is moved in the direction of the arrow d by its own weight as shown in FIG. 6B. It hangs down. At this time, since the conductive film 105 is in contact with the ceramic body 101, the wet dimension e does not vary greatly. However, if this state is left to dry the conductive film 105, the conductive film 105 becomes thicker at the substantially central portion l with the passage of time, and the thickness w in the other portions, particularly in the vicinity of the end face corners, is reduced. . In this state, the conductive film 105 is baked and solidified to form a base electrode.

ところが、端面角部近傍の厚みwが薄くなると、後工程のめっき工程でセラミック素体をめっき液に浸漬したり、製品である積層セラミック電子部品を高温多湿下で長時間晒すと、めっき液や水分がセラミック素体内部や内部電極とセラミック層との界面に浸入したり、外部電極内の空隙に浸入し、その結果電子部品としての諸特性が低下するという問題点が生じる。   However, when the thickness w near the corners of the end face is reduced, the ceramic body is immersed in a plating solution in a subsequent plating process, or the product is exposed to a multilayer ceramic electronic component under high temperature and high humidity for a long time. Moisture permeates into the ceramic body and the interface between the internal electrode and the ceramic layer, or into the voids in the external electrode, resulting in a problem that various characteristics as an electronic component are deteriorated.

一方、特許文献1には、セラミック素体(セラミック焼結体)の両端面が、凹状面とされた積層セラミック電子部品が提案されている。   On the other hand, Patent Document 1 proposes a multilayer ceramic electronic component in which both end surfaces of a ceramic body (ceramic sintered body) are concave surfaces.

この特許文献1では、セラミック素体の両端面が凹状面とされているので、導電性ペーストが自重で垂れ下がっても、下地電極の膜厚、特に端面角部近傍での膜厚を或る程度確保することが可能であると考えられる。   In Patent Document 1, since both end surfaces of the ceramic body are concave surfaces, even if the conductive paste hangs down due to its own weight, the film thickness of the base electrode, in particular, the film thickness in the vicinity of the corners of the end surface is somewhat increased. It is thought that it can be secured.

特開2000−49032号公報JP 2000-49032 A

しかしながら、上記特許文献1は、所謂ツームストーン現象の発生を回避するためにセラミック素体の両端面を凹状面にしたものであることから、凹状面の深さ、すなわち凹み量が小さく、このため端面近傍の下地電極膜厚を十分に確保することができないという問題点があった。   However, in Patent Document 1, since both end faces of the ceramic body are concave surfaces in order to avoid the so-called tombstone phenomenon, the depth of the concave surface, that is, the amount of dents is small. There is a problem in that a sufficient thickness of the base electrode near the end face cannot be secured.

すなわち、ツームストーン現象とは、セラミック素体の端面部分をR状に丸めた場合、プリント基板上に積層セラミック電子部品を実装する際、はんだが固化する前に積層セラミック電子部品が立ち上がってしまう現象をいうが、特許文献1は、斯かるツームストーン現象に対処するためにセラミック素体の両端面を凹状面に形成していることから、凹状面の凹み量も比較的小さくて済み、例えば、長さ:1.6mm、幅:0.8mm、厚み0.8mmの積層セラミックコンデンサの場合、凹み量は3μmで十分である。そして、凹み量を増大させると生産コストの増加や製造工程の煩雑化を招くことから、凹み量を必要以上に大きくすることは通常は考慮されない。   That is, the tombstone phenomenon is a phenomenon in which, when the end surface portion of the ceramic body is rolled into an R shape, the multilayer ceramic electronic component rises before the solder is solidified when the multilayer ceramic electronic component is mounted on the printed circuit board. However, in Patent Document 1, since both end faces of the ceramic body are formed in a concave surface in order to cope with such a tombstone phenomenon, the amount of recesses in the concave surface may be relatively small. In the case of a multilayer ceramic capacitor having a length of 1.6 mm, a width of 0.8 mm, and a thickness of 0.8 mm, a dent amount of 3 μm is sufficient. And if the amount of dents is increased, the production cost is increased and the manufacturing process becomes complicated. Therefore, it is not normally considered to increase the amount of dents more than necessary.

しかしながら、本発明者の実験結果により、特許文献1に開示された程度の凹み量では、下地電極の端面角部近傍における膜厚を十分に確保することができず、めっき液に浸漬したり高温多湿下で長時間晒すと、めっき液や水分がセラミック素体内部や内部電極とセラミック層との界面に浸入して耐湿性が劣化したり、デラミネーションやクラック等の構造欠陥の発生原因になることが判明した。   However, according to the experiment results of the present inventors, with the amount of dents disclosed in Patent Document 1, it is not possible to ensure a sufficient film thickness in the vicinity of the corners of the end face of the base electrode. If exposed to high humidity for a long time, the plating solution and moisture enter the ceramic body and the interface between the internal electrode and the ceramic layer, resulting in deterioration of moisture resistance and causing structural defects such as delamination and cracks. It has been found.

一方、セラミック素体の両端面角部における下地電極の膜厚を確保するために、該下地電極の膜厚を厚くすると、導電性ペーストの消費量増加を招いてコストアップの原因になり、電極形状も歪(いびつ)になるおそれがある。   On the other hand, if the thickness of the base electrode is increased in order to ensure the thickness of the base electrode at the corners of the both end faces of the ceramic body, the consumption of the conductive paste is increased, resulting in an increase in cost. The shape may also be distorted.

本発明はこのような問題点に鑑みなされたものであって、めっき液や水分が下地電極から内部に浸入するのを防止することができ、良好な耐湿性を有し、かつ構造欠陥を有さない積層セラミック電子部品を高効率で得ることができる積層セラミック電子部品の製造方法、及び該製造方法を使用して製造された積層セラミック電子部品を提供することを目的とする。   The present invention has been made in view of such problems, and can prevent the plating solution and moisture from entering the inside of the base electrode, has good moisture resistance, and has structural defects. It is an object of the present invention to provide a method for manufacturing a multilayer ceramic electronic component that can obtain a multilayer ceramic electronic component that does not have a high efficiency, and a multilayer ceramic electronic component manufactured using the manufacturing method.

本発明者は上記目的を達成するために鋭意研究を行ったところ、セラミック素体の両端面を凹面形状に加工すると共に、凹面形状に加工された端面間の最小寸法Aと最大寸法Bとの比A/Bを0.985〜0.990に設定することにより、下地電極を介してめっき液や水分が内部に浸入することがなく、良好な耐湿性を有し、かつ構造欠陥の発生を抑制した積層セラミック電子部品を得ることができるという知見を得た。   The present inventor conducted intensive research to achieve the above object, and as a result, both end faces of the ceramic body were processed into a concave shape, and the minimum dimension A and the maximum dimension B between the end faces processed into the concave shape were determined. By setting the ratio A / B to 0.985 to 0.990, there is no penetration of plating solution or moisture into the inside through the base electrode, it has good moisture resistance, and structural defects are generated. The knowledge that the suppressed multilayer ceramic electronic component can be obtained was obtained.

本発明はこのような知見に基づきなされたものであって、本発明に係る積層セラミック電子部品の製造方法は、一端が表面に露出した内部電極を内蔵したセラミック素体の両端面を導電性ペーストに浸漬して導電膜を形成し、次いで、該導電膜に焼付け処理を施して前記セラミック素体の両端面に下地電極を形成し、その後、前記下地電極をめっき皮膜で被覆して外部電極を形成する積層セラミック電子部品の製造方法において、前記内部電極の一端が表面露出している側のセラミック素体の端面間の最小寸法Aと最大寸法Bとの寸法比A/Bが0.985〜0.990となるように、前記セラミック素体の両端面を凹面形状に形成することを特徴としている。 The present invention has been made on the basis of such knowledge, and the method for manufacturing a multilayer ceramic electronic component according to the present invention is characterized in that both end faces of a ceramic body incorporating an internal electrode with one end exposed on the surface are electrically conductive paste. Then, the conductive film is baked to form a base electrode on both end surfaces of the ceramic body, and then the base electrode is covered with a plating film to form an external electrode. In the method of manufacturing a multilayer ceramic electronic component to be formed, the dimension ratio A / B between the minimum dimension A and the maximum dimension B between the end faces of the ceramic body on the surface where one end of the internal electrode is exposed is 0.985. It is characterized in that both end faces of the ceramic body are formed in a concave shape so as to be 0.990.

また、本発明に係る積層セラミック電子部品は、一端が表面に露出した内部電極を内蔵したセラミック素体と、該セラミック素体の両端面に形成され前記内部電極と電気的に接続された下地電極と、該下地電極の表面にめっき形成された外部電極とを備えた積層セラミック電子部品において、前記内部電極の一端が表面露出している側のセラミック素体の端面間の最小寸法Aと最大寸法Bとの寸法比A/Bが0.985〜0.990となるように、前記セラミック素体の両端面が、凹面形状に形成されていることを特徴としている。 Further, the multilayer ceramic electronic component according to the present invention includes a ceramic body having an internal electrode with one end exposed on the surface, and a ground electrode formed on both end faces of the ceramic body and electrically connected to the internal electrode. And an outer electrode plated on the surface of the base electrode, and a minimum dimension A and a maximum dimension between the end faces of the ceramic body on the surface where one end of the internal electrode is exposed Both end faces of the ceramic body are formed in a concave shape so that a dimensional ratio A / B with B is 0.985 to 0.990 .

本発明の積層セラミック電子部品の製造方法及び積層セラミック電子部品によれば、セラミック素体の端面間の最小寸法Aと最大寸法Bとの寸法比A/Bが0.985〜0.990となるように前記セラミック素体の両端面を凹面形状に形成するので、その凹み量は適度に大きく、端面の表面積も大きくなり、導電膜の自重による垂れ下がりを防止することができる。したがって下地電極は端面角部近傍においても所望の膜厚を確保することができ、セラミック素体をめっき液に浸漬したり、製品である積層セラミック電子部品を高温多湿下で長時間晒しても、めっき液や水分がセラミック素体内部や内部電極とセラミック層との界面に浸入するのを防止することができ、耐湿性が良好で構造欠陥の発生を抑制することができる積層セラミック電子部品を得ることができる。しかも、凹み量が過度に大きくならないように寸法比A/Bの下限を0.985以上としているので、外部電極内部に微細な空洞(ピンホール)が形成されることもない。   According to the method for manufacturing a multilayer ceramic electronic component and the multilayer ceramic electronic component of the present invention, the dimensional ratio A / B between the minimum dimension A and the maximum dimension B between the end faces of the ceramic body is 0.985 to 0.990. Thus, since the both end surfaces of the ceramic body are formed in a concave shape, the amount of the recesses is moderately large, the surface area of the end surface is also increased, and sagging due to the weight of the conductive film can be prevented. Therefore, the base electrode can secure a desired film thickness even in the vicinity of the corners of the end face, even if the ceramic body is immersed in a plating solution, or even if the multilayer ceramic electronic component as a product is exposed to high temperature and high humidity for a long time, A multilayer ceramic electronic component that can prevent the plating solution and moisture from entering the inside of the ceramic body and the interface between the internal electrode and the ceramic layer, has good moisture resistance, and can suppress the occurrence of structural defects is obtained. be able to. In addition, since the lower limit of the dimension ratio A / B is set to 0.985 or more so that the amount of dents does not become excessively large, fine cavities (pinholes) are not formed inside the external electrode.

次に、本発明の実施の形態を図面に基づいて詳説する。   Next, embodiments of the present invention will be described in detail with reference to the drawings.

図1は、本発明に係る製造方法で製造された積層セラミック電子部品としての積層セラミックコンデンサの一実施の形態を示す概略斜視図であって、該積層セラミックコンデンサは、BaTiO等の誘電体材料からなるセラミック素体1の両端部に外部電極2a、2bが形成されている。 FIG. 1 is a schematic perspective view showing an embodiment of a multilayer ceramic capacitor as a multilayer ceramic electronic component manufactured by the manufacturing method according to the present invention. The multilayer ceramic capacitor is a dielectric material such as BaTiO 3. External electrodes 2a and 2b are formed on both ends of the ceramic body 1 made of

図2は図1のX−X断面図である。   2 is a cross-sectional view taken along the line XX of FIG.

すなわち、セラミック素体1の内部には積層方向にNi等を主成分とした内部電極3a〜3fが並設されると共に、セラミック素体1の両端部にはCuやAg−Pd等を主成分とした下地電極4a、4bが形成され、さらに耐熱性向上の観点から下地電極4a、4bの表面にはNi皮膜5a、5bがめっき形成され、またはんだ濡れ性向上の観点からNi皮膜5a、5bの表面にはSn皮膜6a、6bがめっき形成され、下地電極4a、4b、Ni皮膜5a、5b、及びSn皮膜6a、6bとで外部電極2a、2bを構成している。そして、内部電極3a、3c、3eは下地電極4bと電気的に接続され、内部電極3b、3d、3fは下地電極4aと電気的に接続され、内部電極3a、3c、3eと内部電極3b、3d、3fとの対向面間で静電容量を形成している。   That is, internal electrodes 3 a to 3 f mainly composed of Ni or the like are arranged in parallel in the stacking direction inside the ceramic body 1, and Cu, Ag—Pd, or the like is mainly disposed at both ends of the ceramic body 1. The base electrodes 4a and 4b are formed, and Ni coatings 5a and 5b are formed on the surface of the base electrodes 4a and 4b from the viewpoint of improving heat resistance. Alternatively, the Ni coatings 5a and 5b are formed from the viewpoint of improving wettability. Sn surfaces 6a and 6b are formed by plating on the surface, and the base electrodes 4a and 4b, Ni coatings 5a and 5b, and Sn coatings 6a and 6b constitute external electrodes 2a and 2b. The internal electrodes 3a, 3c, 3e are electrically connected to the base electrode 4b, the internal electrodes 3b, 3d, 3f are electrically connected to the base electrode 4a, and the internal electrodes 3a, 3c, 3e and the internal electrode 3b, Capacitance is formed between the surfaces facing 3d and 3f.

さらに、本実施の形態では、セラミック素体1の両端面1a、1bが凹面形状に形成されており、端面間の最小寸法Aと最大寸法Bとの寸法比A/Bが0.985〜0.990とされている。   Furthermore, in the present embodiment, both end faces 1a, 1b of the ceramic body 1 are formed in a concave shape, and the dimensional ratio A / B between the minimum dimension A and the maximum dimension B between the end faces is 0.985-0. .990.

すなわち、セラミック素体1の端面が略平坦状に形成されている場合、下地電極4a、4bを、後述するようにディップ方式でペースト層に浸漬して形成しようとすると、〔発明が解決しようとする課題〕の項でも述べたように、塗布された導電性ペーストが自重で垂れ下がって中央付近に集合するため、端面角部の膜厚が薄くなる。したがって、後工程であるめっき工程でめっき液がセラミック素体1の内部に浸入したり、或いは高温多湿下に長時間晒されると水分がセラミック素体の内部に浸入して耐湿性を損ない、その結果積層セラミックコンデンサの電気的特性が悪化するおそれがある。   That is, when the end face of the ceramic body 1 is formed in a substantially flat shape, when the base electrodes 4a and 4b are formed by dipping in the paste layer as described later, As described in the section, the applied conductive paste hangs down under its own weight and collects in the vicinity of the center, so that the film thickness at the end face corners becomes thin. Therefore, if the plating solution penetrates into the ceramic body 1 in the subsequent plating step, or if it is exposed to high temperature and humidity for a long time, moisture penetrates into the ceramic body and impairs moisture resistance. As a result, the electrical characteristics of the multilayer ceramic capacitor may be deteriorated.

そこで、本実施の形態では、セラミック素体1の端面1a、1bを凹面形状に形成することにより、端面角部近傍の膜厚を確保している。   Therefore, in the present embodiment, the end faces 1a and 1b of the ceramic body 1 are formed in a concave shape, thereby ensuring the film thickness in the vicinity of the end face corners.

また、寸法比A/Bを0.985〜0.990としたのは以下の理由による。   The reason why the dimensional ratio A / B is set to 0.985 to 0.990 is as follows.

寸法比A/Bが0.985未満になると、端面の凹面形状が鋭角的になり、このため、塗布後に焼付処理を行うと凹面形状の最深部近傍に微細な空洞、すなわちピンホールが形成され、該ピンホールを介してめっき液や水分が浸入するおそれがある。一方、寸法比A/Bが0.990を超えると、所期の作用効果を発揮することができず、下地電極4a、4bの端面角部の膜厚が薄くなってめっき液や水分の浸入を招くおそれがある。   When the dimensional ratio A / B is less than 0.985, the concave shape of the end face becomes acute, and when baking is performed after coating, a fine cavity, that is, a pinhole is formed near the deepest portion of the concave shape. There is a risk that a plating solution or moisture may enter through the pinhole. On the other hand, if the dimensional ratio A / B exceeds 0.990, the desired effect cannot be achieved, and the film thickness at the corners of the end faces of the base electrodes 4a and 4b becomes thin, so that the plating solution and moisture can enter. May be incurred.

そこで、本実施の形態では、寸法比A/Bを0.985〜0.990としている。   Therefore, in this embodiment, the dimensional ratio A / B is set to 0.985 to 0.990.

次に、上記積層セラミックコンデンサの製造方法を詳述する。   Next, a method for manufacturing the multilayer ceramic capacitor will be described in detail.

まず、BaCO、CaCO、SrCO、TiO、ZrO等のセラミック素原料を所定量秤量し、次いで、これらセラミック素原料をボールミルに投入して湿式で混合・粉砕し、その後、乾燥工程を経て所定条件下、仮焼処理を行ない、誘電体セラミック原料を得る。 First, a predetermined amount of ceramic raw materials such as BaCO 3 , CaCO 3 , SrCO 3 , TiO 2 , ZrO 2 are weighed, and then these ceramic raw materials are put into a ball mill, mixed and pulverized by a wet process, and then dried. Then, a calcination process is performed under a predetermined condition to obtain a dielectric ceramic raw material.

次に、この誘電体セラミック原料に有機バインダ及び有機溶剤を加えてボールミル内で湿式混合し、セラミックスラリーを作製した後、このセラミックスラリーをドクターブレード法等の成形法を使用して成形加工を施し、その後所定寸法に切断して矩形状のセラミックグリーンシートを得る。   Next, an organic binder and an organic solvent are added to the dielectric ceramic raw material and wet-mixed in a ball mill to produce a ceramic slurry. The ceramic slurry is then molded using a molding method such as a doctor blade method. Then, it is cut into a predetermined size to obtain a rectangular ceramic green sheet.

次いで、スクリーン印刷法等を使用してNiを主成分とする内部電極用導電性ペーストをセラミックグリーンシート上に塗布し、導電パターンを形成する。   Next, a conductive paste for internal electrodes containing Ni as a main component is applied onto the ceramic green sheet using a screen printing method or the like to form a conductive pattern.

次に、導電パターンが形成されたセラミックグリーンシートを所定方向に複数枚積層し、導電パターンの形成されていないセラミックグリーンシートで挟持し、圧着してセラミック積層体を作製する。   Next, a plurality of ceramic green sheets on which conductive patterns are formed are stacked in a predetermined direction, sandwiched between ceramic green sheets on which conductive patterns are not formed, and pressed to produce a ceramic stacked body.

そしてこの後、前記セラミック積層体に対し、所定条件下、脱バインダ処理を行った後、所定条件で焼成処理を施し、これにより内部電極3が埋設されたセラミック素体1を得る。   Thereafter, the ceramic laminate is subjected to a binder removal process under a predetermined condition, and then subjected to a firing process under the predetermined condition, thereby obtaining the ceramic body 1 in which the internal electrode 3 is embedded.

次に、セラミック素体1の端面間の寸法比A/Bが0.985〜0.990となるように端面1a、1bを凹面形状に加工する。   Next, the end faces 1a and 1b are processed into a concave shape so that the dimensional ratio A / B between the end faces of the ceramic body 1 is 0.985 to 0.990.

端面1a、1bを凹面形状に加工する方法としては、凸型形状の刃を使用してセラミック素体1の端面1a、1bに切削加工を施す方法、或いは、端面1a、1bをサンドブラストやレーザー光、ボール盤等で加工する方法がある。   As a method of processing the end surfaces 1a and 1b into a concave shape, a method of cutting the end surfaces 1a and 1b of the ceramic body 1 using a convex blade, or sandblasting or laser beaming the end surfaces 1a and 1b. There is a method of processing with a drilling machine.

次に、端面が凹面形状に形成されたセラミック素体1を、図3に示すように、一方の端面を定板7上に形成されたCuを主成分とするペースト層8に浸漬し、次いでセラミック素体1を引き上げて乾燥させ、その後、セラミック素体1を反転させて他方の端面を前記ペースト層8に浸漬させ、しかる後焼付け処理を行い、下地電極4a、4bを形成する。   Next, as shown in FIG. 3, the ceramic body 1 having an end surface formed in a concave shape is immersed in a paste layer 8 having Cu as a main component formed on the surface plate 7 as shown in FIG. The ceramic body 1 is pulled up and dried, and then the ceramic body 1 is inverted and the other end face is immersed in the paste layer 8 and then subjected to baking treatment to form the base electrodes 4a and 4b.

図4は下地電極4aとなる導電膜9の形成過程を経時的に示した図である。   FIG. 4 is a view showing the formation process of the conductive film 9 to be the base electrode 4a over time.

すなわち、セラミック素体1をペースト層に浸漬した直後は、図4(a)に示すように、セラミック素体1の端面1a近傍部分は導電性ペーストが濡れ上がり(図中、濡れ寸法Eで示す。)、導電膜9が形成される。そして、セラミック素体1を上方に引き上げると、引き上げ直後は、導電膜9は、図4(b)に示すように、自重で垂れ下がろうとする力が矢印D方向に分散され、導電膜7は楕円状となる。次いで、この状態を放置して導電膜9を乾燥させると、めっき液や水分の浸入を防止することが可能となるような略中央部の厚みL及び端面角部近傍の厚みWを有する導電膜7が形成され、焼付け処理により所望の膜厚が確保された下地電極4aを得ることができる。   That is, immediately after the ceramic body 1 is immersed in the paste layer, as shown in FIG. 4A, the conductive paste wets up in the vicinity of the end face 1a of the ceramic body 1 (indicated by the wetting dimension E in the figure). ), The conductive film 9 is formed. When the ceramic body 1 is lifted upward, immediately after the pulling, the conductive film 9 is dispersed in the direction of arrow D as shown in FIG. Becomes elliptical. Next, when the conductive film 9 is dried by leaving this state, the conductive film having a thickness L at a substantially central portion and a thickness W in the vicinity of an end face corner portion that can prevent infiltration of a plating solution or moisture. 7 is formed, and the base electrode 4a in which a desired film thickness is secured by the baking process can be obtained.

そしてこの後、電解めっきを施して下地電極4a、4bの表面にNi皮膜5a、5bを形成し、さらに該Ni皮膜5a、5bの表面にSn皮膜6a、6bを形成し、これにより積層セラミックコンデンサが製造される。   Thereafter, electrolytic plating is performed to form Ni coatings 5a and 5b on the surfaces of the base electrodes 4a and 4b, and Sn coatings 6a and 6b are further formed on the surfaces of the Ni coatings 5a and 5b. Is manufactured.

このように本実施の形態では、端面1a、1b間の最小寸法Aと最大寸法Bとの寸法比A/Bが0.985〜0.990となるようにセラミック素体1の両端面を凹面形状に加工しているので、ディップ方式で端面1a、1bに導電性ペーストを塗布しても、導電性ペーストが自重で垂れ下がるのを極力抑制することができ、したがって、セラミック素体1へのめっき液や水分の浸入が防止可能に端面角部の膜厚を確保することができ、構造欠陥の発生や耐湿性劣化を防止することができる。   Thus, in the present embodiment, both end faces of the ceramic body 1 are concave so that the dimensional ratio A / B between the minimum dimension A and the maximum dimension B between the end faces 1a and 1b is 0.985 to 0.990. Since it is processed into a shape, even if a conductive paste is applied to the end faces 1a and 1b by the dipping method, it is possible to suppress the conductive paste from sagging under its own weight as much as possible. The film thickness at the end face corners can be ensured so that liquid and moisture can be prevented from entering, and the occurrence of structural defects and deterioration in moisture resistance can be prevented.

また、端面角部の膜厚を確保するために、下地電極4a、4bの膜厚を必要以上に厚くする必要もなく、したがってペースト消費量も少なくて済み、コストダウンを図ることができ、電極形状も良好なものとすることができる。   In addition, in order to secure the film thickness at the end face corners, it is not necessary to increase the film thickness of the base electrodes 4a and 4b more than necessary, so that the paste consumption can be reduced and the cost can be reduced. The shape can also be good.

尚、本発明は上記実施の形態に限定されるものではない。上記実施の形態では、下地電極4a、4bの表面にNi皮膜5a、5b及びSn皮膜6a、6bをめっき形成しているが、Cuやはんだ等をめっき形成してもよい。   The present invention is not limited to the above embodiment. In the above embodiment, the Ni films 5a and 5b and the Sn films 6a and 6b are formed by plating on the surfaces of the base electrodes 4a and 4b. However, Cu, solder, or the like may be formed by plating.

また、上記実施の形態では、積層セラミックコンデンサについて説明したが、下地電極がデッィプ方式で形成されるものであれば適用可能であり、例えば、積層型圧電部品等の各種積層セラミック電子部品にも適用できるのはいうまでもない。   In the above embodiment, the multilayer ceramic capacitor has been described. However, the multilayer ceramic capacitor can be applied as long as the base electrode is formed by a dip method. For example, the multilayer ceramic capacitor is also applicable to various multilayer ceramic electronic components such as a multilayer piezoelectric component. Needless to say, you can.

次に、本発明の実施例を具体的に説明する。   Next, examples of the present invention will be specifically described.

まず、セラミック素原料としてのBaCO、TiOを所定量秤量し、次いで、これらセラミック素原料をボールミルに投入して湿式で混合・粉砕し、その後、乾燥工程を経て大気雰囲気下、800〜1300℃の温度で約2時間仮焼処理を行ない、BaTiOからなる誘電体セラミック原料を得た。 First, BaCO 3 and TiO 2 as ceramic raw materials are weighed in predetermined amounts, and then these ceramic raw materials are put into a ball mill, mixed and pulverized in a wet manner, and then subjected to a drying process in an air atmosphere at 800 to 1300. A calcining treatment was performed at a temperature of about 2 hours for about 2 hours to obtain a dielectric ceramic material made of BaTiO 3 .

次に、この誘電体セラミック原料に有機バインダ及び有機溶剤を加えてボールミル内で湿式混合し、セラミックスラリーを作製した後、このセラミックスラリーをドクターブレード法を使用して焼成後の膜厚が3μmとなるように成形加工し、その後所定寸法に切断して矩形状のセラミックグリーンシートを得た。   Next, an organic binder and an organic solvent are added to the dielectric ceramic raw material and wet mixed in a ball mill to produce a ceramic slurry. The ceramic slurry is then fired using a doctor blade method to a film thickness of 3 μm. Then, it was cut into a predetermined size to obtain a rectangular ceramic green sheet.

次いで、Niを主成分とする内部電極用導電性ペーストをセラミックグリーンシート上にスクリーン印刷し、所定の導電パターンを形成した。   Next, a conductive paste for internal electrodes containing Ni as a main component was screen-printed on a ceramic green sheet to form a predetermined conductive pattern.

次に、導電パターンが形成されたセラミックグリーンシートを所定方向に複数枚積層し、導電パターンの形成されていないセラミックグリーンシートで挟持し、圧着してセラミック積層体を作製した。尚、セラミックグリーンシートの有効積層数は300であった。   Next, a plurality of ceramic green sheets on which conductive patterns were formed were laminated in a predetermined direction, sandwiched between ceramic green sheets on which conductive patterns were not formed, and pressed to produce a ceramic laminate. The effective number of laminated ceramic green sheets was 300.

そしてこの後、前記セラミック積層体を、大気雰囲気下、約500℃の温度に加熱して有機バインダを燃焼させ、さらに所定の還元雰囲気下、850〜1000℃の温度で焼成処理を施し、これにより内部電極が埋設されたセラミック素体を得た。   After that, the ceramic laminate is heated to a temperature of about 500 ° C. in an air atmosphere to burn the organic binder, and further subjected to a firing treatment at a temperature of 850 to 1000 ° C. in a predetermined reducing atmosphere. A ceramic body with embedded internal electrodes was obtained.

次に、セラミック素体が、表1のような端面間寸法となるようにサンドブラストで端面を凹面形状に加工した。   Next, the end surface was processed into a concave shape by sand blasting so that the ceramic body had a dimension between end surfaces as shown in Table 1.

次いで、表1のような厚みを有するペースト層を定板上に形成し、セラミック素体の一方の端面を前記ペースト層に浸漬し、乾燥した後、セラミック素体1を反転させて他方の端面を前記ペースト層中に浸漬し、乾燥し、その後焼付け処理を施し、下地電極の形成された長さ:約3.2mm、幅:約2.5mm、厚み:約2.5mmからなる試料番号1〜15の試料を作製した。   Next, a paste layer having a thickness as shown in Table 1 is formed on a surface plate, and one end surface of the ceramic body is immersed in the paste layer and dried, and then the ceramic body 1 is inverted to the other end surface. Was immersed in the paste layer, dried, and then subjected to a baking treatment. Sample No. 1 having a length of about 3.2 mm, a width: about 2.5 mm, and a thickness: about 2.5 mm where the base electrode was formed. ~ 15 samples were made.

次に、各試料72個を温度70℃、相対湿度95%の高温多湿下で1000時間放置して耐湿試験を行った。次いで、耐湿試験前後の静電容量及び誘電損失tanδをキャパシタメーター(ヒューレットパッカード社製4268A)で測定し、また、絶縁抵抗測定機を使用し、6.3Vの電圧を120秒間印加して絶縁抵抗IRを測定した。そして、耐湿試験前後の静電容量の変化率が30%以内、誘電損失tanδが40%以下、絶縁抵抗IRが2.5×10Ω以上のいずれかを満足しないものを不良品と判断してその個数を計数し、耐湿性を評価した。 Next, 72 samples were left to stand for 1000 hours under high temperature and high humidity at a temperature of 70 ° C. and a relative humidity of 95% to conduct a moisture resistance test. Next, the capacitance before and after the moisture resistance test and the dielectric loss tan δ were measured with a capacitor meter (4268A manufactured by Hewlett Packard), and the insulation resistance was measured by applying a voltage of 6.3 V for 120 seconds using an insulation resistance measuring machine. IR was measured. A product that does not satisfy any of the following: the capacitance change rate before and after the moisture resistance test is within 30%, the dielectric loss tan δ is 40% or less, and the insulation resistance IR is 2.5 × 10 5 Ω or more. The number was counted and the moisture resistance was evaluated.

また、各試料200個の断面を電子顕微鏡で観察し、下地電極の凹部中にピンホールが形成されていないか否かを確認し、ピンホールが形成された試料を計数した。   In addition, the cross section of 200 samples was observed with an electron microscope to confirm whether or not pinholes were formed in the recesses of the base electrode, and the samples with pinholes were counted.

表1は端面間寸法、ペースト層厚、下地電極の焼付け処理後の最小膜厚及び最大膜、耐湿性不良個数、ピンホール発生個数をそれぞれ示している。   Table 1 shows the dimensions between the end faces, the paste layer thickness, the minimum film thickness and the maximum film after baking of the base electrode, the number of moisture resistance defects, and the number of pinholes generated.

ここで、最大膜厚は、セラミック素体のB寸法(図2参照)に対応する位置での下地電極の膜厚の平均値を示し、最小膜厚は、セラミック素体のA寸法(図2参照)に対応する位置での下地電極の膜厚の平均値を示している。   Here, the maximum film thickness indicates an average value of the film thickness of the base electrode at a position corresponding to the B dimension of the ceramic body (see FIG. 2), and the minimum film thickness is the A dimension of the ceramic body (FIG. 2). The average value of the film thickness of the base electrode at the position corresponding to (reference) is shown.

尚、端面間寸法はマイクロメータで測定した。また下地電極の最小膜厚、最大膜厚は積層セラミックコンデンサの切断面を研磨し、200倍に拡大した画像データで測定した。具体的には、最小膜厚は積層セラミックコンデンサの断面におけるセラミック素体の角部の下地電極の厚みを測定して得た。また、最大膜厚は積層セラミックコンデンサの断面におけるセラミック素体の端面凹部の最深部における下地電極の厚みを測定して得た。

Figure 0004513129
この表1から明らかなように、試料番号1〜3は、端面が略平坦状に形成されているため、下地電極の最小膜厚が3〜8μmと薄く、このため、水分がセラミック素体内部に浸入し、耐湿性不良が認められる試料が生じることが分かった。 In addition, the dimension between end faces was measured with a micrometer. Further, the minimum film thickness and the maximum film thickness of the base electrode were measured by polishing the cut surface of the multilayer ceramic capacitor and expanding the image data 200 times. Specifically, the minimum film thickness was obtained by measuring the thickness of the base electrode at the corner of the ceramic body in the cross section of the multilayer ceramic capacitor. The maximum film thickness was obtained by measuring the thickness of the base electrode at the deepest portion of the end face recess of the ceramic body in the cross section of the multilayer ceramic capacitor.
Figure 0004513129
As apparent from Table 1, since the end faces of Sample Nos. 1 to 3 are formed in a substantially flat shape, the minimum film thickness of the base electrode is as thin as 3 to 8 μm. It was found that a sample infiltrating into the slag and having poor moisture resistance was produced.

また、試料番号4〜6は、寸法比A/Bが0.995であり、端面が若干凹面形状に形成されているため、耐湿性不良の発生率は低下傾向にあるものの、耐湿性不良の発生率を「0」にすることはできなかった。   Sample Nos. 4 to 6 have a dimensional ratio A / B of 0.995 and the end face is formed in a slightly concave shape, so the incidence of poor moisture resistance tends to decrease, but poor moisture resistance. The occurrence rate could not be “0”.

また、試料番号13〜15は、寸法比A/Bが0.980であり、0.985未満であるため、凹部に空気が残存し、ピンホールの形成された試料が確認された。また、試料番号14、15に示すように、寸法比A/Bが0.980と小さくなると最小膜厚も小さくなり、耐湿性の低下する試料の生じることが分かった。これは端面側に回り込むべきペーストが凹部に吸収されてしまうためと思われる。   In Sample Nos. 13 to 15, since the dimensional ratio A / B was 0.980 and less than 0.985, air remained in the recesses, and samples having pinholes were confirmed. Further, as shown in Sample Nos. 14 and 15, it was found that when the dimensional ratio A / B is reduced to 0.980, the minimum film thickness is also reduced, resulting in a sample with reduced moisture resistance. This is presumably because the paste that should go around to the end face side is absorbed by the recess.

これに対し試料番号7〜12は、寸法比A/Bが0.985〜0.990であるので、耐湿性を確保することができ、しかもピンホールも発生しないことが確認された。特に、試料番号9及び12から明らかなように、ペースト層を30μmまで薄くしても最小膜厚として10μmを確保することができ、良好な耐湿性が得られることが分かった。   On the other hand, since sample numbers 7 to 12 have a dimensional ratio A / B of 0.985 to 0.990, it was confirmed that moisture resistance could be secured and pinholes were not generated. In particular, as is clear from Sample Nos. 9 and 12, it was found that even if the paste layer was made as thin as 30 μm, a minimum film thickness of 10 μm could be ensured, and good moisture resistance could be obtained.

また、表1の結果から、最小膜厚として少なくとも10μmの膜厚を確保することにより、耐湿性低下を回避できることも分かった。   Further, from the results of Table 1, it was also found that a decrease in moisture resistance can be avoided by ensuring a minimum film thickness of 10 μm.

本発明に係る積層セラミック電子部品としての積層セラミックコンデンサの一実施の形態を示す斜視図である。1 is a perspective view showing an embodiment of a multilayer ceramic capacitor as a multilayer ceramic electronic component according to the present invention. 図1のX−X断面図である。It is XX sectional drawing of FIG. 本発明のセラミック素体を導電性ペースト層に浸漬させた状態を示す図である。It is a figure which shows the state which the ceramic body of this invention was immersed in the electrically conductive paste layer. 本発明における導電膜形成の経時的変化を示す図である。It is a figure which shows the time-dependent change of electrically conductive film formation in this invention. 端面が平坦状のセラミック素体を導電性ペースト層に浸漬させた状態を示す図である。It is a figure which shows the state which immersed the ceramic body with a flat end surface in the electrically conductive paste layer. 図5における導電膜形成の経時的変化を示す図である。It is a figure which shows the time-dependent change of electrically conductive film formation in FIG.

符号の説明Explanation of symbols

1 セラミック素体
1a、1b 端面
3 内部電極
8 ペースト層
4a、4b 下地電極
5a、5b Ni皮膜
6a、6b Sn皮膜
DESCRIPTION OF SYMBOLS 1 Ceramic body 1a, 1b End surface 3 Internal electrode 8 Paste layer 4a, 4b Base electrode 5a, 5b Ni film | membrane 6a, 6b Sn film | membrane

Claims (2)

一端が表面に露出した内部電極を内蔵したセラミック素体の両端面を導電性ペーストに浸漬して導電膜を形成し、次いで、該導電膜に焼付け処理を施して前記セラミック素体の両端面に下地電極を形成し、その後、前記下地電極をめっき皮膜で被覆して外部電極を形成する積層セラミック電子部品の製造方法において、
前記内部電極の一端が表面露出している側のセラミック素体の端面間の最小寸法Aと最大寸法Bとの寸法比A/Bが0.985〜0.990となるように、前記セラミック素体の両端面を凹面形状に形成することを特徴とする積層セラミック電子部品の製造方法。
A conductive film is formed by immersing both end faces of a ceramic body containing an internal electrode with one end exposed on the surface in a conductive paste, and then the conductive film is baked to form both ends of the ceramic body. In the method for manufacturing a multilayer ceramic electronic component, in which a base electrode is formed and then the base electrode is coated with a plating film to form an external electrode.
The ceramic element is arranged such that a dimensional ratio A / B between the minimum dimension A and the maximum dimension B between the end faces of the ceramic element body on the side where one end of the internal electrode is exposed is 0.985 to 0.990. A method for manufacturing a multilayer ceramic electronic component, wherein both end surfaces of a body are formed in a concave shape.
一端が表面に露出した内部電極を内蔵したセラミック素体と、該セラミック素体の両端面に形成され前記内部電極と電気的に接続された下地電極と、該下地電極の表面にめっき形成された外部電極とを備えた積層セラミック電子部品において、
前記内部電極の一端が表面露出している側のセラミック素体の端面間の最小寸法Aと最大寸法Bとの寸法比A/Bが0.985〜0.990となるように、前記セラミック素体の両端面が、凹面形状に形成されていることを特徴とする積層セラミック電子部品。
A ceramic body having an internal electrode with one end exposed on the surface, a base electrode formed on both end faces of the ceramic body and electrically connected to the internal electrode, and a plating formed on the surface of the base electrode In multilayer ceramic electronic components with external electrodes,
The ceramic element is arranged such that a dimensional ratio A / B between the minimum dimension A and the maximum dimension B between the end faces of the ceramic element body on the side where one end of the internal electrode is exposed is 0.985 to 0.990. A multilayer ceramic electronic component characterized in that both end surfaces of the body are formed in a concave shape .
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JP5267583B2 (en) * 2011-01-21 2013-08-21 株式会社村田製作所 Multilayer ceramic electronic components
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JPS61144628U (en) * 1985-02-27 1986-09-06
JPH09260192A (en) * 1996-03-25 1997-10-03 Taiyo Yuden Co Ltd Multilayer capacitor
JPH10199746A (en) * 1997-01-10 1998-07-31 Murata Mfg Co Ltd Mutilayer ceramic electronic component and its manufacture
JP2000049032A (en) * 1998-07-27 2000-02-18 Murata Mfg Co Ltd Laminated ceramic electronic component and manufacture thereof
JP2005050894A (en) * 2003-07-30 2005-02-24 Murata Mfg Co Ltd Method for manufacturing layered ceramic electronic component

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Publication number Priority date Publication date Assignee Title
JPS61144628U (en) * 1985-02-27 1986-09-06
JPH09260192A (en) * 1996-03-25 1997-10-03 Taiyo Yuden Co Ltd Multilayer capacitor
JPH10199746A (en) * 1997-01-10 1998-07-31 Murata Mfg Co Ltd Mutilayer ceramic electronic component and its manufacture
JP2000049032A (en) * 1998-07-27 2000-02-18 Murata Mfg Co Ltd Laminated ceramic electronic component and manufacture thereof
JP2005050894A (en) * 2003-07-30 2005-02-24 Murata Mfg Co Ltd Method for manufacturing layered ceramic electronic component

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