JP4507961B2 - Driver circuit and solid-state imaging device - Google Patents

Description

  The present invention relates to a driver circuit and a solid-state imaging device. More specifically, the present invention relates to a driver circuit that applies a driving signal to a solid-state imaging device such as a CCD chip and a solid-state imaging device having such a driver circuit.

  As a solid-state imaging device, a charge transfer type imaging device typified by a CCD (Charge Coupled Device) type imaging device and an XY address type imaging device typified by a MOS type imaging device are known (for example, see Patent Document 1). .) Hereinafter, a CCD solid-state imaging device which is one of conventional charge transfer type imaging devices will be described.

  The overall configuration of a typical CCD solid-state imaging device will be described with reference to FIG. The CCD solid-state imaging device includes an optical lens system 101, a CCD solid-state imaging element 102 that performs photoelectric conversion of light incident through the optical lens system, and an image signal processing circuit 103 that processes image signals output from the CCD solid-state imaging element. A driving circuit 104 that applies a driving signal to the CCD solid-state imaging device and the image signal processing circuit, and a display unit 105 that displays an image based on an output signal from the image signal processing circuit.

  Here, the image signal processing circuit includes a noise removing unit 103a, an amplification (AMP) and analog-digital conversion (ADC) unit 103b, a digital signal processor (DSP), and a digital-analog conversion (DAC) unit 103c. The image signal input to the image signal processing circuit is sent in the order of noise removal means, amplification and analog-digital conversion means, digital processor and digital-analog conversion means.

  The drive circuit includes a timing generator 104a and a driver circuit 104b. The timing generator includes a driver circuit, a CCD solid-state imaging device, noise removing means, amplification and analog-digital conversion means, a digital signal processor, and digital-analog conversion means. The driver circuit is configured to generate a drive signal based on the reference clock applied from the timing generator and apply the drive signal to the CCD solid-state imaging device.

  FIG. 6A is a schematic diagram for explaining a CCD solid-state imaging device. In the CCD solid-state imaging device shown here, a plurality of light receiving portions 106 are arranged in a matrix and provided for each vertical column of the light receiving portions. An imaging unit 108 having a vertical transfer unit 107 that transfers charges from each of the light receiving units, a horizontal transfer unit 109 that transfers charges from the vertical transfer unit and transfers the transferred charges in the horizontal direction, and a horizontal transfer unit The output unit 110 outputs the transferred charge as a voltage.

  In the CCD solid-state imaging device configured as described above, the drive signal V1 is applied from the driver circuit to the vertical transfer unit, for example, at the clock timing indicated by the symbol a in FIG. 6B (where V1 is a drive pulse for vertical transfer). And a pulse for reading out the electric charge accumulated in the light receiving unit to the vertical transfer unit) and, for example, by applying a drive signal V2 at a clock timing indicated by a symbol b in FIG. The charges are read out to the vertical transfer unit and transferred in the vertical direction. The charges transferred from the vertical transfer unit to the horizontal transfer unit are transferred in the horizontal direction by a clock applied from the timing generator to the horizontal transfer unit, and output from the output unit as indicated by a symbol c in FIG. 6B. A waveform can be obtained.

  By the way, as an example of the conventional driver circuit as described above, as shown in FIG. There is something to be done. The output buffer circuit includes a first MOS transistor 115, a second MOS transistor 116, and a third MOS transistor 117.

Here, the first MOS transistor is connected to the voltage unit 119a having a voltage of 15V and the output terminal OUT of the output buffer circuit, and the gate terminal has the first high voltage unit 118a having a voltage of 15V and the ground potential. It is connected to the selector circuit via the first inverting amplifier circuit 120a connected to (0V).
The second MOS transistor is connected to the ground potential (0V potential) and the output terminal OUT of the output buffer circuit, and the gate terminal is connected to the second high voltage portion 118b having a voltage of 15V and the ground potential (0V). ) Is connected to the selector circuit via the second inverting amplifier circuit 120b.
Further, the third MOS transistor is connected to the voltage unit 119b having a voltage of -7V and the output terminal OUT of the output buffer circuit, and the gate terminal is connected to the third high voltage unit 118c having a voltage of 15V and the ground potential. It is connected to the selector circuit via a third inverting amplifier circuit 120c connected to (0V).

  An input signal IN (IN1, IN2) that takes a binary value of 0V as a low level (hereinafter referred to as L level) and 3V as a high level (hereinafter referred to as H level) is input to the input buffer circuit. And the level shift circuit converts the signal to a binary value of −7V as the L level and 15V as the H level, and then the selector circuit selects one of the first MOS transistor, the second MOS transistor, and the third MOS transistor. 1 is selected and a signal is output according to the selected MOS transistor, and a signal having three values of -7 V as the L level, 0 V as the middle level, and 15 V as the H level is output from the output terminal. The Rukoto.

JP 2001-77684 A

  By the way, in a driver circuit that drives a solid-state image sensor, an output buffer circuit with high driving capability is required when the load of the solid-state image sensor to be driven is large. The area tends to increase.

  In recent years, the load on the solid-state imaging device has increased due to the higher definition (multiple pixels) of the solid-state imaging device driven by the driver circuit, the higher speed of driving, etc., and the area of the output buffer circuit is the area of the driver circuit. (See FIG. 8A). The increase in the area of the output buffer circuit also increases the area of the entire driver circuit, which is an adverse effect on an increase in manufacturing cost and downsizing of the solid-state imaging device.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a driver circuit capable of reducing the occupied area and a solid-state imaging device having such a driver circuit.

  In order to achieve the above object, a driver circuit according to the present invention includes a drive MOS transistor that controls a final output, and in the driver circuit that drives an output line based on an input signal, An amplifying circuit is connected to the gate terminal, and the amplifying circuit is configured by connecting a first MOS transistor and a first diode in series, and one end is connected to the first high voltage unit and the other end is A first circuit connected to the gate terminal of the driving MOS transistor, a second MOS transistor having a polarity different from that of the first MOS transistor, and a second diode are connected in series, and one end is And a second circuit connected to the gate terminal of the driving MOS transistor. Delay inversion means for inverting the polarity of the input signal and delaying the input signal by a predetermined amount, and the input signal to the amplifier circuit is the gate terminal of the first MOS transistor, the second MOS transistor The delay inversion means is connected to the gate terminal of the drive MOS transistor through at least one capacitor having a predetermined capacity.

  In order to achieve the above object, a solid-state imaging device according to the present invention includes a solid-state imaging device and a driver circuit that applies a driving signal to the solid-state imaging device. A drive MOS transistor for controlling the final output of the driver circuit is provided, an amplifier circuit is connected to the gate terminal of the drive MOS transistor, and the amplifier circuit has a first MOS transistor and a first diode connected in series. A first circuit in which one end is connected to the first high voltage section and the other end is connected to the gate terminal of the drive MOS transistor, and has a polarity different from that of the first MOS transistor. When the second MOS transistor and the second diode are connected in series, and one end is connected to the first low voltage section, it is shared. A second circuit having the other end connected to the gate terminal of the drive MOS transistor, and a delay inversion means for inverting the polarity of the input signal and delaying the input signal by a predetermined amount. Are input to the gate terminal of the first MOS transistor, the gate terminal of the second MOS transistor, and the delay inverting means, and the delay inverting means has at least one capacitor having a predetermined capacity. The capacitor is connected to the gate terminal of the drive MOS transistor via a capacitor.

  Here, the voltage value applied to the gate terminal of the drive MOS transistor can be increased by the amplifier circuit connected to the gate terminal of the drive MOS transistor, and the area of the drive MOS transistor can be reduced. Hereinafter, this point will be described in detail.

That is, FIG. 8B shows the relationship between the area on the plane of the driving MOS and the gate voltage. The relationship shown below is a general matter in MOS. The width of the MOS transistor indicated by the symbol W is related to the current flowing through the drive MOS transistor. When the voltage value applied to the gate terminal of the MOS transistor is considered to be constant, a large current is generated when the MOS transistor is wide. If the width of the MOS transistor is narrow, only a small current can flow. In addition, when the voltage applied to the gate voltage of the MOS transistor is increased, the saturation current between the source and drain is
Isd = a · (Vg-Vp ) 2/2 a = ε · ε 0 · μ · b / Ld
Isd: Saturation current between source and drain Vg: Gate voltage Vp: Pinch-off voltage ε, ε ₀ : Dielectric constant μ: Mobility b: Channel width L: Channel length d: Insulator thickness (From page 168 (7.109) in "20 printing Asakura Shoten")
As the gate voltage increases, the saturation current increases in a quadratic function.
That is, assuming that a constant current flows through the MOS transistor, the width of the MOS transistor can be reduced by increasing the gate voltage of the MOS transistor.
In addition, the distance between the source and the drain indicated by the symbol L in FIG. 8B, that is, the channel length of the MOS transistor is related to the dielectric strength of the voltage between the source and the drain. Does not matter.
For these reasons, by increasing the gate voltage of the drive MOS transistor, the width of the drive MOS transistor can be reduced, and as described above, the area of the drive MOS transistor can be reduced.

  In the driver circuit to which the present invention is applied, the circuit area can be reduced. Further, in the solid-state imaging device to which the present invention is applied, the area of the driver circuit can be reduced, so that the solid-state imaging device can be reduced in size.

Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
FIG. 1 is a schematic configuration diagram for explaining an example of a driver circuit to which the present invention is applied. A driver circuit 1 shown here includes an input buffer circuit 2, a selector circuit 3, and an amplifier circuit connected in order from an input terminal IN. 4 and the output buffer circuit 5, the amplifier circuit 4 has a first amplifier circuit 4a, a second amplifier circuit 4b, and a third amplifier circuit 4c, and the output buffer circuit 5 is for the first drive. It has a MOS transistor 5a, a second drive MOS transistor 5b, and a third drive MOS transistor 5c.

Here, the first amplifier circuit 4a is configured by connecting a first p-type MOS transistor 6a and a first diode 7a in series, and one end is connected to the first high voltage unit 8a having a voltage of 15V. The first circuit 9a having the other end connected to the first connection point A, the first n-type MOS transistor 10a, and the second diode 11a are connected in series, and one end is −7V. And a second circuit 13a having the other end connected to the first connection point. Further, the first amplifier circuit is connected to the first delay circuit 14a, the first level shift circuit 15a, the second high voltage portion 16a having a voltage of 15V, and the ground potential (0V). Are connected to a first delay circuit, a first level shift circuit, and a first inverting amplifier circuit in order from the input terminal of the first amplifier circuit. The first capacitor 19a is connected to the first connection point. The first connection point is connected to the gate terminal of the first drive MOS transistor 5a.
The first amplifier circuit has a second level shift circuit 20a connected to the input terminal of the first amplifier circuit, and the second level shift circuit is the gate of the first p-type MOS transistor. The terminal and the gate terminal of the first n-type MOS transistor are connected.
When the gate voltage of the first drive MOS transistor 5a is applied by this circuit, the output of the seventh high voltage section is output from the final output OUT.

The second amplifier circuit 4b is configured by connecting a second p-type MOS transistor 6b and a third diode 7b in series, and one end of which is connected to a third high voltage unit 8b having a voltage of 15V. And the other end of the third circuit 9b connected to the second connection point B, the second n-type MOS transistor 10b and the fourth diode 11b are connected in series, and one end is -7V. A fourth circuit 13b is connected to the second low voltage portion 12b having a voltage and the other end is connected to the second connection point. Further, the second amplifier circuit is connected to the second delay circuit 14b, the third level shift circuit 15b, the fourth high voltage portion 16b having a voltage of 15V, and the second potential connected to the ground potential (0V). Is connected to a second delay circuit, a second level shift circuit, and a second inverting amplifier circuit in order from the input terminal of the second amplifier circuit, and the second inverting amplifier circuit is It is connected to the second connection point through the second capacitor 19b. The second connection point is connected to the gate terminal of the second drive MOS transistor 5b.
The second amplifier circuit has a fourth level shift circuit 20b connected to the input terminal of the second amplifier circuit, and the fourth level shift circuit is a gate of the second p-type MOS transistor. The terminal and the gate terminal of the second n-type MOS transistor are connected.
When the gate voltage of the third driving MOS transistor 5b is applied by this circuit, the output of the third low voltage section is output from the final output OUT.

The third amplifying circuit 4c is configured by connecting a third p-type MOS transistor 6c and a fifth diode 7c in series, and one end of which is connected to a fifth high voltage unit 8c having a voltage of 15V. The fifth circuit 9c having the other end connected to the third connection point C, the third n-type MOS transistor 10c, and the sixth diode 11c are connected in series, and one end is connected to the ground potential ( 0V) and a sixth circuit 13c having the other end connected to the third connection point. Further, the third amplifier circuit is connected to the third delay circuit 14c, the fifth level shift circuit 15c, the sixth high voltage unit 16c having a voltage of 15V, and the third potential connected to the ground potential (0V). Is connected to a third delay circuit, a fifth level shift circuit, and a third inverting amplifier circuit in order from the input terminal of the third amplifier circuit. It is connected to the third connection point via the third capacitor 19c. The third connection point is connected to the gate terminal of the third drive MOS transistor 5c.
The third amplifier circuit has a sixth level shift circuit 20c connected to the input terminal of the third amplifier circuit, and the sixth level shift circuit is the gate of the third p-type MOS transistor. The terminal and the gate terminal of the third n-type MOS transistor are connected.
When the gate voltage of the first drive MOS transistor 5c is applied by this circuit, the final output OUT becomes the GND potential.

The first drive MOS transistor 5a is connected to the seventh high voltage unit 21a having a voltage of 15V and the output terminal OUT of the output buffer circuit, and the gate terminal is connected to the first connection point. Yes.
Further, the second drive MOS transistor 5b is connected to the third low voltage part 21b having a voltage of -7V and the output terminal OUT of the output buffer circuit, and the gate terminal is connected to the second connection point. ing.
The third drive MOS transistor 5c is connected to the ground potential and the output terminal OUT of the output buffer circuit, and the gate terminal is connected to the third connection point.

  In the following, the amplification circuit configured as described above increases the voltage value applied to the gate terminal of the drive MOS transistor. FIG. 2A is a schematic configuration diagram of the amplification circuit described above and the amplification circuit. 2B, which is a timing chart of the input signal, the inverted delay signal of the input signal, and the output signal from the amplifier circuit.

Here, the circuit (1) 32 configured by connecting the p-type MOS transistor 30 and the diode (1) 31 in series includes a high voltage section (1) 33 having a voltage of VH and the gate terminal of the drive MOS transistor 50. The circuit (2) 36, which is configured by connecting the n-type MOS transistor 34 and the diode (2) 35 in series to each other, has a low voltage section (1) 37 having a voltage of VL and the gate terminal of the drive MOS transistor It is connected to the. The inverting amplifier circuit 38 is connected to a high voltage part (2) 39 having a voltage of VH and a low voltage part (2) 40 having a voltage of VL, and is connected to the gate terminal of the drive MOS transistor via a capacitor 41. Has been.
When an input signal having a clock timing indicated by the symbol IN in FIG. 2B is input to the amplifier circuit, the capacitor takes two values, VH and VL, through the delay circuit 42, the level shift circuit, and the inverting amplifier circuit. A signal having a clock timing indicated by a symbol Cin in FIG. 2B is input.

  When an H level input signal is input to the amplifier circuit at time t1, the p-type MOS transistor is turned off and the n-type MOS transistor is turned on, and the n-type MOS transistor is connected to the gate terminal of the drive MOS transistor. The voltage of the low voltage part (1) to which the MOS transistor is connected is applied, and the voltage value applied to the gate terminal of the drive MOS transistor is VL.

  Next, when the input signal becomes L level at time t2, the p-type MOS transistor is turned on and the n-type MOS transistor is turned off, and the p-type MOS transistor is connected to the gate terminal of the drive MOS transistor. The voltage of the high voltage portion (1) is applied, and the voltage value applied to the gate terminal of the drive MOS transistor is VH.

Subsequently, when the voltage value applied to the capacitor becomes VH while the input signal is at the L level at time t3, the voltage applied to the capacitor is superimposed on the voltage applied to the gate terminal of the drive MOS transistor. It will be. That is, the voltage applied to the capacitor is superimposed on the voltage of the high voltage section (1) to which the p-type MOS transistor is connected, and the voltage value applied to the gate terminal of the drive MOS transistor is 2VH.
Here, the voltage of the high voltage portion (2) is VH, but it is sufficient if it is greater than 0V. For example, if it is 1/2 · VH, the voltage value applied to the gate terminal of the drive MOS transistor is 1.5 VH. Further, by adjusting the voltage of the high voltage portion (1) and the voltage of the high voltage portion (2) independently by this adjustment, not only the waveform voltage superimposed and synthesized, but also the waveform rounding can be adjusted.

  Next, when the input signal becomes H level at time t4, the p-type MOS transistor is turned off, the n-type MOS transistor is turned on, and the voltage value of the low voltage portion (1) to which the n-type MOS transistor is connected. The voltage applied to the capacitor is superimposed on the capacitor, and the voltage value applied to the gate terminal of the driving MOS transistor is (VH + VL).

Next, when the input signal is at the H level at time t5 and the voltage value applied to the capacitor becomes VL, the voltage applied to the capacitor is superimposed on the voltage applied to the gate terminal of the drive MOS transistor. It will be. That is, the voltage applied to the capacitor is superimposed on the voltage of the low voltage portion (1) to which the n-type MOS transistor is connected, and the voltage value applied to the gate terminal of the drive MOS transistor is 2 VL.
In this case as well, by adjusting the low voltage portion (1) and the low voltage portion (2) independently, the absolute value of the superimposed voltage and the waveform rounding can be adjusted.

  Thereafter, the same voltage value change from time t2 to time t5 is repeated, and the voltage shown in the timing chart indicated by the reference symbol Vg in FIG. 2B is applied to the gate terminal of the drive MOS transistor.

  As described above, by using the amplifier circuit, the voltage value applied to the gate terminal of the drive MOS transistor increases, and the maximum value of the voltage applied to the gate terminal of the drive MOS transistor is the p-type MOS transistor. Is the sum of the voltage value of the high voltage part (1) connected to the voltage value of the high voltage part (2) connected to the inverting amplifier circuit, and is the minimum value of the voltage applied to the gate terminal of the drive MOS transistor Is the sum of the voltage value of the low voltage part (1) connected to the n-type MOS transistor and the voltage value of the low voltage part (2) connected to the inverting amplifier circuit.

  Specifically, by using the first amplifier circuit, the voltage value applied to the gate terminal of the first drive MOS transistor increases, and the voltage applied to the gate terminal of the first drive MOS transistor. Is the voltage value of the first high voltage portion connected to the first p-type MOS transistor, 15V, and the voltage value of the second high voltage portion connected to the first inverting amplifier circuit. The minimum value of the voltage applied to the gate terminal of the first drive MOS transistor is 30V, which is the sum of 15V, and is the voltage value of the first low-voltage portion connected to the first n-type MOS transistor. It becomes -7V which is the sum of -7V and 0V which is the voltage value of the ground potential connected to the first inverting amplifier circuit.

  Further, by using the second amplifier circuit, the voltage value applied to the gate terminal of the second drive MOS transistor increases, and the maximum value of the voltage applied to the gate terminal of the second drive MOS transistor. Is the sum of 15V, which is the voltage value of the third high voltage portion connected to the second p-type MOS transistor, and 15V, which is the voltage value of the fourth high voltage portion connected to the second inverting amplifier circuit. 30V, and the minimum value of the voltage applied to the gate terminal of the second drive MOS transistor is -7V, which is the voltage value of the second low voltage portion connected to the second n-type MOS transistor. It becomes −7V which is the sum of 0V which is the voltage value of the ground potential connected to the second inverting amplifier circuit.

  Further, by using the third amplifier circuit, the voltage value applied to the gate terminal of the third drive MOS transistor increases, and the maximum value of the voltage applied to the gate terminal of the third drive MOS transistor. Is the sum of 15V, which is the voltage value of the fifth high voltage portion connected to the third p-type MOS transistor, and 15V, which is the voltage value of the sixth high voltage portion connected to the third inverting amplifier circuit. The minimum value of the voltage applied to the gate terminal of the third driving MOS transistor is 0 V, which is the voltage value of the ground potential connected to the third n-type MOS transistor, and the third inversion amplification. It becomes 0V which is the sum of 0V which is the voltage value of the ground potential connected to the circuit.

As described above, the driving MOS transistors (first driving MOS transistor, second driving MOS transistor, and second driving MOS transistor) are amplified by the amplification circuits (first amplification circuit, second amplification circuit, and third amplification circuit). Although the voltage applied to the gate terminal of the third driving MOS transistor) can be increased and the area of the driving MOS transistor can be reduced, the area of the driving MOS transistor can be reduced. When this amplifier circuit needs to be formed and the area of the entire driver circuit including the drive MOS transistor and the amplifier circuit is taken into consideration, (1) the area occupied by the reduced drive MOS transistor and (2 ) The increase / decrease of the area of the entire driver circuit is determined by comparison with the area of the newly formed amplifier circuit. .
Here, since the drive MOS transistor is supplied with the power supply voltage, the drive MOS transistor, which is usually a high breakdown voltage specification, that is, the distance between the source and the drain, is formed long and a relatively wide (transistor) circuit. Requires area. For this reason, when the increase / decrease in the area occupied by the entire driver circuit is considered, the increase / decrease in the area of the drive MOS transistor is dominant.
Therefore, even if the amplifier circuit is formed, if the voltage applied to the gate terminal of the drive MOS transistor becomes a high voltage and, as a result, the area of the drive MOS transistor decreases, the circuit area of the entire driver circuit can be reduced. it can.

Further, considering the capacitor capacity in the amplifier circuit, when the capacitor capacity in the amplifier circuit is large, the area of the capacitor increases, the area of the amplifier circuit increases, and as a result, the area of the driver circuit increases. On the other hand, the capacitor in the amplifier circuit and the capacitor capacitance parasitic on the gate of the drive MOS transistor are connected in series. Here, when voltages at both ends of the two capacitors are applied, the voltages applied to the respective capacitors have values that are inversely proportional to the respective capacities. That is, the charge amount Q accumulated in the capacitor and the capacitor capacitance C and the voltage applied to the capacitor have a relationship of Q = C · V, and the charge amount accumulated in each capacitor is the same amount. In addition, the smaller the capacitor capacity, the higher the voltage applied to the capacitor.
That is, when the capacitor capacity in the amplifier circuit is small, the voltage value applied to the gate terminal of the drive MOS transistor is small, and the amount of reduction in the area of the drive MOS transistor is reduced.
Therefore, it is necessary to optimize the capacitor capacity in the amplifier circuit. When the relationship between the capacitor capacity in the amplifier circuit and the area of the driver circuit is examined, a capacitor parasitic on the gate of the drive MOS transistor is shown in FIG. From the relationship between (capacitance) and (conventional ratio of drive MOS transistor area (due to the formation of the amplifier circuit)), if the capacitor capacity in the amplifier circuit is 2.5 pF under these conditions, the area of the driver circuit is Minimal.

  In the driver circuit to which the present invention described above is applied, the voltage applied to the gate terminal of the first drive MOS transistor is increased by the first amplifier circuit to reduce the area of the first drive MOS transistor. The amplifier circuit increases the voltage applied to the gate terminal of the second drive MOS transistor to reduce the area of the second drive MOS transistor, and the third amplifier circuit reduces the area of the third drive MOS transistor. The voltage applied to the terminal is increased to reduce the area of the third drive MOS transistor, and as a result, the area of the driver circuit is reduced by 19% compared to the area of the conventional driver circuit as shown in FIG. The manufacturing cost can be reduced.

It is a schematic block diagram for demonstrating an example of the driver circuit to which this invention is applied. It is a schematic block diagram of an amplifier circuit and a timing chart of each pulse. It is a graph which shows the conventional ratio of the capacitor | condenser capacity | capacitance parasitic on the gate of a drive MOS transistor, and the area of a drive MOS transistor. It is a graph which shows the area structure and transition of the conventional driver circuit and the driver circuit of this invention. It is a figure for demonstrating the mechanism of the whole CCD solid-state imaging device. 4 is a timing chart of a configuration of a CCD solid-state image sensor and pulses applied to the CCD solid-state image sensor. It is a figure for demonstrating the conventional driver circuit. It is a top view for demonstrating the area structure ratio of an output buffer circuit, and a MOS transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Driver circuit 2 Input buffer circuit 3 Selector circuit 4a 1st amplifier circuit 4b 2nd amplifier circuit 4c 3rd amplifier circuit 5a 1st drive MOS transistor 5b 2nd drive MOS transistor 5c 3rd drive use MOS transistor 6a 1st p-type MOS transistor 6b 2nd p-type MOS transistor 6c 3rd p-type MOS transistor 7a 1st diode 7b 3rd diode 7c 3rd diode 8a 1st high voltage part 8b 1st 3 high voltage portion 8c fifth high voltage portion 9a first circuit 9b third circuit 9c fifth circuit 10a first n-type MOS transistor 10b second n-type MOS transistor 10c third n-type MOS Transistor 11a Second diode 11b Fourth diode 11c Sixth diode 12a 1st low voltage part 12b 2nd low voltage part 13a 2nd circuit 13b 4th circuit 13c 6th circuit 14a 1st delay circuit 14b 2nd delay circuit 14c 3rd delay circuit 15a 3rd 1 level shift circuit 15b second level shift circuit 15c third level shift circuit 16a second high voltage unit 16b fourth high voltage unit 16c sixth high voltage unit 18a first inverting amplifier circuit 18b second Inverting amplifier circuit 18c third inverting amplifier circuit 19a first capacitor 19b second capacitor 19c third capacitor 20a second level shift circuit 20b fourth level shift circuit 20c sixth level shift circuit 21a seventh High voltage part 21b Third low voltage part 30 p-type MOS transistor 31 Diode (1)
32 Circuit (1)
33 High voltage section (1)
34 n-type MOS transistor 35 diode (2)
36 Circuit (2)
37 Low voltage part (1)
38 Inverting Amplifier 39 High Voltage Unit (2)
40 Low voltage part (2)
41 Capacitor 50 MOS transistor for drive

Claims (4)

In a driver circuit that includes a drive MOS transistor that controls the final output and drives the output line based on an input signal,
An amplifier circuit is connected to the gate terminal of the drive MOS transistor,
The amplifying circuit includes a first MOS transistor and a first diode connected in series, one end connected to the first high voltage unit and the other end connected to the gate terminal of the drive MOS transistor. A first circuit,
A second MOS transistor having a polarity different from that of the first MOS transistor and a second diode are connected in series, and one end is connected to the first low voltage portion and the other end is connected to the drive MOS. A second circuit connected to the gate terminal of the transistor;
A delay inversion means for inverting the polarity of the input signal and delaying the input signal by a predetermined amount;
An input signal to the amplifier circuit is configured to be input to the gate terminal of the first MOS transistor, the gate terminal of the second MOS transistor, and the delay inverting means,
The driver circuit, wherein the delay inverting means is connected to the gate terminal of the drive MOS transistor via at least one capacitor having a predetermined capacity. The delay inversion means is connected to the second high voltage unit and the second low voltage unit, and the voltage value applied from the second high voltage unit and the voltage value applied from the second low voltage unit are input signals. The driver circuit according to claim 1, wherein the driver circuit converts the signal into a signal having two values. The first high voltage part, the first low voltage part, the second high voltage part, and the second low voltage part can be adjusted independently of each other. Driver circuit described in 1. A solid-state image sensor;
In a solid-state imaging device having a driver circuit that applies a driving signal to the solid-state imaging device,
The driver circuit includes a drive MOS transistor that controls a final output of the driver circuit,
An amplifier circuit is connected to the gate terminal of the drive MOS transistor,
The amplifying circuit includes a first MOS transistor and a first diode connected in series, one end connected to the first high voltage unit and the other end connected to the gate terminal of the drive MOS transistor. A first circuit,
A second MOS transistor having a polarity different from that of the first MOS transistor and a second diode are connected in series, and one end is connected to the first low voltage portion and the other end is connected to the drive MOS. A second circuit connected to the gate terminal of the transistor;
Delay inversion means for inverting the polarity of the input signal and delaying the input signal by a predetermined amount;
An input signal to the amplifier circuit is configured to be input to the gate terminal of the first MOS transistor, the gate terminal of the second MOS transistor, and the delay inverting means,
The solid-state imaging device, wherein the delay inversion means is connected to the gate terminal of the drive MOS transistor via at least one capacitor having a predetermined capacity.

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