JP4696788B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to a solid-state imaging device, and at least two power supply units are arranged around a pixel unit, thereby increasing the drive capability of a control circuit and uniformly applying a signal to each pixel of the pixel unit. it is to about the solid-state imaging device which is adapted.

  In general, as a semiconductor element for imaging, a solid-state imaging device combining a photodiode and a MOSFET is known (Patent Document 1). This solid-state imaging device includes an amplification type solid-state imaging device having an amplifier in a pixel such as a CMOS image sensor. Such a solid-state imaging device has a signal processing circuit such as a circuit for driving a pixel and a noise suppression circuit around a pixel covering region (pixel portion). When driving the pixels, it is possible to drive in units of rows or all pixels at once.

  FIG. 14 shows an example of such a solid-state imaging device, which is disclosed in Patent Document 1 described above. The pixels Px are regularly arranged in the pixel covering region (pixel portion) 100. On the left side of the figure, there is a circuit group for driving the pixel Px, which includes, for example, a vertical scanning circuit 102, an electronic shutter scanning circuit 104, and a multiplexer 106. These circuits can switch between driving the pixels Px in units of rows or all pixels at once. In the upper part of the pixel covering area 100 in the figure, there is a current source 108 serving as a load of the pixel amplifier output, and a voltage generated in the current source 108 becomes a signal of each pixel Px. The signal output of each pixel Px is subjected to signal processing by the noise suppression circuit 110, the switch 114 is scanned by the horizontal scanning circuit 112, and sequentially output from the output terminal 116.

Japanese Patent Laying-Open No. 2005-64550 (FIG. 10)

  Incidentally, in recent years, the solid-state imaging device has been highly miniaturized, and the number of pixels to be spread has increased. For example, there are solid-state imaging devices with 10 million pixels or more, and the number tends to increase. As the number of pixels increases, the number of pixels that the driving circuit must drive in units of rows or all pixels at the same time also increases. As a result, there is a problem that a pixel far from the driving circuit causes a delay or signal rounding, which affects the image quality. As a result of the increase in the number of pixels, the operation clock frequency is increased to increase the reading speed, and the time allocated for pixel driving tends to be shortened. This tendency also tends to cause delay and signal rounding problems when driving a pixel far from the drive circuit. Such a problem becomes prominent particularly when all the pixels are driven simultaneously.

The present invention has been devised to pay attention to the above problems and to effectively solve them. An object of the present invention, among the power supply unit and the control circuit, Hisage at least the power part by spaced apart from each other so as to provide two or more, with a solid capable of homogenizing the predetermined potential supplied to the pixel imaging device There is to serve.

The invention according to claim 1 includes a photodiode for storing charges generated by photoelectric conversion of incident light, a transfer gate electrode, a transfer gate transistor for transferring charges accumulated in the photodiode, and a ring. have Jo gate electrode, a pixel including a ring-shaped gate transistor for accumulating the charge transferred from said transfer transistor, and a pixel portion having a plurality arranged in a matrix in row and column directions, the in the pixel portion row A first power supply unit that is arranged around one side in the direction and supplies a plurality of first potentials different from each other; and the first power source unit around the one side in the column direction in the pixel unit A second power supply unit that is disposed apart from the power supply unit and supplies a first plurality of different potentials, and is supplied from the first power supply unit and the second power supply unit, respectively. And a ring-shaped gate potential controller that selects a predetermined potential from the first plurality of different potentials and supplies the selected potential to the ring-shaped gate electrode. .

In this case, for example, as defined in claim 2, a third power supply unit that is arranged around the pixel unit and supplies a second plurality of different potentials, and the third power source unit around the pixel unit. The fourth power supply unit that is disposed apart from the power supply unit and supplies the second plurality of different potentials, and the different ones supplied from the third power supply unit and the fourth power supply unit, respectively. A transfer gate potential control unit that selects a predetermined potential from the second plurality of potentials and supplies the selected potential to the transfer gate electrode ;

In the related art of the present invention , a plurality of pixels each including a photodiode and a transistor are arranged in a matrix, and each pixel portion is arranged around the pixel portion and supplies a plurality of predetermined potentials. A plurality of power supply units; at least one control circuit that selectively supplies the pixels by switching the plurality of predetermined potentials respectively supplied from the plurality of power supply units; and a row selection unit that selects a row of the pixel units. When a driving method of a solid-state imaging device having a column selection means for selecting a column of said pixel portion, wherein a plurality of said predetermined potential from the power source unit to the pixel of the pixel portion, respectively it supplies it is a method for driving the solid-state imaging device characterized by having a step.

According to the solid-state imaging device according to the present invention, among the power supply unit and the control circuit, at least the power part by spaced apart from each other so as to provide two or more, it is possible to equalize the predetermined potential supplied to the pixel with.
Further, if the drive capability of the control circuit is improved, the predetermined potential supplied to the pixels can be made more uniform.

Hereinafter will be described in detail with reference to Kazumi施例solid imaging device according to the present invention in the accompanying drawings.
Prior to the description of the present invention, the structure of one pixel and the technical contents disclosed in the patent application previously filed by the present applicant as the premise of the present invention will be described. 1A and 1B are diagrams illustrating a structure for one pixel, FIG. 1A is a top view, and FIG. 1B is a cross-sectional view taken along line XX ′ in FIG. FIG. 2 shows s rows and t columns (s ≦ m, t ≦ n) of a solid-state imaging device constituted by a pixel portion of m rows and n columns proposed by the present applicant in a previous application (Japanese Patent Application No. 2004-21895). An equivalent circuit of the pixel is shown. In the pixel equivalent circuit shown in FIG. 2, in the pixel portion 43, a plurality of pixels Px are regularly arranged vertically and horizontally and arranged in a matrix, and m rows × n columns of pixels Px are provided. In FIG. 2, a pixel in the s-th row and the t-th column is representatively shown as a representative.

Here, the structure of one pixel will be described with reference to FIG. Whole of the solid-state imaging device is formed on a p ⁺ substrate 71, so that all the pixels on the p ⁺ substrate 71 is formed in common by juxtaposed. Specifically, a p ⁻ type epitaxial layer 72 is grown on the p ⁺ substrate 71. An n well 73 is provided in the p ⁻ type epitaxial layer 72, and a ring-shaped gate electrode 75 is formed in a ring shape on the n well 73 as a first gate electrode with a gate oxide film 74 interposed therebetween.
An n ⁺ -type source region 76 is formed on the surface of the n-well 73 in the central opening of the ring-shaped gate electrode 75, and a p-type source vicinity region 77 is formed adjacent to the source region 76. Yes. This source vicinity region 77 does not reach the outer peripheral portion of the ring-shaped gate electrode 75.

An n ⁺ -type drain region 78 is provided on the surface of the n-well far from the source region 76 and the source vicinity region 77. A p-type region 79 is formed in the n-well at a position away from the ring-shaped gate electrode 75 and below the drain region 78, thereby forming the buried photodiode 6.
A transfer gate electrode 81 is provided as a second gate electrode between the embedded photodiode 6 and the ring-shaped gate electrode 75. The portion of the transfer gate electrode 81 is configured as the transfer MOSFET 4. The drain region 78, the ring-shaped gate electrode 75, the source region 76, and the transfer gate electrode 81 are formed with metal wirings 82, 83, 84, and 85, respectively.
A light shielding film 86 is formed on the top of each configuration, and an opening 87 is provided on the top of the photodiode 6. A ring-shaped gate MOSFET 2 is constituted by the source region 76, the drain region 78 and the ring-shaped gate electrode 75.

As described above, one pixel Px is mainly formed by the MOSFET 2 having the ring-shaped gate electrode, the transfer gate MOSFET 4 and the photodiode 6, and the drain of the gate electrode of the ring-shaped gate MOSFET 2 is connected to the n-type of the photodiode 6. The source of the transfer gate MOSFET 4 is connected to the p-type of the photodiode 6, and the drain of the transfer gate MOSFET 4 is connected to the back gate of the ring-shaped gate MOSFET 2.
There is a peripheral circuit for reading a signal from each pixel Px in s rows and t columns, and a frame start signal generating circuit 42 is provided for reading one frame. The output frame start signal is supplied to the vertical shift register 32 which is a row selection means. The vertical shift register 32 outputs a signal instructing which row of pixels to read out.

  In each pixel, the ring-shaped gate electrode of the ring-shaped gate MOSFET 2 is connected to the ring-shaped gate potential control circuit 31 via the ring-shaped gate electrode wiring 33, and the transfer gate electrode of the transfer gate MOSFET 6 is connected via the transfer gate electrode wiring 44. Are connected to the transfer gate potential control circuit 41, and the drain of the transfer gate MOSFET 4 is connected to the drain potential control circuit 8 via the drain electrode wiring 10, so that each can be controlled to have a predetermined potential. Yes.

  Signals are supplied from the vertical shift register 32 to the ring-shaped gate potential control circuit 31 and the drain potential control circuit 8, respectively. Since the ring-shaped gate electrode is controlled for each row, wiring is performed in the horizontal direction. However, since the transfer gate electrode is controlled for all pixels at the same time, wiring in the vertical direction may be used, but here the wiring is performed in the horizontal direction. . The drain potential control circuit 8 may control all the pixels at the same time or may control it for each row. Here, the drain potential control circuit 8 is wired in the horizontal direction. The ring-shaped gate potential control circuit 31 is connected to the vertical shift register 32, the transfer gate potential control circuit 41 is connected to the frame start signal generating circuit 42, and the drain potential control circuit 8 is connected to the vertical shift register 32 and the frame start signal generating circuit 42. Are connected to each.

  The source electrode wiring (output line) 12 connected to the source electrode of the ring-shaped gate MOSFET 2 is wired in the vertical direction, and one of the wirings 12 is connected to the source potential control circuit 14 via the switch sw1, and the other is connected to the switch sw2. Via the signal readout circuit 16. When the signal is read, the switch sw1 is turned off and the switch sw2 is turned on. On the other hand, when the source potential is controlled, the switch sw1 is turned on and the switch sw2 is turned off.

  The signal readout circuit 16 includes a current source 18 serving as a load, capacitors C1 and C2 connected in parallel to each other, switches sc1 and sc2 for switching these capacitors, and a differential amplifier 20 that takes a potential difference between the capacitors C1 and C2. It consists of. Specifically, the source electrode wiring 12 is connected to a current source 18 serving as a load, and the signal readout circuit 16 forms a source follower circuit. The current source 18 is connected in parallel with one end of each of the capacitors C1 and C2 via the switches sc1 and sc2. The other ends of the capacitors C1 and C2 are grounded, and one end thereof is connected to the inverting input terminal and the non-inverting input terminal of the differential amplifier 20, respectively, and the potential difference between the capacitors C1 and C2 is output as an output signal Vout through the output switch swt. It is designed to output. The output switch swt is selectively opened and closed by a horizontal shift register 22 which is a column selection unit. The source potential control circuit 14 is connected to the frame signal generation circuit 42 and the vertical shift register 32, respectively.

FIG. 3 shows a signal of each control circuit and a timing chart of the CMOS sensor equivalent circuit. Here, description will be made by paying attention to the pixel in the s row and the t column as a representative.
Period (1) is a photodiode charge accumulation period. Light enters the embedded photodiode 6, electron hole pairs are generated by the photoelectric effect, and holes are accumulated in the p ⁻ type region of the photodiode 6.
When the frame start signal is output in a pulse form, first, in period (2), the charge is transferred from the photodiode 6 to the back gate of the ring-shaped gate MOSFET 2 all at once in all the pixels. This is performed when the control signal potential of the transfer gate potential control circuit 41 falls from Vdd to Low 2 and the transfer gate MOSFET 4 is turned on. At this time, the potential of the ring-shaped gate electrode changes from Low to Low1, but Low2 is larger than Low1. Note that Low1 may be the same as Low. Most simply, Low1 = Low = 0V is set. The source potential is set to S 1 by the source potential control circuit 14. S1> Low1, so that the ring-shaped gate MOSFET 2 remains off and no current flows.

In the period (3), the potential of the transfer gate electrode becomes Vdd again, and the transfer gate MOSFET 4 is turned off. The photodiode 6 starts to accumulate hole charges again and continues until the next transfer. Since pixel signal readout is performed in order for each row, a standby state is entered in a period (3) in which the first to (s-1) th rows are read out. At this time, the gate potential of the ring-shaped gate MOSFET 2 in the s-th row and the t-th column is Low, the source potential is S1, and it is in the off state. The source potential can take various values depending on the value of the signal from the pixel while the signal is read from another row. Further, the ring-shaped gate electrode potential can take various potentials for each row. Such a region is indicated by hatching in the figure.
In the periods (4) to (6), reading from the pixel in the s row and the t column is performed.
First, in the period (4), the potential of the ring-shaped gate electrode becomes Vg1. This Vg1 has the following relationship with Low, Low1, and Vdd. Here, Vdd = High1.
Low ≤ Low1 ≤ Vg1 ≤ Vdd (where Low <Vdd)

  On the other hand, the switch sw1 is off, the switch sw2 is on, the switch sc1 is on, and the switch sc2 is off. As a result, the signal readout circuit 16 which is a source follower circuit works, and the source potential of the ring-shaped gate MOSFET 2 becomes S2 (= Vg1-Vth1). Here, Vth1 is a threshold voltage of the ring-shaped gate MOSFET 2 in a state where there is a hole in the back gate (p-type region near the source). This value is stored in the capacitor C1 through the switch sc1.

Next, in period (5), the potential of the ring-shaped gate electrode becomes High1, and the potential of the source electrode becomes Highs. Here, High1, Highs> Low1, and it is desirable to set the potential so that the ring-shaped gate MOSFET 2 is turned on and no current flows. Further, High1 and Highs ≦ Vdd are desirable. In a simple setting, High1 = Highs = Vdd. Note that when High1 and Highs> Vdd, it is desirable that each transistor for driving the pixel be a high breakdown voltage transistor.
At this time, the potential of the p-type region in the vicinity of the source is raised, and holes are discharged to the p-type epitaxial layer beyond the barrier of the n-well (reset).

  In the period (6), the potential of the ring-shaped gate electrode becomes Vg1 again. On the other hand, the switch sw1 is off, the switch sw2 is on, the switch sc1 is off, and the switch sc2 is on. As a result, the source follower circuit (signal readout circuit 16) works, and the source potential of the ring-shaped gate MOSFET 2 becomes S0 (= Vg1-Vth0). Here, Vth0 is the threshold voltage of the ring-shaped gate MOSFET 2 in the state where there is no hole in the back gate (p-type region near the source). This value is stored in the capacitor C2 through the switch sc2.

The differential amplifier 20 outputs a potential difference between the capacitors C1 and C2, that is, “Vth0−Vth1”. This output value is a change in threshold value due to hole charges. When the horizontal shift register 22 turns on the output switch swt in the t-th column, the signal of the pixel in the s-th row and the t-th column is output outside the sensor.
In the period (7), the potential of the ring-shaped gate electrode becomes Low, the ring-shaped gate MOSFET 2 is turned off, and the signal of the pixels in the s + 1 to n rows is read out.
When signals are read from all pixels, the next frame is started again.

Note that there is a method other than the supply of the source potential from the source potential control circuit 14 at the time of resetting in the period (5). In the period (5), the switches sw1 and sw2 are both set to Low, and the source electrode wiring 12 is floated. Here, when the potential of the ring-shaped gate electrode is set to High1, the ring-shaped gate MOSFET 2 is turned on, current is supplied from the drain to the source electrode, the potential of the source electrode is increased, and thus the potential of the p-type region near the source is increased. Then, the holes are discharged into the p-type epitaxial layer beyond the n-well barrier (reset). The potential of the source electrode when the holes are completely discharged becomes “High1-Vth0”. This method can reduce the number of transistors that supply Highs in the source potential control circuit 14, and can reduce the chip area.
Next, the layout of the control circuit and the pixel portion which are controlled in a row or simultaneously as described in the timing chart of FIG. 3 will be described.

  FIG. 4 shows a layout of the s-th ring-shaped gate potential control circuit on the solid-state imaging device. The ring-shaped gate control circuit 31 in the sth row is connected to the vertical shift register 32. In addition, by connecting to the ring-shaped gate electrode wiring 33, n pixels from the pixel Px35 in the first row of the s row to the pixel Px36 in the nth column in the same row of the pixel portion 34 configured by m rows and n columns. Is supplying the signal. A power supply unit 38 is provided in the periphery of the pixel unit 43, and four power supply units 38 are provided to supply four different predetermined potentials, that is, Low, Low1, Vg1, and Vdd. Includes power supply. A voltage is supplied from the power supply unit 38 to the ring-shaped gate potential control circuit 31 through a power supply wiring group 37 collectively showing wirings of each power supply (four power supply wirings in the figure). The voltage of the ring-shaped gate potential control circuit 31 in each row is supplied from the power supply unit 38 arranged at one place.

  FIG. 5 shows a layout of the transfer gate potential control circuit 41 on the solid-state imaging device. In FIG. 2, the transfer gate potential control circuit 41 is depicted in each row, but actually, the transfer gate potential control circuit 41 is arranged at one place in the peripheral portion of the pixel unit 43. The transfer gate electrodes of all the pixels Px are controlled. This is because the operation of the pixel transfer gate potential control circuit 41 is simultaneously performed at all timings as can be seen from the timing chart of FIG. Therefore, as shown in the drawing, signals are transferred to all the pixels from the gate potential control circuit 41 arranged at one place. The transfer gate potential control circuit 41 is connected to the frame start signal generation circuit 42. The transfer gate potential control circuit 41 is connected to all m × n pixels in the pixel portion 43 by transfer gate electrode wirings 44 that are wired for each row.

  A power supply unit 46 is provided in the periphery of the pixel unit 43. The power supply unit 46 includes two power supplies for supplying two different potentials, that is, Low2 and Vdd. A voltage is supplied from the power supply section 46 to the transfer gate potential control circuit 41 through a power supply wiring group 45 collectively showing wirings of each power supply (two power supply wirings in the figure).

  FIG. 6 shows a block diagram of the ring-shaped gate potential control circuit 31 as a configuration example of the control circuit. The ring-shaped gate potential control circuit 31 is mainly composed of a CMOS structure analog switch circuit 52 that switches the potential of a signal supplied to a pixel, and a signal switching control circuit 53 that controls the timing of switching the signal potential. . A switch switching signal 54 is output from the signal switching control circuit 53 to the analog switch circuit 52. As described above, the power source unit 38 supplies the analog switch circuit 52 with four types of voltages having predetermined potentials. The ring-shaped gate potential signal 56 output from the analog switch circuit 52 changes the signal potential among the above four types by the switch switching signal 54. Although the ring-shaped gate potential control circuit 31 has been described as an example of the configuration in the figure, the transfer gate potential control circuit 41 and other control circuits, that is, the drain potential control circuit 8 and the source potential control circuit 14 are similar to the signal switching control circuit 53. An analog switch circuit 52 is included. However, the type of potential to be switched corresponds to the type in each control circuit.

FIG. 7 shows an analog switch circuit of the control circuit. Here, a configuration example of the analog switch circuit 52 in the ring-shaped gate potential control circuit 31 is shown as a representative. As shown in FIG. 7, here, the analog switch circuit 52 includes four analog switches A1 to A4. Each of the analog switches A1 to A4 includes a CMOS transistor 26 including an n-channel MOS 61 and a p-channel MOS 62.
An inverter 24 is interposed in front of the gate of the n-channel MOS 61. Here, the potential Low switching signal 54A, the potential Low2 switching signal 54B, the potential Vg1 switching signal 54C, and the potential Vdd switching signal 54D are supplied to the gate side of the CMOS transistor 26 constituting each analog switch A1 to A4. Similarly, four predetermined potentials, that is, Low, Low1, Vg1, and Vdd are respectively supplied to one terminal side of each of the analog switches A1 to A4, and the other terminal side is connected to the ring-shaped gate electrode wiring 33. Yes. Then, by controlling the gate electrode of each CMOS transistor 26 with each switching signal 65A to 54D, four kinds of predetermined potentials can be selectively supplied to the pixels.

  For example, in order to set the potential of the ring-shaped gate electrode to Low, the analog switch A1 is set so that the potential Low switching signal 54A is set to “L” and the potential of the Low signal from the power supply unit 38 (see FIG. 4) is selected. Turn on. At this time, the other switching signals 54B to 54D are set to “H”. As a result, the potential of the ring-shaped gate electrode wiring 33 in the pixel portion becomes Low. Similarly, in order to set the potential of the ring-shaped gate electrode wiring to the potentials of Low1, Vg1, and Vdd, the same thing is performed. In the other control circuits 8, 14, and 41, analog switches each including the CMOS transistor 26 are provided by the number of types of the predetermined potential to be set, and the predetermined potential is selectively output in the same manner. .

  Incidentally, the layout of the solid-state imaging device described with reference to FIGS. 4 and 5 is such that one row or all pixels are connected to one control circuit (feature 1), and the wiring from the control circuit to the pixels is long. The following problems were newly discovered from the feature that there is a restriction (feature 2) and the voltage source supplied to the control circuit is one place (feature 3).

  FIG. 8 is a diagram for explaining a problem of “periods (4) to (6) in FIG. 3” of the control signal output from the ring-shaped gate potential control circuit 31 in the s row. The ideal timing is that the potentials of the control signals supplied to the ring-shaped gate electrodes of the pixels in the s row and the first column and the pixels in the s row and the t column match as shown in FIG. However, in reality, as shown in FIG. 8B, the potential of the pixel in the t-th column does not rise to High1, but becomes High1 ′ (High1> High1 ′), and does not match the potential of the control signal between pixels connected to the same row. Occurs. This is because, in a pixel far from the control circuit 31, the drive capability (the maximum current that flows) of the control circuit 31 is limited, so that it is difficult to charge a pixel far from the control circuit 31.

  In other words, this may be due to the fact that there is one power source supplied to the control circuit 31 and the lack of drive capability due to the control circuit 31 controlling pixels for one row. As a result, in the pixels between the same rows, the potential of the p-type region in the vicinity of the source is raised, and the reset in which holes are discharged to the p-type epitaxial layer beyond the barrier of the n-well occurs. Here, the potential “High1” related between the pixels in the same row is considered as a problem, but it is considered that the same phenomenon occurs even at the potential of Vg1. Such a problem becomes more prominent when all the pixels having a large capacity are driven all at once.

  FIG. 9 is a diagram for explaining the problem of the “period (2) period in FIG. 3” of the control signal output from the transfer gate potential control circuit 41. As shown in FIG. 9A, the ideal timing is that the timings of the control signals of the first row and the first column and the first row and the nth column or the mth row and the nth column are the same, and the voltage drops are the same. However, actually, as shown in FIG. 9B, the signal is delayed by the pixel. Further, as shown in FIG. 9C, the voltage does not drop to a predetermined value by the pixel. In FIG. 9C, there arises a problem that the pixel of m rows and n columns does not fall from Vdd to Low 2 but falls only to Low 2 '(Low 2'> Low 2). In addition to the cause described in FIG. 8, the cause of this is the difference in the wiring length connected from the control circuit to each pixel (the distance from the control circuit is different between the pixel in the first row and the first column and the pixel in the m row and the n column). Signal delay due to the difference). As a result, a signal delay caused by a difference in wiring length causes a shift in data transfer between pixels, that is, a phenomenon in which the hole transfer timing is shifted for each pixel. In addition, an afterimage is generated due to the remaining transfer of hole charges from the photodiodes performed simultaneously in all pixels.

The problem described with reference to FIGS. 8 and 9 is a phenomenon caused by the limitations of the features 1 to 3 described above. These problems cause image deterioration.
By the way, the maximum potential of the ring-shaped gate electrode of FIGS. 4 and 6 is Vdd, which is a case where High1 = Vdd is set. When High1> Vdd, it is necessary to newly provide a power supply and analog switch for High1. At this time, since High1 is larger than Vdd, the power supply / analog switch needs to be a high voltage transistor. When this high breakdown voltage transistor is used, the drive current is reduced, and the above-described problem becomes more remarkable.

The present invention further solves the above problems.
It will be described in detail below Kazumi施例of a solid-state imaging device according to the specific invention.
10 is a diagram showing an example of a layout when the ring-shaped gate potential control circuit is mainly taken up in the solid-state imaging device according to the present invention. FIG. 11 is an analog switch of the ring-shaped gate potential control circuit in the solid-state imaging device according to the present invention. It is a circuit diagram which shows a circuit. This embodiment is configured as follows mainly in order to solve the problem described with reference to FIG.

Here, as an example, a ring-shaped gate potential control circuit will be described, but other control circuits have a configuration according to this configuration. Since the basic configuration of the solid-state imaging device is the same as that shown in FIGS. 2 to 9 described above, different points will be mainly described here.
As is apparent from comparison with FIG. 4, as shown in FIG. 10, here, with respect to the ring-shaped gate potential control circuit 31, a plurality, that is, two power supply units 38, 38 </ b> A are provided apart from each other. One power supply unit 38 is the same as that of the conventional structure shown in FIG. 4, and the other power supply unit 38A is newly provided here. In this case, the new power supply unit 38A is disposed around the pixel unit 43, and is separated from the power supply unit 38 by a distance corresponding to the length of one side of the pixel unit 43 region. Yes.

The new power supply unit 38A also includes power supplies that output four predetermined potentials, that is, Low, Low1, Vg1, and Vdd. The new power supply unit 38A and the ring-shaped gate potential control circuit 31 are connected by a power supply wiring group 37A in which four wirings are bundled. The new power supply wiring group 37A and the previous power supply wiring group 37 are connected by a ring-shaped gate potential control circuit 31.
Thereby, in the conventional solid-state imaging device, it is possible to improve the decrease in the potential on the s-row side (the lower side in the figure) that was physically far from the power supply unit 38.
It should be noted that three or more power supply units 38, 38A may be used and disposed between the two power supply units 38, 38A to further improve the potential drop.

Next, the improvement of the analog switch circuit 52 (see FIG. 6) in the ring-shaped gate potential control circuit 31 will be described with reference to FIG.
In the case shown in FIG. 6, each of the four analog switches A1 to A4 is configured by one CMOS transistor 26 including one n-channel MOS 61 and one P-channel MOS 62. In the case of the present invention shown in FIG. 11, each of the four analog switches B <b> 1 to B <b> 4 is composed of a plurality of, for example, four CMOS transistors 26. The number of CMOS transistors 26 is not limited as long as it is two or more.

Specifically, as described above, the CMOS transistor 26 includes one n-channel MOS and one p-channel MOS. For example, the analog switch B1 is configured by connecting four CMOS transistors 26 in parallel. As a result, the channel length of the transistor is apparently increased. As a result, the current that can be output can be increased, and as a result, the drive capability of the analog switch circuit 52 can be increased.
Then, an inverter 24 is interposed in front of the n-channel MOS 61. The other analog switches B1 to B4 are configured similarly to the analog switch B1.

  Here, similarly to the case described with reference to FIG. 7, the potential Low switching signal 54A, the potential Low2 switching signal 54B, the potential Vg1 switching signal 54C, and the potential Vdd are provided on the gate side of the CMOS transistor 26 constituting each of the analog switches B1 to B4. A switching signal 54D is supplied. Similarly, four predetermined potentials, that is, Low, Low1, Vg1, and Vdd are respectively supplied to one terminal side of each of the analog switches B1 to B4, and the other terminal side is connected to the ring-shaped gate electrode wiring 33. Yes.

  With the configuration as described above, the problem described with reference to FIG. 8 can be solved. That is, first, by using the analog switch circuit 52 with increased driving capability described in FIG. 11 for the ring-shaped gate potential control circuit 31, it is possible to increase the driving capability of signals supplied to a plurality of pixels in the same row. Further, the power supply unit 38 related to the potential of the signal is arranged from one place to a plurality of places. For example, in this embodiment, the power supply unit 38A is arranged in addition to the power supply unit 38 to provide two places in total. Then, with respect to the ring-shaped gate potential control circuit 31 in each row (for example, s row), the voltage is applied to the power supply wiring group 37 and the power supply wiring group 37A of the four power supply wirings from the two places of the power supply unit 38 and the power supply unit 38A in the drawing. Supply. As a result, the drive capability of the ring-shaped gate potential control circuit 31 can be increased, and the pixel Px35 from the s row to the first column in the pixel portion (m row and n column) 43 to the pixel from the s row to the n column. The signal potential of the ring-shaped gate electrode wiring 33 connected to Px36 can be stabilized. As a result, the variation in potential of the ring gate electrode between a plurality of pixels in the same row described in FIG. 8 can be eliminated and uniformized. From the above results, the potential of the p-type region in the vicinity of the source is raised, and it is possible to prevent variations in resetting that holes are discharged to the p-type epitaxial layer beyond the barrier of the n-well.

  In the above embodiment, the case where the configuration shown in FIG. 11 is used as the analog switch circuit 52 of the ring-shaped potential control circuit 31 has been described as an example. Instead, the conventional analog switch circuit 52 shown in FIG. A plurality of power supply units 38, 38A may be provided. Also in this case, although not as much as the above embodiment, the operation capability of the analog switch circuit 52 can be improved as compared with the conventional circuit.

  Next, improvement of the transfer gate potential control circuit will be described. FIG. 12 is a diagram showing an example of a layout when the transfer gate potential control circuit of the solid-state imaging device according to the present invention is mainly taken up. FIG. 13 shows an analog switch circuit of the transfer gate potential control circuit in the solid-state imaging device according to the present invention. It is a circuit diagram. This embodiment is configured as follows mainly in order to solve the problem described with reference to FIG.

  As apparent from comparison with FIG. 5, here, as shown in FIG. 12, a plurality of transfer gate potential control circuits 41, that is, four transfer gate potential control circuits 41, 41 </ b> A, 41 </ b> B, 41 </ b> C, Correspondingly, four power supply units 46, 46A, 46B, 46C are provided separately from each other. The newly applied transfer gate potential control circuits 41A to 41C and power supply units 46A to 46C are the same as those of the conventional structure shown in FIG. In this case, the transfer gate potential control circuits 41, 41 </ b> A to 41 </ b> C and the power supply units 46, 46 </ b> A to 46 </ b> C are arranged at the four corners around the pixel unit 43 and correspond to the length of one side of the region of the pixel unit 43. They are provided separated by a distance.

The new power supply units 46A to 46C also include power supplies that output two predetermined potentials, that is, Low2 and Vdd, respectively. The new power supply units 46A to 46C and the new transfer gate potential control circuits 41A to 41 are connected to each other by power supply wiring groups 45A, 45B, and 45C in which two wirings are bundled.
The power supply wiring groups 45 and 45 </ b> A to 45 </ b> C are connected to each other by a common line 25 provided along the periphery of the pixel unit 43. The frame start signal from the frame start signal generating circuit 42 is supplied to the transfer gate potential control circuits 41 and 41A to 41C through the common line 27. Further, a common line 28 is connected around the pixel portion 43 so as to connect both ends of all the transfer gate electrode wirings 44 and outputs of the transfer gate potential control circuits 41 and 41A to 41C.

Thereby, in the conventional solid-state imaging device, the s row side (lower side in the drawing) and the n column side (right side in the drawing) which are physically far from the power supply unit 46 and the transfer gate potential control circuit 41 are provided. It is possible to improve the decrease in potential.
The transfer gate potential control circuit 41 and the power supply units 46 corresponding thereto are not limited to four, and at least two or more may be provided to improve the potential drop. For example, when two are provided, they may be arranged so as to be positioned at, for example, the corners in the diagonal direction with respect to the pixel portion 43.

Next, the improvement of the analog switch circuit in the transfer gate potential control circuits 41 and 41A to 41C will be described with reference to FIG.
In this case, the structure is the same as the structure using two analog switches among the four analog switches B1 to B4 shown in FIG. That is, in the case of the present invention shown in FIG. 13, each of the two analog switches B <b> 1 and B <b> 2 is composed of a plurality of, for example, four CMOS transistors 26. The number of CMOS transistors 26 is not limited as long as it is two or more.

  Specifically, as described in FIG. 11, the CMOS transistor 26 is composed of one n-channel MOS and one p-channel MOS as described above. For example, the analog switch B1 includes four CMOS transistors 26. The transistors are configured to be connected in parallel, so that the channel length of the transistor is apparently increased. As a result, the current that can be output can be increased, and as a result, the drive capability of the analog switch circuit 52 can be increased. Then, an inverter 24 is interposed in front of the n-channel MOS 61.

  As described above, a plurality of transfer gate potential control circuits 41 are provided, and a plurality (four) of power supply units 46 are provided and strengthened accordingly. The potential of the transfer gate electrode can be made uniform across the pixels. In addition, since a plurality of power supply units 46 and transfer gate potential control circuits 41 are arranged at a plurality of locations, a common frame start signal for connection from the frame start signal generation circuit 42 to each of the transfer gate potential control circuits 41, 41A to 41C. The line 27 is wired so as to surround the periphery of the pixel portion 43. Similarly, in the drawing in which the power supply portions 46 and 46A to 46C are connected to the transfer gate potential control circuits 41 and 41A to 41C, two power supply wires are formed. The power supply common line 25 is also wired so as to surround the periphery of the pixel portion 43, and both ends of the transfer gate electrode wiring 44 connected to each pixel of the pixel portion 43 from the transfer gate potential control circuits 41 and 41A to 41C are connected. Since the connected common line 28 is also wired so as to surround the periphery of the pixel portion 43, the wiring length connected to each pixel from the transfer gate potential control circuit is thereby reduced. It is possible to solve the signal delay pressing the variability. From the above results, the problem described with reference to FIG. 9 can be solved, and variations in the transfer of hole charges from the photodiodes performed simultaneously in all pixels can be prevented. Further, according to the present embodiment, problems such as an afterimage phenomenon that has occurred in the conventional apparatus can be solved.

Further, as in this embodiment, the control circuit and the power supply unit are divided and arranged, so that not only signal transmission and voltage drop can be made uniform, but also the circuit scale can be increased to improve drive capability. An efficient arrangement of the increased control circuit can be realized.
As is well known, such a solid-state imaging device can be used for video systems such as video cameras and digital cameras.
In the above embodiment, the ring-shaped gate potential control circuit 31 and the transfer gate potential control circuit 41 have been described as examples. However, the present invention also applies to the drain potential control circuit 8 and the source potential control circuit 14 that output a plurality of predetermined potentials. Of course, it can be applied.

It is a figure which shows the structure for one pixel. It is an equivalent circuit which shows the pixel of s row and t column of the solid-state imaging device comprised by the pixel part of the m row n column which this applicant proposed in the previous application. It is a figure which shows the timing chart of the signal of each control circuit, and a CMOS sensor equivalent circuit. It is a figure which shows the layout of the ring-shaped gate potential control circuit of the s line on a solid-state imaging device. It is a figure which shows the layout of the transfer gate electric potential control circuit on a solid-state imaging device. It is a block circuit showing a ring-shaped gate potential control circuit. It is a figure which shows the analog switch circuit of a control circuit. It is a figure explaining the problem of "the period of the period (4)-(6) in FIG. 3" of the control signal output from a ring-shaped gate potential control circuit. FIG. 4 is a diagram for explaining a problem of “period (2) in FIG. 3” of a control signal output from a transfer gate potential control circuit. It is a figure which shows an example of a layout when the ring-shaped gate potential control circuit is mainly taken up in the solid-state imaging device according to the present invention. It is a circuit diagram which shows the analog switch circuit of the ring-shaped gate electric potential control circuit in the solid-state imaging device concerning this invention. It is a figure which shows an example of a layout when the transfer gate electric potential control circuit of the solid-state imaging device of this invention is mainly picked up. It is a circuit diagram which shows the analog switch circuit of the transfer gate electric potential control circuit in the solid-state imaging device concerning this invention. It is a schematic block diagram which shows the conventional general image pick-up apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 2,4 ... MOSFET, 6 ... Photodiode, 8 ... Drain potential control circuit, 14 ... Source potential control circuit, 22 ... Horizontal shift register, 26 ... CMOS transistor, 31 ... Ring gate potential control circuit, 32 ... Vertical shift register , 38, 38A ... power supply unit, 41, 41A-41C ... transfer gate potential control circuit, 43 ... pixel unit (m rows and n columns), 46, 46A-46C ... power supply unit, 52 ... analog switch circuit, 61 ... n channel MOS, 62... P-channel MOS, B1 to B4... Analog switch, Px.

Claims (2)

A photodiode for storing charges generated by photoelectric conversion of incident light; a transfer gate electrode; a transfer gate transistor for transferring charges stored in the photodiode; and a ring-shaped gate electrode; A pixel portion in which a plurality of pixels including a ring-shaped gate transistor that accumulates charges transferred from the transfer transistor are arranged in a matrix in the row direction and the column direction ;
A first power supply unit that is arranged around one side in the column direction in the pixel unit and supplies a first plurality of different potentials;
A second power supply unit that is arranged around the opposite side of the one side in the column direction of the pixel unit and is spaced apart from the first power supply unit and supplies the first potentials different from each other; ,
Ring-shaped gate potential control that selects a predetermined potential from the first plurality of different potentials supplied from the first power supply unit and the second power supply unit and supplies the selected potential to the ring-shaped gate electrode. And
A solid-state imaging device comprising: A third power supply unit disposed around the pixel unit and supplying a second plurality of different potentials;
A fourth power supply unit that is arranged around the pixel unit and spaced apart from the third power supply unit, and supplies a second plurality of different potentials;
A transfer gate potential control unit that selects a predetermined potential from a plurality of different second potentials respectively supplied from the third power supply unit and the fourth power supply unit and supplies the selected potential to the transfer gate electrode; ,
The solid-state imaging device according to claim 1, further comprising:

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