WO2024009600A1 - Solid-state imaging element and imaging device - Google Patents

Abstract

The present invention suppresses an increase in circuit scale in a solid-state imaging element in which the drive performance of a drive circuit is variable.　This solid-state imaging element is equipped with a driver, a current mirror and a current control circuit. The driver in the solid-state imaging element outputs a prescribed drive signal from an output terminal. The current mirror in the solid-state imaging element generates an output current which corresponds to a prescribed reference current, and causes the same to flow to the power source side of the driver or the ground side thereof. The current control circuit in the solid-state imaging element controls the current value of the reference current.

Description

Solid-state imaging device and imaging device

The present technology relates to a solid-state image sensor. Specifically, the present invention relates to a solid-state imaging device and an imaging device having a drive circuit that drives pixels.

Conventionally, in solid-state image sensors and the like, drive circuits have been arranged for each row in order to drive the rows. For example, a solid-state image sensor has been proposed in which a circuit including two stages of inverters is arranged as a drive circuit for each row and the voltage is controlled to prevent blooming (see, for example, Patent Document 1).

Japanese Patent Application Publication No. 2012-195734

The above-mentioned conventional technology attempts to improve image quality by taking measures against blooming. However, in the above-described solid-state image sensor, there is a problem in that the number of inverter stages needs to be increased when improving the driving capability of the drive circuit, resulting in an increase in circuit scale.

The present technology was created in view of this situation, and its purpose is to suppress the increase in circuit scale in a solid-state image sensor in which the driving ability of the driving circuit is variable.

This technology was developed to solve the above-mentioned problems, and its first aspect is a driver that outputs a predetermined drive signal from an output terminal, and a driver that generates an output current according to a predetermined reference current. a current mirror that causes the current to flow to at least one of the power supply side and the ground side of the driver;
The present invention provides a solid-state imaging device and an imaging device including a current control circuit that controls the current value of the reference current. This brings about the effect of suppressing an increase in circuit scale.

Further, in this first aspect, a pixel array section may be further provided in which a plurality of pixels that generate analog signals in accordance with the drive signal are arranged in a two-dimensional grid. This brings about the effect that an image is captured.

Further, in this first aspect, the driver and the current mirror are arranged for each row in the pixel array section, and the current mirror includes a mirror source transistor that flows the reference current and a mirror destination that generates the output current. It may also include a transistor. This provides the effect of suppressing current variations from row to row.

Further, in this first aspect, the current mirror includes a mirror source transistor through which the reference current flows, and first and second mirror destination transistors that share the mirror source transistor and generate the output current. , the driver includes first and second drivers, the first driver outputs the output current to a first row within the pixel array section, and the second driver outputs the output current to a first row within the pixel array section. the first mirrored transistor outputs the output current to a second row of the first driver, the second mirrored transistor supplies the output current to the second driver; An output current may be applied. This brings about the effect that the circuit scale of the vertical scanning circuit is reduced.

Further, in this first aspect, a first analog-to-digital converter converts an analog signal from the first row into a digital signal, and a second analog-to-digital converter converts an analog signal from the second row into a digital signal. and an analog-to-digital converter, the first and second drivers may simultaneously supply the output current. This brings about the effect that multiple rows are read at the same time.

In addition, in this first aspect, it may further include a selection switch that opens and closes a path between the current mirror and the current control circuit in synchronization with a predetermined selection signal. This brings about the effect of reducing power consumption.

Furthermore, in this first aspect, the device may further include a logic gate that generates and outputs the selection signal, and a latch circuit that holds the output selection signal and supplies it to the selection switch. This brings about the effect of suppressing potential fluctuations due to settling.

Further, in this first aspect, the output current includes first and second output currents, and the current mirror is configured to generate a power supply side current that causes the first output current to flow from the power supply node to the power supply terminal of the driver. The device may include a mirror and a ground side current mirror that causes the second output current to flow from the ground terminal of the driver to the ground node. This brings about the effect that the currents on both the power supply side and the ground side are controlled.

In addition, a second aspect of the present technology includes a variable current source, a mirror source transistor through which a reference current generated by the variable current source flows, and an output current corresponding to the reference current and outputting a voltage signal from the drain. The solid-state image sensing device includes a mirror destination transistor, and a sample and hold circuit that samples and holds a voltage between the gate and source of the mirror destination transistor in synchronization with a predetermined control signal. This brings about the effect of stabilizing the driving ability.

FIG. 1 is a block diagram illustrating a configuration example of an imaging device according to a first embodiment of the present technology. FIG. 1 is a block diagram showing an example of a configuration of a solid-state image sensor according to a first embodiment of the present technology. FIG. 2 is a circuit diagram showing an example of a configuration of a pixel in a first embodiment of the present technology. FIG. 1 is a block diagram illustrating a configuration example of a vertical scanning circuit according to a first embodiment of the present technology. FIG. 2 is a block diagram illustrating a configuration example of a drive unit in the first embodiment of the present technology. FIG. 2 is a circuit diagram illustrating a configuration example of a transfer drive circuit according to the first embodiment of the present technology. FIG. 2 is a circuit diagram showing a configuration example of a drive circuit for initialization in the first embodiment of the present technology. FIG. 2 is a circuit diagram showing a configuration example of a selection drive circuit in the first embodiment of the present technology. FIG. 2 is a circuit diagram showing a configuration example of a current control circuit according to a first embodiment of the present technology. FIG. 2 is a circuit diagram showing a configuration example of a drive circuit in a first comparative example. FIG. 2 is a circuit diagram showing a configuration example of a column signal processing circuit according to a first embodiment of the present technology. It is a timing chart which shows an example of operation of a solid-state image sensing device in a 1st embodiment of this art. FIG. 6 is a diagram illustrating an example of the state of the drive circuit of each row when driving the first row in the first embodiment of the present technology. FIG. 7 is a diagram illustrating an example of the state of the drive circuit of each row when driving the second row in the first embodiment of the present technology. FIG. 6 is a diagram illustrating an example of the state of the drive circuit of each row when driving the last row in the first embodiment of the present technology. FIG. 2 is a block diagram illustrating a configuration example of a solid-state image sensor according to a second embodiment of the present technology. FIG. 7 is a circuit diagram illustrating a configuration example of a drive circuit according to a second embodiment of the present technology. FIG. 7 is a circuit diagram showing an example of a configuration of a drive circuit and a current control circuit in a third embodiment of the present technology. FIG. 7 is a diagram illustrating an example of a drive circuit and operation in a second comparative example. 12 is a timing chart illustrating an example of the operation of the drive circuit in the third embodiment of the present technology. It is a figure for explaining the effect in a 3rd embodiment of this technology.

Hereinafter, a mode for implementing the present technology (hereinafter referred to as an embodiment) will be described. The explanation will be given in the following order.
1. First embodiment (example of controlling the current value of reference current)
2. Second embodiment (example where the current value of the reference current is controlled and a mirror source transistor is shared by multiple rows)
3. Third embodiment (example of controlling the current value of the reference current and maintaining the gate-source voltage of the mirror destination transistor)

<1. First embodiment>
[Example of configuration of imaging device]
FIG. 1 is a block diagram illustrating a configuration example of an imaging device according to a first embodiment of the present technology. The imaging device 100 is a device for capturing image data, and includes an optical section 110, a solid-state imaging device 200, and a DSP (Digital Signal Processing) circuit 120. Further, the imaging device 100 includes a display section 130, an operation section 140, a bus 150, a frame memory 160, a storage section 170, and a power supply section 180. As the imaging device 100, a smartphone, a digital still camera, a vehicle-mounted camera, etc. are assumed.

The optical section 110 collects light from a subject and guides it to the solid-state image sensor 200. The solid-state image sensor 200 generates image data through photoelectric conversion. This solid-state image sensor 200 generates image data and supplies it to the DSP circuit 120 via a signal line 209.

The DSP circuit 120 performs predetermined signal processing on image data. This DSP circuit 120 outputs the processed image data to a frame memory 160 or the like via a bus 150.

The display unit 130 displays image data. As the display unit 130, for example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed. The operation unit 140 generates an operation signal according to a user's operation.

The bus 150 is a common path through which the optical section 110, solid-state image sensor 200, DSP circuit 120, display section 130, operation section 140, frame memory 160, storage section 170, and power supply section 180 exchange data with each other.

The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply section 180 supplies power to the solid-state image sensor 200, the DSP circuit 120, the display section 130, and the like.

[Configuration example of solid-state image sensor]
FIG. 2 is a block diagram showing a configuration example of the solid-state image sensor 200 in the first embodiment of the present technology. This solid-state imaging device 200 includes a vertical scanning circuit 300, a pixel array section 210, a timing control circuit 230, and a column signal processing circuit 250.

A plurality of pixels 220 are arranged in a two-dimensional grid in the pixel array section 210. Hereinafter, a set of pixels 220 arranged in the horizontal direction will be referred to as a "row", and a set of pixels 220 arranged in the vertical direction will be referred to as a "column".

The pixel 220 generates an analog pixel signal by photoelectric conversion according to the drive signal from the vertical scanning circuit 300, and outputs it to the column signal processing circuit 250.

The vertical scanning circuit 300 sequentially drives the rows and outputs pixel signals. The timing control circuit 230 controls the operation timing of the vertical scanning circuit 300 and the column signal processing circuit 250 in synchronization with the vertical synchronization signal VSYNC indicating the imaging timing.

The column signal processing circuit 250 performs various signal processing such as AD (Analog to Digital) conversion processing and CDS (Correlated Double Sampling) processing on pixel signals from each column. The column signal processing circuit 250 supplies image data in which processed pixel signals are arranged to the DSP circuit 120. Note that the column signal processing circuit 250 is an example of a signal processing circuit described in the claims.

[Example of pixel configuration]
FIG. 3 is a circuit diagram showing a configuration example of the pixel 220 in the first embodiment of the present technology. This pixel 220 includes a photoelectric conversion element 221, a transfer transistor 222, a reset transistor 223, a floating diffusion layer 224, an amplification transistor 225, and a selection transistor 226. Further, in the pixel array section 210, vertical signal lines 219 are wired for each column.

The photoelectric conversion element 221 generates charges by photoelectric conversion of incident light. The transfer transistor 222 transfers charges from the photoelectric conversion element 221 to the floating diffusion layer 224 in accordance with the drive signal TRG from the vertical scanning circuit 300. The reset transistor 223 initializes the floating diffusion layer 224 according to the drive signal RST from the vertical scanning circuit 300.

The floating diffusion layer 224 accumulates charge and generates a voltage according to the amount of charge. The amplification transistor 225 amplifies the voltage of the floating diffusion layer 224. The selection transistor 226 outputs the amplified voltage signal as a pixel signal to the column signal processing circuit 250 via the vertical signal line 219 in accordance with the selection signal SEL from the vertical scanning circuit 300.

Note that the circuit configuration of the pixel 220 is not limited to that illustrated in the figure as long as it can generate a pixel signal according to the control of the vertical scanning circuit 300.

[Example of configuration of vertical scanning circuit]
FIG. 4 is a block diagram showing a configuration example of the vertical scanning circuit 300 in the first embodiment of the present technology. This vertical scanning circuit 300 includes a decoder 310, a current control circuit 320, and a drive section 330.

The decoder 310 generates a plurality of signals through decoding processing under the control of the timing control circuit 230. This decoder 310 supplies these signals to the drive section 330.

In the drive unit 330, drive circuits 400, 500, and 600 are arranged for each row. Assuming that the number of rows is N (N is an integer), N driving circuits 400, 500, and 600 are provided.

The drive circuit 400 generates a drive signal TRG for charge transfer and outputs it to the corresponding row. The drive circuit 500 generates a drive signal RST for initialization and outputs it to a corresponding row. The drive circuit 600 generates a selection signal SEL and outputs it to a corresponding row. Let TRG, RST, and SEL in the n-th (n is an integer from 1 to N) row be TRGn, RSTn, and SELn, respectively.

The current control circuit 320 controls the current within the drive unit 330 according to setting data indicating a current value.

[Example of configuration of drive unit]
FIG. 5 is a block diagram showing a configuration example of the drive section 330 in the first embodiment of the present technology. A signal from decoder 310 is input to each of drive circuits 400 and 500. The first row drive circuit 400 generates a selection signal SEL1 and supplies it to the first row drive circuits 500 and 600. Further, drive circuits 400, 500, and 600 are commonly connected to current control circuit 320. The same applies to each drive circuit corresponding to the second and subsequent rows.

[Configuration example of drive circuit]
FIG. 6 is a circuit diagram showing a configuration example of the transfer drive circuit 400 in the first embodiment of the present technology. This drive circuit 400 includes a selection signal generation section 410, a control signal generation section 420, selection switches 431 and 432, current mirrors 440 and 460, and a driver 450.

The selection signal generation section 410 generates the selection signal SEL1. This selection signal generation section 410 includes a logic gate 411 and a latch circuit 412. As the logic gate 411, for example, a NAND (not logical product) gate is used.

The logic gate 411 performs a predetermined logical operation on a plurality of signals from the decoder 310. This logic gate 411 supplies the processing result to the latch circuit 412 as a selection signal SEL1. The latch circuit 412 holds the selection signal SEL1 from the logic gate 411 and supplies the signal to the selection switches 431 and 432, the drive circuit 500, and the like. The time that the latch circuit 412 holds is set in consideration of the settling time of the selection switches 431 and 432.

The control signal generation unit 420 generates a control signal xTRG1 and supplies it to the input terminal 458 of the driver 450. The circuit configuration of this control signal generation section 420 is the same as that of the selection signal generation section 410, for example.

The current mirror 440 generates an output current Iout1 according to the reference current Iref1 and sends it to the power supply side (that is, from the power supply node to the power supply terminal 456 of the driver 450). For example, a current having the same value as the reference current Iref1 is generated as the output current Iout1. This current mirror 440 includes a mirror source transistor 441 and a mirror destination transistor 442. For example, pMOS transistors are used as these transistors. Note that the current mirror 440 is an example of a power supply side current mirror described in the claims.

The mirror source transistor 441 is for flowing the reference current Iref1. The mirror destination transistor 442 generates an output current Iout1 according to the reference current Iref1, and causes it to flow from the power supply node to the power supply terminal 456. The sources of these mirror source transistor 441 and mirror destination transistor 442 are commonly connected to a power supply node. Further, the gate and drain of the mirror source transistor 441 are short-circuited, and the drain is connected to the selection switch 431. The gate of the mirror destination transistor 442 is connected to the gate of the mirror source transistor 441, and the drain is connected to the power supply terminal 456.

The driver 450 generates a drive signal TRG1 based on the control signal xTRG1 and outputs it to the corresponding row of the pixel array section 210. This driver 450 includes a pMOS transistor 451 and an nMOS transistor 452. These transistors are connected in series between power supply terminal 456 and ground terminal 457. Further, the gates of these transistors are commonly connected to an input terminal 458, and the connection nodes of these transistors are connected to an output terminal 459. With this circuit configuration, the driver 450 functions as an inverter that inverts the control signal xTRG1 and outputs it as the drive signal TRG1. Furthermore, when inverting, the driver 450 shifts the level of the signal as necessary.

The current mirror 460 generates an output current Iout2 according to the reference current Iref2 and sends it to the ground side (that is, from the ground terminal 457 of the driver 450 to the ground node). For example, a current having the same value as the reference current Iref2 is generated as the output current Iout2. This current mirror 460 includes a mirror source transistor 461 and a mirror destination transistor 462. For example, nMOS transistors are used as these transistors. Note that the current mirror 460 is an example of a ground side current mirror described in the claims.

The mirror source transistor 461 is for flowing the reference current Iref2. The mirror destination transistor 462 generates an output current Iout2 according to the reference current Iref2, and causes it to flow from the ground terminal 457 to the ground node. The sources of mirror source transistor 461 and mirror destination transistor 462 are commonly connected to a ground node. Further, the gate and drain of the mirror source transistor 461 are short-circuited, and the drain is connected to the selection switch 432. The gate of the mirror destination transistor 462 is connected to the gate of the mirror source transistor 461, and the drain is connected to the ground terminal 457.

Selection switches 431 and 432 open and close paths between current mirrors 440 and 460 and current control circuit 320 according to selection signal SEL. Selection switch 431 is connected to current control circuit 320 via signal line 329, and selection switch 432 is connected to current control circuit 320 via signal line 328. This current control circuit 320 controls the current values of reference currents Iref1 and Iref2.

As illustrated in the figure, by providing current mirrors 440 and 460 in the drive circuit 400 and controlling the value of the reference current, the drive capability of the drive circuit 400 can be freely adjusted. In this method, since there is no need to increase or decrease the number of inverter stages, it is possible to suppress an increase in circuit scale when improving drive capability.

Further, since the mirror source transistors 441 and 461 are arranged in the drive circuit 400, it is possible to suppress variations in current due to fluctuations in voltage and temperature, and realize stable driving of the drive circuit 400.

Furthermore, since the selection switches 431 and 432 open and close according to the selection signal SEL, power consumption can be reduced compared to the case where they are always connected to the current control circuit 320.

Although current mirrors are arranged on both the power supply side and the ground side of the driver 450, they can also be arranged only on one side.

Further, although selection switches 431 and 432 are provided, current mirrors 440 and 460 and current control circuit 320 may be directly connected without providing these.

Furthermore, although an inverter is arranged as the driver 450, a buffer can also be arranged. Furthermore, multiple stages of inverters and buffers can be arranged as the driver 450.

Further, although the current mirrors 440 and 460 generate an output current having the same value as the reference current, they can also generate an output current that is twice or more the reference current. In this case, mirror destination transistors are added in a number corresponding to the value of the output current and connected in parallel.

FIG. 7 is a circuit diagram showing a configuration example of the initialization drive circuit 500 in the first embodiment of the present technology. This drive circuit 500 includes a control signal generation section 520, selection switches 531 and 532, current mirrors 540 and 560, and a driver 550.

The circuit configurations of the control signal generation section 520, selection switches 531 and 532, current mirrors 540 and 560, and driver 550 are similar to the circuits with the same names in the drive circuit 400. However, the control signal generation unit 520 generates the control signal xRST1, and the driver 550 inverts the control signal xRST1 and outputs it as the drive signal RST1.

FIG. 8 is a circuit diagram showing a configuration example of the selection drive circuit 600 in the first embodiment of the present technology. This drive circuit 600 includes selection switches 631 and 632, current mirrors 640 and 660, and a driver 650.

The respective circuit configurations of the selection switches 631 and 632 and the current mirrors 640 and 660 are similar to the circuits with the same names in the drive circuit 400.

The driver 650 changes the level of the selection signal SEL1 as necessary and outputs it to the corresponding first row. A buffer or a two-stage inverter is used as the driver 650.

[Example of configuration of current control circuit]
FIG. 9 is a circuit diagram showing a configuration example of the current control circuit 320 in the first embodiment of the present technology. This current control circuit 320 includes a variable current source 321, nMOS transistors 322, 323, and 324, and pMOS transistors 325 and 326.

The variable current source 321 generates a current having a value indicated by the setting data. When controlling the current value statically, the setting data is held in, for example, a register (not shown). When dynamically controlling the current value, setting data is supplied from a predetermined setting circuit (not shown) that generates setting data depending on the operation mode and the like.

The sources of nMOS transistors 322, 323, and 324 are commonly connected to a ground node. Further, the gate and drain of the nMOS transistor 322 are short-circuited, and the drain is connected to the variable current source 321. The gate of nMOS transistor 323 is connected to the gate of nMOS transistor 322, and the drain is connected to pMOS transistor 325.

The gate of the nMOS transistor 324 is connected to the gate of the nMOS transistor 322, and the drain is connected to a mirror source transistor (not shown) in a current mirror 440 on the power supply side via a selection switch 431.

The sources of pMOS transistors 325 and 326 are commonly connected to a ground node. Furthermore, the gate and drain of the pMOS transistor 325 are short-circuited. The gate of the pMOS transistor 326 is connected to the gate of the pMOS transistor 325, and the drain is connected to a mirror source transistor (not shown) in a current mirror 460 on the ground side via a selection switch 432.

In the circuit illustrated in the figure, by changing the current value of the variable current source using setting data, each of the reference currents Iref1 and Iref2 can be adjusted according to the value.

Here, as a first comparative example, a configuration is assumed in which the drive capability of the drive circuit 400 is adjusted by connecting inverters in multiple stages and changing the number of stages.

FIG. 10 is a circuit diagram showing a configuration example of the drive circuit 400 in the first comparative example. The drive circuit 400 of the first comparative example includes M (M is an integer) NAND gates 415, M nMOS transistors 452, M NOR gates 416, and M pMOS transistors 451. Be prepared.

A drive signal TRG1 is input to the input terminals of M NAND gates 415 and M NOR gates 416. A circuit that generates this drive signal is omitted.

The switching signal selm is input to the m-th (m is an integer from 1 to M) NAND gate 415, and the switching signal xselm obtained by inverting selm is input to the m-th NOR gate 416. The NAND gate 415 at each stage supplies the NAND of the drive signal TRG1 and the corresponding switching signal selm to the gate of the m-th nMOS transistor 452. The NOR gate 416 at each stage supplies the NOR of the drive signal TRG1 and the corresponding switching signal xselm to the gate of the m-th pMOS transistor 451.

The sources of the M nMOS transistors 452 are commonly connected to a power supply node, and the sources of the M pMOS transistors 451 are commonly connected to a ground node. Further, the drains of the M nMOS transistors 452 and the drains of the M pMOS transistors 451 are connected to a common output node, and the drive signal TRG1 is output from that node.

The driver consisting of the m-th nMOS transistor 452 and the pMOS transistor 451 can be enabled or disabled by the switching signals selm and xselm. Thereby, the number of driver stages can be changed and the driving ability of the driving circuit 400 can be adjusted. Increasing the drive capability improves the frame rate, but on the other hand, pixel noise components such as charge injection increase. On the other hand, if the driving ability is lowered, the pixel noise component will be reduced, but the frame rate will be lowered.The driving ability is adjusted in consideration of this trade-off.

However, in the circuit configuration illustrated in the figure, the wider the variable range of the driving capability, the larger the circuit scale. For example, when the number of driver stages is switchable from one stage to four stages, the circuit size becomes twice as large as that when the number of driver stages can be switched up to two stages.

On the other hand, in a configuration in which the drive capacity is adjusted by controlling the current value of the reference value, there is no need to increase the number of inverter stages when widening the variable range of the drive capacity, thereby suppressing the increase in circuit size. be able to.

[Example of configuration of column signal processing circuit]
FIG. 11 is a circuit diagram showing a configuration example of the column signal processing circuit 250 in the first embodiment of the present technology. This column signal processing circuit 250 includes a plurality of ADCs 251 and a digital signal processing section 252. ADC 251 is arranged for each column.

Analog pixel signals from the corresponding columns are input to the ADC 251 via the vertical signal line 219. This ADC 251 converts the pixel signal into a digital signal and supplies it to the digital signal processing section 252.

The digital signal processing unit 252 performs various signal processing such as CDS processing as necessary on image data in which digital signals are arranged. The digital signal processing unit 252 then outputs the processed image data to the DSP circuit 120.

[Operation example of solid-state image sensor]
FIG. 12 is a timing chart showing an example of the operation of the solid-state image sensor 200 in the first embodiment of the present technology. After timing T0, the vertical scanning circuit 300 sequentially selects rows and starts exposure. Then, between timings T1 and T2, the vertical scanning circuit 300 sequentially selects rows, finishes exposure, and outputs pixel signals.

For example, the vertical scanning circuit 300 outputs the high-level selection signal SEL1 to the first row over the selection period from timing T1 to T12. Further, the vertical scanning circuit 300 outputs a high-level drive signal RST1 to the first row from timing T1 over the pulse period, and outputs a high-level drive signal TRG1 to the first row from timing T11 within the selection period over the pulse period. Output on one line. The pixels in the first row are initialized by the drive signal RST1, and immediately after that, the reset level is read by the ADC 251. Signal charges are transferred in the pixels of the first row by the drive signal TRG1, and immediately after that, the signal level is read by the ADC 251.

Over the selection period from timing T12 to T13, the vertical scanning circuit 300 outputs a high-level selection signal SEL2 to the second row, and outputs a drive signal to the second row within that period. Thereafter, the vertical scanning circuit 300 sequentially selects rows up to the Nth row and performs similar control.

FIG. 13 is a diagram illustrating an example of the state of the drive circuit of each row when driving the first row in the first embodiment of the present technology. When driving the first row, only the selection signal SEL1 is set to high level, and the selection signals SEL2 to SELN are set to low level. These selection signals turn on only the selection switches 431 and 432 in the first row, and current is supplied only to the driver 450 in the first row. Then, the first row driver 450 outputs the drive signal TRG1 to the first row.

FIG. 14 is a diagram illustrating an example of the state of the drive circuit of each row when driving the second row in the first embodiment of the present technology. Immediately after driving the first row, only the selection signal SEL2 is set to high level, and the other selection signals are set to low level. These selection signals turn on only the selection switches 431 and 432 in the second row, and current is supplied only to the driver 450 in the second row. Then, the second row driver 450 outputs the drive signal TRG2 to the second row.

Hereinafter, similar control is repeatedly executed from the third line onwards.

FIG. 15 is a diagram illustrating an example of the state of the drive circuit of each row when driving the last row in the first embodiment of the present technology. Immediately after driving the N-1th row, only the selection signal SELN is set to high level, and the other selection signals are set to low level. These selection signals turn on only the selection switches 431 and 432 in the Nth row, and current is supplied only to the driver 450 in the Nth row. Then, the driver 450 in the Nth row outputs the drive signal TRGN to the Nth row.

As illustrated in FIGS. 13 to 15, only the selection switches 431 and 432 of the row to be driven are turned on in synchronization with the selection signal, and current is supplied only to the driver 450 to be driven. Thereby, power consumption can be reduced compared to the case where current is supplied to the drivers 450 of all rows. Note that if low power consumption is not required, the selection switches 431 and 432 may not be arranged for each row, and the current mirrors 440 and 460 of all rows may be directly connected to the current control circuit 320.

As described above, according to the first embodiment of the present technology, the drive capacity is adjusted by controlling the reference current values of the current mirrors 440 and 460, so compared to the first comparative example in which the number of driver stages is changed. This makes it possible to suppress an increase in circuit scale.

<2. Second embodiment>
In the first embodiment described above, the mirror source transistors 441 and 461 are arranged for each row, but the number of these transistors can also be reduced. The solid-state imaging device 200 in this second embodiment differs from the first embodiment in that mirror source transistors 441 and 461 are shared by a plurality of rows.

FIG. 16 is a block diagram showing a configuration example of the solid-state image sensor 200 in the second embodiment of the present technology. The solid-state imaging device 200 of this second embodiment differs from the first embodiment in that it further includes a column signal processing circuit 240.

In the column signal processing circuit 240, ADCs are arranged for each column similarly to the column signal processing circuit 250. Further, in the pixel array section 210 of the second embodiment, vertical signal lines 218 and 219 are wired for each column. Half of all the rows (odd rows, etc.) are connected to the column signal processing circuit 240 via the vertical signal line 218, and the remaining half (even rows, etc.) are connected to the column signal processing circuit 250 via the vertical signal line 219. Connected. In this way, since two ADCs are arranged for each column, the vertical scanning circuit 300 drives two rows simultaneously, and the column signal processing circuits 240 and 250 simultaneously AD convert the pixel signals of the two rows. (In other words, read out).

Note that the ADC in the column signal processing circuit 240 is an example of the first ADC described in the claims, and the ADC in the column signal processing circuit 250 is an example of the second ADC described in the claims. This is an example.

FIG. 17 is a circuit diagram showing a configuration example of a drive circuit in the second embodiment of the present technology. In this second embodiment, drive circuits 400, 500, and 600 that output TRG, RST, and SEL are connected to odd rows. Furthermore, drive circuits 700, 800, and 900 that output TRG, RST, and SEL are connected to even-numbered rows.

The drive circuit 700 includes mirror destination transistors 742 and 762 and a driver 750. Mirror destination transistor 742 is inserted between the power supply terminal of driver 750 and the power supply node, and mirror destination transistor 762 is inserted between the ground terminal of driver 750 and the ground node.

The circuit configuration of the drive circuit 400 of the second embodiment is the same as that of the first embodiment. However, the gate of the mirror source transistor 441 is also connected to the gate of the mirror destination transistor 742. Further, the gate of the mirror source transistor 461 is also connected to the gate of the mirror destination transistor 762. The control signal xTRG is also input to the input terminal of the driver 750.

Note that the drivers 450 and 750 are examples of the first and second drivers described in the claims. Mirror destination transistors 442 and 462 are examples of first mirror destination transistors described in the claims. Mirror destination transistors 742 and 762 are examples of second mirror destination transistors described in the claims.

As illustrated in the figure, the mirror destination transistors are arranged for each row, and the mirror source transistors are shared by two rows. Thereby, the circuit scale of the vertical scanning circuit 300 can be reduced compared to the first embodiment in which mirror source transistors are arranged for each row.

Note that mirror destination transistors and drivers are similarly arranged in the drive circuits 800 and 900, and are connected to the mirror source transistors of the drive circuits 500 and 600.

Furthermore, although two rows share a mirror source transistor, it is also possible to arrange three or more ADCs in each column and share a mirror source transistor among three or more rows.

In this way, according to the second embodiment of the present technology, the mirror source transistors are shared by multiple rows, so the circuit scale of the vertical scanning circuit 300 can be reduced.

<3. Third embodiment>
In the first embodiment described above, the mirror source transistors 441 and 461 are arranged for each row, but in this configuration, when the amount of power fluctuation is different between the current control circuit 320 and the mirror source transistor, The amount of current may vary from row to row. The solid-state imaging device 200 in the third embodiment differs from the first embodiment in that a mirror source transistor is placed within the current control circuit 320, and a sample and hold circuit is added for each row.

FIG. 18 is a circuit diagram showing a configuration example of the drive circuit 400 and the current control circuit 350 in the third embodiment of the present technology. The drive circuit 400 includes a control signal generation section 470, sample and hold circuits 480 and 490, and a driver 450.

The driver 450 includes a pMOS transistor 451 and an nMOS transistor 452. These transistors are inserted in series between the power supply node and the ground node, and the drive signal TRG is output from these connection nodes to the corresponding row in the pixel array section 210.

The control signal generation unit 470 generates control signals SW1, SW2, SW3, and SW4. Control signals SW1 and SW2 are supplied to sample and hold circuit 480, and control signals SW3 and SW4 are supplied to sample and hold circuit 490.

The sample hold circuit 480 includes a sample switch 481, a short circuit switch 482, and a capacitive element 483.

The sample switch 481 opens and closes the path between the current control circuit 350 and the gate of the pMOS transistor 451 according to the control signal SW1. The short-circuit switch 482 opens and closes a path between the power supply side terminal and the ground side terminal of the capacitive element 483 in accordance with the control signal SW2. Capacitive element 483 is inserted between the gate and source of pMOS transistor 451.

The sample and hold circuit 490 includes a sample switch 491, a short circuit switch 492, and a capacitive element 493.

The sample switch 491 opens and closes the path between the current control circuit 350 and the gate of the nMOS transistor 452 according to the control signal SW3. The short-circuit switch 492 opens and closes a path between the power supply side terminal and the ground side terminal of the capacitive element 493 in accordance with the control signal SW4. Capacitive element 493 is inserted between the gate and source of nMOS transistor 452.

The current control circuit 350 includes variable current sources 351 and 352, a pMOS transistor 353, and an nMOS transistor 354.

The variable current source 351 is inserted between the power supply node and the drain of the nMOS transistor 354, and the variable current source 352 is inserted between the ground node and the drain of the pMOS transistor 353.

The source of the pMOS transistor 353 is connected to the power supply node, and the gate and drain are short-circuited. Further, the gate of the pMOS transistor 353 is connected to the gate of the pMOS transistor 451 via a sample switch 481.

The source of the nMOS transistor 354 is connected to the ground node, and the gate and drain are short-circuited. Further, the gate of the nMOS transistor 354 is connected to the gate of the nMOS transistor 452 via a sample switch 491.

The configurations of other drive circuits such as drive circuit 500 are similar to drive circuit 400.

With the connection configuration illustrated in the figure, the pMOS transistor 353 common to each row and the pMOS transistor 451 in each row constitute a current mirror on the power supply side. The pMOS transistor 353 functions as a mirror source transistor of a current mirror, and allows the reference current generated by the variable current source 352 to flow. The pMOS transistor 451 functions as a mirror destination transistor of a current mirror, and generates an output current according to a reference current.

Furthermore, the nMOS transistor 354 common to each row and the nMOS transistor 452 in each row constitute a current mirror on the ground side. The nMOS transistor 354 functions as a mirror source transistor of a current mirror, and allows the reference current generated by the variable current source 351 to flow. The nMOS transistor 452 functions as a mirror destination transistor of a current mirror, and generates an output current according to the reference current.

Note that the pMOS transistor 353 and the nMOS transistor 354 are examples of mirror source transistors described in the claims. Further, the pMOS transistor 451 and the nMOS transistor 452 are examples of mirror destination transistors described in the claims.

Furthermore, a pMOS transistor 451 and an nMOS transistor 452, which are mirror destinations of the current mirrors on the power supply side and the ground side, constitute a driver 450, and output a drive signal TRG, which is a voltage signal, from the drain.

Here, a configuration without current control circuit 350 and sample and hold circuits 480 and 490 is assumed as a second comparative example.

FIG. 19 is a diagram illustrating an example of a drive circuit and operation in a second comparative example. As illustrated in a in the figure, in the second comparative example, power is supplied to each driver (driver 450, etc.) via a package terminal 911, a power supply pad 912, and a power supply wiring 913. The symbol a for resistance in the figure indicates the impedance of the wiring or interposer.

The further away from the power supply pad 912, the higher the wiring impedance of the power supply wiring 913 becomes, and as illustrated in b in the figure, the power supply pad current flows through the driver, and this current causes an IR drop, causing a large fluctuation in the power supply pad voltage. . This fluctuation causes the transistors in the driver to temporarily become inoperable. Therefore, it takes time for the signal to rise and fall, and the output waveform becomes distorted with respect to the input signal of the driver.

In order to operate pixels correctly, there is a criterion that ``a certain voltage or more must be supplied for a certain period of time.'' As shown in b in the same figure, there is a way to satisfy the criteria even when the output waveform is distorted, by increasing the pulse width of the input signal, but in that case, the time required for AD conversion is longer. This is not desirable because it becomes

In order to meet the criteria without changing the pulse width of the input signal, it is necessary to shorten the rise and fall times. To this end, it is effective to reduce the internal impedance and reduce the IR drop. . One method for reducing internal impedance is to increase the width of the power supply wiring, but in this case, in the second comparative example, the circuit area increases.

On the other hand, in the circuit configuration illustrated in FIG. 18, by changing the current values of the variable current sources 351 and 352, the current values of the reference currents of the current mirrors on the power supply side and the ground side can be controlled. can. By controlling the current value, power fluctuations due to IR drop can be suppressed. By suppressing the IR drop, it is possible to narrow the wiring width of the signal line connected to the power supply node and the ground node, so that even if the wiring impedance increases, the drive capability is not affected. Therefore, the circuit scale of the drive circuit 400 and the like can be reduced without significantly increasing power consumption or reducing drive capability.

Further, the sample and hold circuit 480 holds the voltage between the gate and source of the pMOS transistor 451 in synchronization with the control signal SW1. The sample and hold circuit 490 holds the voltage between the gate and source of the nMOS transistor 452 in synchronization with the control signal SW3.

These sample and hold circuits maintain the gate-source voltage constant even if the respective source voltages (power supply voltage or ground voltage) of the pMOS transistor 451 and the nMOS transistor 452 fluctuate, suppressing fluctuations in drive capability. be able to.

FIG. 20 is a timing chart showing an example of the operation of the drive circuit 400 in the third embodiment of the present technology.

The control signal generation section 470 supplies the high-level control signal SW1 over the pulse period from timing T0 to T1. Furthermore, the control signal generation section 470 sets the control signal SW2 to a low level over a period from timing T0 to T2. Outside this period, the control signal SW2 is controlled to a high level. Even if the sample switch 481 is turned off at timing T1 and the power supply voltage VDD fluctuates, the gate voltage Vpg of the pMOS transistor 451 also fluctuates to the same extent due to the connection of the capacitive element 483. Therefore, the gate-source voltage of the pMOS transistor 451 becomes constant, and fluctuations in the power supply voltage do not affect the driving ability.

Then, the control signal generation section 470 supplies a high-level control signal SW3 over the pulse period from timing T2 to T3. Further, the control signal generation unit 470 sets the control signal SW4 to a high level over the period from timing T0 to timing T2. Outside this period, control signal SW4 is controlled to low level. Even if the sample switch 491 is turned off at timing T3 and the ground voltage VRL fluctuates, the gate voltage Vng of the nMOS transistor 452 fluctuates to the same extent due to the connection of the capacitive element 493. Therefore, the gate-source voltage of the nMOS transistor 452 becomes constant, and fluctuations in the ground voltage do not affect the driving ability.

Furthermore, the driver 450 outputs the drive signal TRG1 within the period from timing T0 to timing T2.

FIG. 21 is a diagram for explaining the effects of the third embodiment of the present technology. In the same figure, a shows the layout of the drive unit 330 of the second comparative example, and b in the same figure shows the layout of the drive unit 330 of the third embodiment.

As illustrated in a in the figure, in the second comparative example, the power supply wiring 913 is thick and its area is large. In contrast, in the third embodiment, as illustrated in b in the figure, the area of the power supply wiring 913 can be reduced.

As described above, according to the third embodiment of the present technology, the sample and hold circuits 480 and 490 hold the gate-source voltage of the mirror destination transistor, so even if the power supply voltage or the ground voltage fluctuates, the sample and hold circuits 480 and 490 can be driven. ability can be maintained.

Note that the above-described embodiments show an example for embodying the present technology, and the matters in the embodiments and the matters specifying the invention in the claims have a corresponding relationship, respectively. Similarly, the matters specifying the invention in the claims and the matters in the embodiments of the present technology having the same names have a corresponding relationship. However, the present technology is not limited to the embodiments, and can be realized by making various modifications to the embodiments without departing from the gist thereof.

Note that the effects described in this specification are merely examples and are not limiting, and other effects may also exist.

Note that the present technology can also have the following configuration.
(1) A driver that outputs a predetermined drive signal from an output terminal;
a current mirror that generates an output current according to a predetermined reference current and flows it to at least one of a power supply side and a ground side of the driver;
A solid-state imaging device comprising: a current control circuit that controls a current value of the reference current.
(2) The solid-state imaging device according to (1), further comprising a pixel array section in which a plurality of pixels that generate analog signals in accordance with the drive signal are arranged in a two-dimensional grid.
(3) the driver and the current mirror are arranged for each row in the pixel array section;
The current mirror is
a mirror source transistor through which the reference current flows;
The solid-state imaging device according to (2) above, further comprising a mirror-end transistor that generates the output current.
(4) The current mirror is
a mirror source transistor through which the reference current flows;
first and second mirror destination transistors that share the mirror source transistor and generate the output current;
the driver includes first and second drivers;
the first driver outputs the output current to a first row in the pixel array section;
the second driver outputs the output current to a second row in the pixel array section;
the first mirror destination transistor passes the output current to the first driver;
The solid-state imaging device according to (2), wherein the second mirror destination transistor causes the output current to flow through the second driver.
(5) a first analog-to-digital converter that converts the analog signal from the first row into a digital signal;
further comprising a second analog-to-digital converter that converts the analog signal from the second row into a digital signal,
The solid-state imaging device according to (4), wherein the first and second drivers simultaneously supply the output current.
(6) The solid-state imaging device according to any one of (1) to (5), further comprising a selection switch that opens and closes a path between the current mirror and the current control circuit in synchronization with a predetermined selection signal. .
(7) a logic gate that generates and outputs the selection signal;
The solid-state imaging device according to (6), further comprising a latch circuit that holds the output selection signal and supplies it to the selection switch.
(8) the output current includes first and second output currents;
The current mirror is
a power supply side current mirror that causes the first output current to flow from the power supply node to the power supply terminal of the driver;
The solid-state image sensor according to any one of (1) to (7), including a ground side current mirror that causes the second output current to flow from the ground terminal of the driver to the ground node.
(9) a variable current source;
a mirror source transistor through which a reference current generated by the variable current source flows;
a mirror destination transistor that generates an output current according to the reference current and outputs a voltage signal from its drain;
A solid-state image pickup device comprising a sample and hold circuit that samples and holds a voltage between the gate and source of the mirror destination transistor in synchronization with a predetermined control signal.
(10) a driver that outputs a predetermined drive signal from an output terminal;
a current mirror that generates an output current according to a predetermined reference current and flows it to at least one of a power supply side and a ground side of the driver;
a current control circuit that controls the current value of the reference current;
a plurality of pixels that generate analog signals according to the drive signal;
An imaging device comprising: a signal processing circuit that performs predetermined signal processing on the analog signal.

100 Imaging device 110 Optical section 120 DSP circuit 130 Display section 140 Operation section 150 Bus 160 Frame memory 170 Storage section 180 Power supply section 200 Solid-state image sensor 210 Pixel array section 220 Pixel 221 Photoelectric conversion element 222 Transfer transistor 223 Reset transistor 224 Floating diffusion layer 225 Amplification transistor 226 Selection transistor 230 Timing control circuit 240, 250 Column signal processing circuit 251 ADC
252 Digital signal processing section 300 Vertical scanning circuit 310 Decoder 320, 350 Current control circuit 321, 351, 352 Variable current source 322 to 324, 354, 452 NMOS transistor 325, 326, 353, 451 PMOS transistor 330 Drive section 400, 500, 600, 700, 800, 900 Drive circuit 410 Selection signal generation section 411 Logic gate 412 Latch circuit 415 NAND (Negated OR) gate 416 NOR (Negated OR) gate 420, 470, 520 Control signal generation section 431, 432, 531 , 532, 631, 632 Selection switch 440, 460, 540, 560, 640, 660 Current mirror 441, 461 Mirror source transistor 442, 462, 742, 762 Mirror destination transistor 450, 550, 650, 750 Driver 480, 490 Sample hold Circuit 481, 491 Sample switch 482, 492 Short circuit switch 483, 493 Capacitive element

Claims (10)

1. a driver that outputs a predetermined drive signal from an output terminal;
   a current mirror that generates an output current according to a predetermined reference current and flows it to at least one of a power supply side and a ground side of the driver;
   A solid-state imaging device comprising: a current control circuit that controls a current value of the reference current.
2. 2. The solid-state image sensor according to claim 1, further comprising a pixel array section in which a plurality of pixels that generate analog signals in accordance with the drive signal are arranged in a two-dimensional grid.
3. The driver and the current mirror are arranged for each row in the pixel array section,
   The current mirror is
   a mirror source transistor through which the reference current flows;
   The solid-state image sensor according to claim 2, further comprising a mirror-end transistor that generates the output current.
4. The current mirror is
   a mirror source transistor through which the reference current flows;
   first and second mirror destination transistors that share the mirror source transistor and generate the output current;
   the driver includes first and second drivers;
   the first driver outputs the output current to a first row in the pixel array section;
   the second driver outputs the output current to a second row in the pixel array section;
   the first mirror destination transistor passes the output current to the first driver;
   3. The solid-state image sensor according to claim 2, wherein the second mirror destination transistor causes the output current to flow through the second driver.
5. a first analog-to-digital converter for converting analog signals from the first row into digital signals;
   further comprising a second analog-to-digital converter that converts the analog signal from the second row into a digital signal,
   The solid-state imaging device according to claim 4, wherein the first and second drivers simultaneously supply the output current.
6. 2. The solid-state imaging device according to claim 1, further comprising a selection switch that opens and closes a path between the current mirror and the current control circuit in synchronization with a predetermined selection signal.
7. a logic gate that generates and outputs the selection signal;
   7. The solid-state imaging device according to claim 6, further comprising a latch circuit that holds the output selection signal and supplies it to the selection switch.
8. the output current includes first and second output currents,
   The current mirror is
   a power supply side current mirror that causes the first output current to flow from the power supply node to the power supply terminal of the driver;
   2. The solid-state image sensor according to claim 1, further comprising a ground-side current mirror that causes the second output current to flow from the ground terminal of the driver to the ground node.
9. a variable current source;
   a mirror source transistor through which a reference current generated by the variable current source flows;
   a mirror destination transistor that generates an output current according to the reference current and outputs a voltage signal from its drain;
   A solid-state imaging device comprising a sample and hold circuit that samples and holds a voltage between the gate and source of the mirror destination transistor in synchronization with a predetermined control signal.
10. a driver that outputs a predetermined drive signal from an output terminal;
    a current mirror that generates an output current according to a predetermined reference current and flows it to at least one of a power supply side and a ground side of the driver;
    a current control circuit that controls the current value of the reference current;
    a plurality of pixels that generate analog signals according to the drive signal;
    An imaging device comprising: a signal processing circuit that performs predetermined signal processing on the analog signal.

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