JP4501524B2 - Ceramic multilayer substrate and manufacturing method thereof - Google Patents

Description

  The present invention relates to a ceramic multilayer substrate and a method for manufacturing the same, and more particularly, to a ceramic multilayer substrate with a built-in chip type electronic component, in which a chip type electronic component is accommodated in a through hole provided in the ceramic multilayer substrate, and a method for manufacturing the same. Is.

  In order to increase the density and functionality of electronic circuits used in wireless communication devices, engine control units, and the like, a ceramic multilayer substrate incorporating passive elements such as capacitors and inductors is desired.

  In general, a ceramic multilayer substrate is obtained by printing a conductive paste on a ceramic green sheet to form a conductor pattern to be a capacitor or an inductor, and then laminating and firing the ceramic green sheet. However, in this method, since the types of ceramic green sheets that can be used are limited, it is difficult to form a large-capacity capacitor, an inductor having a high Q value, and the like in the multilayer substrate.

  Therefore, Patent Document 1 and Patent Document 2 disclose a chip-type electronic component built-in ceramic multilayer substrate in which a chip-type electronic component such as a chip-type multilayer ceramic capacitor is housed in a space formed in the ceramic multilayer substrate. . According to such a ceramic multilayer substrate, for example, a chip-type multilayer ceramic capacitor having a large capacity or excellent temperature characteristics can be built in as a capacitor. Is easy.

However, the chip-type electronic component built-in ceramic multilayer substrate disclosed in Patent Document 1 is obtained by embedding a fired chip-type multilayer ceramic capacitor in the through hole of the ceramic green sheet and integrally firing the ceramic multilayer substrate. During the firing, the chip-type multilayer ceramic capacitor does not shrink, but the ceramic green sheet shrinks both in the plane direction and in the thickness direction. In some cases, sufficient electrical connection with the chip-type electronic component could not be obtained.
Japanese Patent Publication No. 6-32378 Japanese Patent Laid-Open No. 2003-332741

  On the other hand, as shown in FIGS. 4A and 4B, the chip-type electronic component built-in ceramic multilayer substrate disclosed in Patent Document 2 is a first ceramic that can be fired simultaneously with a conductive material such as silver or copper. It is obtained by firing a ceramic laminate 31a formed by alternately laminating green sheets 32a and second ceramic green sheets 33a that can suppress firing shrinkage in the planar direction of the ceramic green sheets 32a. Since the ceramic laminate 31a is restrained by the second ceramic green sheet 33a during firing, the ceramic laminate 31a does not substantially shrink in the planar direction. That is, neither the chip-type electronic component 41 built in the space 35 of the ceramic laminate 31a nor the first ceramic green sheet 32a constituting the ceramic laminate 31a substantially shrinks in the plane direction. Cracks are unlikely to occur between the ceramic layer 32 and the chip-type electronic component 41, and the electrical connection between the land conductor 34 provided on the bottom surface of the space 35 and the terminal electrode 42 provided on the end surface of the chip-type electronic component 41. Connection reliability is high.

  However, when the ceramic laminate 31a is fired, the ceramic laminate 31a does not substantially contract in the plane direction, but greatly contracts in the thickness direction. That is, according to the manufacturing method of the chip-type electronic component built-in ceramic multilayer substrate disclosed in Patent Document 2, the entire periphery of the chip-type electronic component 41 is surrounded by the first ceramic layer 32 and the second ceramic layer 33. Therefore, stress is generated between the ceramic layer 33 above and below the space 35 and the upper and lower surfaces of the chip-type electronic component 41, and cracks may occur at the upper interface 51 and the lower interface 52.

  Further, a predetermined conductor pattern (not shown) is formed above and below the space 35 in which the chip-type electronic component 41 is disposed. Usually, in order to ensure the degree of freedom of circuit design in the ceramic multilayer substrate 31, The wiring density of the conductor pattern is not symmetrical vertically. That is, since the wiring density of the conductor pattern is generally asymmetrical in the upper and lower sides of the chip-type electronic component 41, there is a difference in the shrinkage behavior of the ceramic green sheet between the vicinity of the upper interface 51 and the vicinity of the lower interface 52. Cracks may occur in the part.

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a ceramic multilayer substrate that is resistant to cracks and the like and that has high electrical connection reliability while accommodating chip-type electronic components. And providing a manufacturing method thereof.

That is, according to the present invention, a plurality of ceramic layers are laminated, and a ceramic laminate including a through hole penetrating the upper and lower main surfaces thereof, and a side conductor exposed on a side surface of the through hole, and the through hole is accommodated, wherein the side conductor to the external terminal connected to have that chip-type electronic component is configured to include a, a ceramic multilayer substrate wherein the side conductor and said external terminals that are connected directly are fired integrally It is related.

  Further, the present invention is a process for producing a green ceramic laminate comprising a plurality of green ceramic layers laminated, a through hole penetrating the upper and lower main surfaces, and a side conductor exposed on a side surface of the through hole. A step of accommodating a chip-type electronic component in the through hole of the green ceramic laminate so that the external terminal is connected to the side conductor, and the green ceramic laminate at a sintering temperature of the green ceramic layer. A method of manufacturing a ceramic multilayer substrate having a firing step.

According to the ceramic multilayer substrate of the present invention, the chip-type electronic component is accommodated in the through-hole penetrating the upper and lower main surfaces of the ceramic laminate, and the external terminal of the chip-type electronic component is the side portion of the through-hole of the ceramic laminate. because it is directly connected is integrally sintered to the side surface conductor exposed to, Ru can secure high reliability of connection between the ceramic multilayer substrate and the chip-type electronic component without using solder. Further, since a structure in which the chip-type electronic component are exposed to the upper and lower main surfaces of the ceramic laminate, Ru can be suppressed stress remaining between the ceramic layer and the chip-type electronic component to a minimum. Therefore, it is possible to obtain a ceramic multilayer substrate that is less likely to generate cracks and has high reliability of electrical connection while accommodating chip-type electronic components.

  Further, according to the method for manufacturing a ceramic multilayer substrate of the present invention, the chip type electronic component is accommodated in the through hole penetrating the upper and lower main surfaces of the ceramic laminate, and the external terminal of the chip type electronic component is connected to the through hole of the ceramic laminate. Because it is connected to the side conductor exposed on the side surface, high connection reliability between the ceramic multilayer substrate and the chip-type electronic component can be secured, and the chip-type electronic component is exposed on the upper and lower main surfaces of the ceramic laminate. Therefore, the residual stress between the ceramic layer and the chip-type electronic component can be suppressed to a minimum. Therefore, cracks and the like are hardly generated while housing the chip-type electronic component, and the electric It is possible to manufacture a ceramic multilayer substrate with high reliability in connection with high reproducibility.

  Hereinafter, preferred embodiments of the present invention will be described.

  First, the ceramic multilayer substrate of this embodiment will be described with reference to FIGS. 1 and 2.

As shown in FIGS. 1 and 2, the ceramic multilayer substrate 1 of the present embodiment is based on a ceramic laminate 2 in which a plurality of ceramic layers 3 are laminated. A through hole 6 that penetrates the main surface 4 and the lower main surface 5 is provided. The through-hole 6 provided in the ceramic laminate 2 includes a side conductor 8 exposed on the side surface 7. The chip-type electronic component 15 is accommodated in the through-hole 6, and is formed on the end surface of the chip-type electronic component 15. The provided external terminal 16 is integrally fired with the side conductor 8 and is directly electrically connected.

  An upper surface conductor 9 is provided on the upper main surface 4 of the ceramic laminate 2, and the upper surface conductor 9 functions as a connection land with a surface mounting component (not shown) such as a semiconductor device. On the other hand, a lower surface conductor 10 is provided on the lower main surface 5 of the ceramic laminate 2, and the lower surface conductor 10 functions as a connection land with a mother board (not shown) such as a printed wiring board. . Furthermore, an inner conductor 11 disposed at the interface of the ceramic layer 3 and a via conductor 12 that vertically penetrates the ceramic layer are provided inside the ceramic laminate 2, and the inner conductor 11 and the via conductor 12 are provided. Various circuit patterns such as wiring, a ground pattern, a capacitor pattern, and an inductor pattern for forming a predetermined electric circuit are formed by the inner conductor pattern.

  Here, the chip-type electronic component 15 accommodated in the through hole 6 is a chip-type electronic component such as a chip-type multilayer ceramic capacitor, a chip-type multilayer ceramic inductor, or a chip-type multilayer LC filter, and more specifically, a ceramic sintered body. The chip-type ceramic electronic component that is an element body is housed so that all side surfaces of the rectangular chip-type electronic component are substantially in contact with the side surface of the rectangular through hole 6. More specifically, the two external terminals 16 provided on both end faces of the chip-type electronic component 15 are respectively connected to the two side conductors 8 exposed on the two opposite side faces 7 of the through hole 6. . Further, the other end surfaces of the chip-type electronic component 15 are in contact with the other two opposite side surfaces of the through hole 6. Note that a gap due to the thickness of the external terminal 16 may be formed between the chip-type electronic component 15 and the side surface of the through hole 6. Further, when there is a gap between the chip-type electronic component 15 and the side surface of the through hole 6, the connection reliability between the chip-type electronic component 15 and the ceramic laminate 2 can be further improved by providing a resin there. Can do.

  The side conductor 8 exposed on the side face 7 of the through hole 6 is formed by a via conductor provided in the ceramic layer 3. In other words, the side conductor 8 is formed by exposing a cross section of a via conductor penetrating the ceramic layer 3 in the vertical direction to the side face 7 of the through hole 6. 2 has a rectangular exposed surface having long pieces in the thickness direction, and has a structure in which a conductive material is filled in a groove portion extending over a plurality of ceramic layers. The side conductor 8 is electrically connected to an internal conductor provided inside the ceramic laminate 2 and is connected to the above-described internal conductor pattern. As described above, since the side conductor 8 is provided by the via conductor provided in the ceramic layer 3, a land electrode (in-plane pattern) for connecting to the external terminal 16 of the chip-type electronic component 15 is not required. The ceramic laminate 3 and the side conductor 8 can be firmly bonded to ensure high connection reliability.

  Both end portions of the side conductor 8 may be exposed on the upper main surface 4 and the lower main surface 5 of the ceramic laminate 2, but at least one end portion thereof, and further, both end portions thereof are the upper main surface. 4 and the lower main surface 5 are desirably exposed and remain in the ceramic laminate 2. That is, the height of the side conductor 8 (the length in the thickness direction of the ceramic laminate) is desirably smaller than the height of the through hole 6 (the length in the thickness direction of the ceramic laminate). The height of the side conductor 8 is preferably in the range of 20 to 90% with respect to the height of 6. By configuring the both ends of the side conductor 8 so as not to be exposed to the upper main surface 4 and the lower main surface 5, the side conductor 8 is less affected by the external environment, and connection reliability and environmental resistance are improved.

  In this embodiment, since the thickness of the chip-type electronic component 15 is substantially the same as the thickness of the ceramic laminate 2, the upper surface of the chip-type electronic component 15 and the upper main surface 4 of the ceramic laminate 2 constitute substantially the same surface. Thus, the lower surface of the chip-type electronic component 15 and the lower main surface 5 of the ceramic laminate 2 constitute substantially the same surface. However, the upper surface of the chip-type electronic component 15 may be lower than the upper main surface 4 of the ceramic laminate 2, and the lower surface of the chip-type electronic component 15 is higher than the lower main surface 5 of the ceramic laminate 2. May be. Alternatively, the upper surface of the chip-type electronic component 15 may be above the upper main surface 4 of the ceramic laminate 2.

Furthermore, the ceramic layer 3 may be formed of a ceramic material such as alumina or barium titanate, but is preferably formed of a low-temperature sintered ceramic material, and is further formed inside the ceramic laminate 2. The inner conductor pattern is preferably composed mainly of silver or copper. A conductor pattern mainly composed of silver or copper has a lower resistance than a refractory metal such as tungsten or molybdenum, and is particularly suitable for forming a circuit pattern for high frequency applications. Low temperature co-fired ceramic (LTCC) materials can be sintered at a firing temperature of 1000 ° C. or less and can be co-fired with silver, copper, and the like. Glass composite LTCC material obtained by mixing borosilicate glass with ceramic powder such as stellite, crystallized glass LTCC material using ZnO—MgO—Al ₂ O ₃ —SiO ₂ crystallized glass, BaO—Al Examples thereof include non-glass LTCC materials using ₂ O ₃ —SiO ₂ ceramic powder, Al ₂ O ₃ —CaO—SiO ₂ —MgO—B ₂ O ₃ ceramic powder, and the like.

  Next, the manufacturing method of the ceramic multilayer substrate of this embodiment is demonstrated based on FIG.

  First, as shown in FIG. 3A, a plurality of green ceramic layers 3a are laminated, a through hole 6 that penetrates the upper main surface 4 and the lower main surface 5, and a side surface 7a of the through hole 6 , 7b, a green ceramic laminate (unsintered ceramic laminate) 2a provided with side conductors 8a and 8b exposed to 7b is produced.

  Here, the upper surface conductor (not shown) described above is provided on the upper main surface 4 of the green ceramic laminate 2a, and the lower surface conductor (not shown) described above is provided on the lower main surface 5 of the ceramic laminate 2a. Furthermore, an internal conductor 11 disposed at the interface of the green ceramic layer 3a and a via conductor 12 vertically passing through the ceramic layer are provided inside the green ceramic laminate 2a. For example, when the green ceramic layer 3a is formed of the above-described low-temperature sintered ceramic material, the inner conductor pattern such as the inner conductor 11 and the via conductor 12 provided inside the green ceramic laminate 2a is mainly made of silver or copper. It can be formed of a metal material as a component.

  Next, as shown in FIG. 3B, the chip-type electronic component 15 is accommodated in the through hole 6 of the green ceramic laminate 2a so that the external terminals 16a and 16b are in contact with the side conductors 8a and 8b, respectively.

  At this time, it is desirable that a spacer such as a resin is disposed in advance in the through hole 6 so that the chip-type electronic component 15 is positioned in the center with respect to the height direction (thickness direction) of the through hole 6. Further, as described above, the side conductors 8a and 8b exposed on the side faces 7a and 7b of the through hole 6 are provided by via conductors provided in the green ceramic layer 3a. That is, the side conductors 8a and 8b are provided by exposing the cross section of the via conductor that vertically passes through at least one green ceramic layer of all the green ceramic layers 3a to the side face 7 of the through hole 6. is there. The chip-type electronic component 15 accommodated in the through-hole 6 is a chip-type ceramic electronic component having a ceramic sintered body as a base body, and the chip-type electronic component 15 is a through-hole having a rectangular shape on all sides. It is desirable that the chip-type electronic component 15 is stably accommodated in the through-hole 6 to be accommodated so as to substantially contact the side surface of 6. Further, since the chip-type electronic component 15 can be easily accommodated in the ceramic laminate 2a, it is desirable that the peripheral edge portion of the through hole 6 is rounded by roll brush polishing or the like.

  Next, as shown in FIG. 3 (C), the upper main surface 4 and the lower main surface 5 of the green ceramic laminate 2a containing the chip-type electronic component 16 are substantially at the sintering temperature of the green ceramic laminate 2a. For example, after the shrinkage suppression layers 21a and 21b mainly made of alumina or zirconia are provided, the green ceramic laminate 2a and the shrinkage suppression layers 21a and 21b are pressure-bonded.

  The shrinkage suppression layers 21a and 21b may be provided only on one of the upper main surface 4 and the lower main surface 5 of the green ceramic laminate 2a. In addition, there is a space between the upper and lower surfaces of the chip-type electronic component 16 and the shrinkage suppression layers 21a and 21b. If a filler such as a resin is provided in advance in this space, the shrinkage suppression layer 21a, It is easy to apply pressure uniformly to the entire surface of 21b, and the shrinkage suppression layers 21a and 21b can be prevented from having non-uniform stress. Or in order to prevent that the shrinkage | contraction suppression layers 21a and 21b have a nonuniform stress, an opening part can also be formed in the part corresponding to the through-hole 6 of the green ceramic laminated body 2a.

  Next, as shown in FIG. 3D, the green ceramic laminate 2a containing the chip-type electronic component 16 is fired together with the shrinkage suppression layers 21a and 21b at the sintering temperature of the green ceramic layer 3a as the base material. . That is, since the upper main surface 4 and the lower main surface 5 of the green ceramic laminate 2a are provided with shrinkage suppression layers 21a and 21b that are not substantially sintered at the sintering temperature of the green ceramic laminate 2a, respectively. Due to the restraining force of the shrinkage suppression layers 21a and 21b, the green ceramic laminate 2a is not substantially shrunk in the plane direction, and the ceramic multilayer substrate 2 having excellent dimensional accuracy in the plane direction is obtained.

  Next, as shown in FIG. 3E, the ceramic multilayer substrate 2 is taken out by peeling and removing the shrinkage suppression layers 21a and 21b by various means such as a wet honing method and a sand blast method. In addition, each shrinkage | contraction suppression layer 21a, 21b after baking exists as a porous layer which consists of an unsintered ceramic powder, and can be easily removed by the said means.

  According to the ceramic multilayer substrate and the manufacturing method thereof according to the above-described embodiment, since the green ceramic laminate 2a does not substantially contract in the plane direction during firing, the green ceramic body is formed on the fired ceramic multilayer substrate 2. 2a and the chip-type electronic component 15 are not cracked due to inconsistent contraction behavior, and the terminal electrodes 16a and 16b of the chip-type electronic component 15 are connected to the side conductors 8a and 8b in the through hole 6. It is less susceptible to shrinkage behavior and does not impair connection reliability. Further, the green ceramic laminate 2a does not substantially contract in the plane direction, but greatly contracts in the thickness direction. However, the chip-type electronic component 15 is inserted into the through hole 6 penetrating the green ceramic laminate 2a. Since it is accommodated, stress generated between the chip-type electronic component 15 and the green ceramic laminate 2a does not occur between the upper and lower surfaces of the chip-type electronic component 15 and the green ceramic laminate 2a. Therefore, it is possible to obtain a ceramic multilayer substrate in which cracks and the like are hardly generated and the reliability of electrical connection is high while accommodating chip-type electronic components. Furthermore, since the ceramic layer is not provided above and below the through hole 6, the ceramic multilayer substrate can be reduced in height, and a chip-type electronic component-containing multilayer substrate having a thickness of 300 μm or less and further a thickness of 200 μm or less is obtained. Can do.

  As described above, according to the ceramic multilayer substrate and the manufacturing method thereof of the present invention, a ceramic multilayer substrate that is less likely to generate cracks and has high reliability in electrical connection can be obtained. For example, a wireless communication device, an engine control unit, etc. Thus, it is suitably used as a multilayer substrate for various electronic circuits.

  Although the preferred embodiments of the ceramic multilayer substrate and the manufacturing method thereof of the present invention have been described above, the ceramic multilayer substrate and the manufacturing method of the present invention are not limited to the above-described configuration.

  For example, in the method for manufacturing a ceramic multilayer substrate described above, the shrinkage suppression layers are provided on both main surfaces of the green ceramic laminate, but the shrinkage suppression layers may be formed at the interfaces of the green ceramic layers. That is, the green ceramic laminate is formed by alternately stacking a green ceramic layer and a shrinkage suppression layer as a base material, and chip-type electronic components are accommodated in through holes that penetrate the upper and lower main surfaces of the green ceramic laminate. Also, by firing this, a ceramic multilayer substrate with built-in chip-type electronic components can be obtained. In this case, inorganic powder constituting the shrinkage suppression layer (specifically, ceramic powder that does not substantially sinter at the sintering temperature of the green ceramic layer) is fixed by the glass that has oozed from each green ceramic layer during firing. Therefore, the shrinkage suppression layer becomes dense and becomes a part of the ceramic multilayer substrate. Alternatively, if the shrinkage ratio in the planar direction of the green ceramic laminate and the shrinkage ratio in the planar direction of the chip-type electronic component are substantially the same, a ceramic multilayer substrate with built-in chip-type electronic components can be obtained without using the shrinkage suppression layer. Is also possible.

The method for producing a ceramic multilayer substrate obtained by the above mentioned, the green ceramic laminate is not substantially shrunk in the plane direction, in the vicinity of the central portion of the thickness direction of the laminate, although small but shrinks. That is, the opening area of the green ceramic laminate and the area of the upper and lower main surfaces of the chip-type electronic component are substantially the same, and the ceramic laminate can be utilized without using a bonding material such as solder by utilizing the slight shrinkage. it is possible to connect the external terminal 16 of the second side surface conductor 8 and the chip-type electronic component 15.

  Hereinafter, specific examples of the present invention will be described.

First, ceramic green sheets mainly made of low-temperature sintered ceramic materials (ceramic green sheets for substrate layers), and ceramic green sheets that do not substantially sinter at the temperature at which the low-temperature sintered ceramic materials are sintered (shrinkage suppression) Layer ceramic green sheet). In addition, the ceramic green sheet for the base material layer is obtained by adding 48 parts by weight of Ca—Al—B—Si—O-based glass powder to 52 parts by weight of Al ₂ O ₃ ceramic powder, and further, polyvinyl butyral as a binder. A ceramic slurry formed by mixing 10 parts by weight of a binder, 50 parts by weight of toluene and ethanol as solvents, and 3 parts by weight of DOP as a plasticizer was formed into a sheet having a thickness of 50 μm by a doctor blade method. It is cut into □. The ceramic green sheet for shrinkage suppression layer is made of 100 parts by weight of Al ₂ O ₃ ceramic powder, 10 parts by weight of polyvinyl butyral binder as binder, 50 parts by weight of toluene and ethanol as solvent, and DOP as plasticizer. A ceramic slurry obtained by mixing 3 parts by weight of this is formed into a sheet having a thickness of 100 μm by the doctor blade method, and this is cut into 100 mm □.

  Next, about 4 ceramic green sheets for the base material layer, via conductor forming holes were opened at predetermined positions by laser, and Ag paste was filled therein by screen printing to form via conductors to be side conductors. . Subsequently, 1.0 mm for accommodating the chip-type multilayer ceramic capacitor so that the cross-section of the via conductor to be a side conductor is exposed to the side surface of the through hole by the puncher with respect to the ceramic green sheet for the base material layer. A through hole of × 0.5 mm was made. That is, for these ceramic green sheets for the base layer, side conductors exposed on the side surfaces of the through holes were formed simultaneously with the formation of the through holes for accommodating the chip-type electronic components. Further, through holes for accommodating chip-type multilayer ceramic capacitors were made in the same manner as described above on four other ceramic green sheets for base material layers.

  Next, on the ceramic green sheet for shrinkage suppression layer, two ceramic green sheets for base material layer having through holes, four ceramic green sheets having through holes and side conductors, and ceramic for base material layer having through holes The green sheets were sequentially stacked, and a 1.0 mm × 0.5 mm × 0.4 mm chip type multilayer ceramic capacitor was accommodated in the through hole so as to fit in the substantially central portion of the through hole. Further, a ceramic green sheet for shrinkage suppression layer was laminated thereon, followed by pressure bonding at a temperature of 60 ° C. and a pressure of 180 MPa.

  Next, this is fired at 870 ° C., and the ceramic green sheet for the shrinkage suppression layer, which is unsintered based on the wet honing method, is removed, whereby the ceramic multilayer substrate containing the chip-type multilayer ceramic capacitor in the through hole Obtained.

Thus, since the green ceramic laminated body which consists of the ceramic green sheet for base materials layers was baked with being pinched | interposed into the ceramic green sheet for shrinkage | contraction suppression layers, the shrinkage | contraction of the plane direction could be suppressed. That is, since the chip-type multilayer ceramic capacitor housed in the through-hole penetrating the upper and lower main surfaces of the green ceramic multilayer body does not substantially contract, the external terminals of the chip-type multilayer ceramic capacitor and the side conductors of the ceramic multilayer substrate The electrical connection could be maintained. In addition, since the electrical connection between the chip-type multilayer ceramic capacitor and the ceramic multilayer substrate is not the bottom surface of the ceramic multilayer substrate but the side surface, there is no need for ceramic layers above and below the chip-type multilayer ceramic capacitor. Although a ceramic capacitor was built in, a low-profile ceramic multilayer substrate could be obtained. Furthermore, since there are no ceramic layers above and below the chip-type multilayer ceramic capacitor, no cracks were observed at the interface (junction).

It is a schematic perspective view of the partial cross section which shows the state which accommodated the chip type electronic component in the ceramic multilayer substrate of this embodiment. It is a schematic perspective view of the partial cross section which shows the state which removed the chip-type electronic component in the same ceramic multilayer substrate. It is a schematic sectional drawing which shows the manufacturing method of the same ceramic multilayer substrate. It is the schematic sectional drawing (A) which shows the state before baking of the ceramic multilayer substrate with a chip | tip electronic component of patent document 2, and the schematic sectional drawing (B) which similarly shows the state after baking.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Ceramic multilayer substrate 2 ... Ceramic laminated body 3 ... Ceramic layer 4 ... Upper main surface 5 ... Lower main surface 6 ... Through-hole 7 ... Side surface 8 ... Side conductor 9 ... Upper surface conductor 10 ... Lower surface conductor 11 ... Inside Conductor 12 ... Via conductor 15 ... Chip type electronic component 16 ... External terminal

Claims (9)

A plurality of ceramic layers are laminated, and a ceramic laminate including a through hole penetrating the upper and lower main surfaces, and a side conductor exposed on a side surface of the through hole,
A chip-type electronic component housed in the through hole and having an external terminal connected to the side conductor;
It is configured to include a,
Wherein that it is directly connected to the side conductor and said external terminal is integrally fired, ceramic multilayer substrate.   The through hole is a rectangular through hole, the chip electronic component is a rectangular chip electronic component, and all the side surfaces of the chip electronic component are accommodated in contact with the side surface of the through hole. The ceramic multilayer substrate according to claim 1.   3. The ceramic multilayer substrate according to claim 1, wherein the side conductor is formed by a via conductor provided in the ceramic layer.   The said ceramic layer is formed with the low-temperature sintering ceramic material, The said ceramic laminated body is equipped with the internal conductor pattern which has silver or copper as a main component in the inside. Ceramic multilayer substrate. A step of producing a green ceramic laminate comprising a plurality of green ceramic layers laminated, a through hole penetrating the upper and lower main surfaces, and a side conductor exposed on the side surface of the through hole;
A step of accommodating a chip-type electronic component in the through hole of the green ceramic laminate so that an external terminal is connected to the side conductor;
Firing the green ceramic laminate at a sintering temperature of the green ceramic layer;
A method for producing a ceramic multilayer substrate.   After accommodating the chip-type electronic component in the through hole, a shrinkage suppression layer that is not substantially sintered at the sintering temperature of the green ceramic layer is provided on at least one main surface of the green ceramic laminate, and the green ceramic The method for producing a ceramic multilayer substrate according to claim 5, wherein after the laminate is fired at the sintering temperature of the green ceramic layer, the shrinkage suppression layer is removed.   The chip-type electronic component is formed such that the through-hole is a rectangular through-hole, the chip-type electronic component is a rectangular chip-type electronic component, and all side surfaces of the chip-type electronic component are in contact with the side surface of the through-hole. The method for manufacturing a ceramic multilayer substrate according to claim 5, wherein a component is accommodated in the through hole.   The method for producing a ceramic multilayer substrate according to claim 5, wherein the side conductor is formed by dividing a via conductor provided in the green ceramic layer.   The ceramic according to claim 5, wherein the green ceramic layer is formed of a low-temperature sintered ceramic material, and an internal conductor pattern mainly composed of silver or copper is formed inside the green ceramic laminate. A method for producing a multilayer substrate.

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