JP5477191B2 - Coil parts - Google Patents

Description

  The present invention relates to a coil component.

  As a coil component, one in which a plurality of flat printed coils on which a spiral conductive pattern is formed is stacked, and a core is disposed so as to penetrate the center of the conductive pattern of the printed coil is known. (For example, refer to Patent Document 1). In this coil component, a printed coil is sandwiched between an upper component mounting board and a lower component mounting board, and a capacitive element (electronic component) for a filter circuit is mounted on the upper component mounting board and the lower component mounting board.

JP-A-6-349647

  By the way, when the capacitive element for filter circuits is provided in a laminated body like the said conventional coil components, the one end side of the terminal electrode of a capacitive element is connected to a ground terminal electrode. The capacitive element and the ground terminal electrode are connected by a lead conductor (ground line). When the line length of the conducting path of the lead conductor is increased, an equivalent series inductance is generated in the conducting path, which causes a problem that the filter characteristics are deteriorated. In particular, when a capacitive element is provided on the outer surface of the substrate as in a conventional coil component, the line length of the lead conductor is inevitably increased, so that the filter characteristics are significantly degraded.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a coil component capable of improving the filter characteristics.

  In order to solve the above-described problems, a coil component according to the present invention includes a base body in which a plurality of substrates are stacked, a coil formed in the base body, a chip part connected to the coil, and at least one of the base bodies. A coil component including a terminal electrode disposed on an end surface, wherein the coil is formed in the base by laminating a substrate on which a conductor is formed, and the chip component is connected to the terminal electrode. The conductor is provided on the substrate formed on the surface and is located in the base.

  In this coil component, the chip component is provided on the substrate on which the lead conductor connected to the terminal electrode is formed, and is located in the base. Thereby, the line length of the lead conductor which connects a chip component and a terminal electrode can be shortened. Therefore, the equivalent series inductance of the conducting path of the lead conductor can be suppressed, and as a result, the filter characteristics can be improved.

  It is preferable that an accommodating space for accommodating the chip component is formed at a boundary portion between the substrate on which the chip component is provided and the substrate disposed on the side where the lead conductor of the substrate is formed. Thereby, since chip components are reliably accommodated in the inside of the base, the line length of the lead conductor can be suppressed more favorably.

  The coil includes a first coil and a second coil, a first lead conductor connecting the first terminal electrode disposed on the end surface of the base and the end of the first coil, and a first lead disposed on the end surface of the base. A second lead conductor connecting the two-terminal electrode and the end of the second coil, and the first lead conductor and the second lead conductor are respectively formed on adjacent substrates in the stacking direction of the substrates, The substrate is preferably formed at a position overlapping in the stacking direction. According to such a configuration, since the first lead conductor and the second lead conductor are disposed close to each other in the stacking direction, the magnetic coupling between the first lead conductor and the second lead conductor can be enhanced.

  It is provided with a core around which the first coil and the second coil are wound, and the axial direction of the core part of the core around which the first coil and the second coil are wound is a direction orthogonal to the stacking direction of the substrates. preferable. In this case, since the core extends in a direction orthogonal to the stacking direction, the number of turns of the first coil and the second coil can be increased while suppressing an increase in the height dimension of the base and reducing the size. it can.

  The first coil and the second coil are preferably bifilar wound around the core. In this case, the magnetic coupling between the first coil and the second coil can be enhanced.

  The chip component is preferably a capacitive element. In this case, since the filter circuit can be configured, it can be configured as a common mode filter that removes common mode components (noise).

  According to the present invention, it is possible to improve the filter characteristics.

It is the perspective view which looked at the common mode filter concerning one embodiment of the present invention from the upper part. It is the perspective view which looked at the common mode filter shown in FIG. 1 from the downward direction. It is a disassembled perspective view of the common mode filter shown in FIG. It is the sectional view on the AA line in FIG. It is the BB sectional view taken on the line in FIG. It is CC sectional view taken on the line in FIG. It is a perspective view which shows the coil pattern contained in a common mode filter. It is a figure which shows the cross section of a common mode filter typically. It is a figure explaining the equivalent circuit of a common mode filter.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the same reference numerals are used for the same elements or elements having the same functions, and redundant description is omitted. The following embodiment is an example in which the coil component of the present invention is applied to a common mode filter (surface mount noise filter).

  1 is a perspective view of a common mode filter according to an embodiment of the present invention as viewed from above, FIG. 2 is a perspective view of the common mode filter illustrated in FIG. 1 as viewed from below, and FIG. It is a disassembled perspective view of the common mode filter shown in FIG. 4 is a sectional view taken along line AA in FIG. 1, FIG. 5 is a sectional view taken along line BB in FIG. 1, and FIG. 6 is a sectional view taken along line CC in FIG.

  As shown in each figure, the common mode filter 1 includes a substantially rectangular parallelepiped base 2 and a plurality (two in this case) of input / output terminal electrodes 3a disposed on one end face 2a side in the longitudinal direction of the base 2. 3b, a ground terminal electrode (terminal electrode) 3c disposed between the input / output terminal electrodes 3a and 3b on one end face 2a side in the longitudinal direction of the base body 2, and the other end face 2b side in the longitudinal direction of the base body 2 A plurality of (here, two) input / output terminal electrodes (first and second terminal electrodes) 4a and 4b are provided. For example, the common mode filter 1 has a length of 8.5 mm and a width of 6 mm.

  As shown in FIGS. 1 and 2, the input / output terminal electrodes 3a and 3b are arranged on the end surface 2a of the base 2 with a predetermined interval, and are formed across the end surface 2a and the lower surface 2c. The ground terminal electrode 3c is formed across the end surface 2a and the lower surface 2c between the input / output terminal electrodes 3a and 3b. The input / output terminal electrodes 4a and 4b are arranged at a predetermined interval on the end surface 2b of the base 2, and are formed across the end surface 2b and the lower surface 2c. The input / output terminal electrodes 3a, 3b, 4a, 4b and the ground terminal electrode 3c are formed by, for example, through-hole plating.

  As shown in FIG. 3, the base 2 is a laminate in which a plurality of substrates 10 to 17 including the substrates 12, 13, 15, and 16 having the first to fourth conductor patterns 31 to 34 formed on the surface are laminated. is there. The boards 10 to 17 are printed boards, for example, glass epoxy boards. In the base 2, the layers of the substrates 10 to 17 are integrated so that the boundary between them cannot be visually recognized. Hereinafter, the substrates 10 to 17 will be described in detail.

  The board | substrate 10 is arrange | positioned at the lowest layer. A first lead conductor 21 is formed on the surface of the substrate 10. The outer end 21a of the first lead conductor 21 is drawn to the end face 2b of the base 2 and connected to the input / output terminal electrode 4a. The inner end 21b of the first lead conductor 21 extends toward the input / output terminal electrode 3b on the diagonal side of the input / output terminal electrode 4a. A second lead conductor 22 and a third lead conductor 23 are formed on the surface of the substrate 10. The outer end 22a of the second lead conductor 22 is drawn to the end face 2a of the base 2 and connected to the input / output terminal electrode 3a. The inner end 22b of the second lead conductor 22 is connected to the ground terminal electrode 3c side. It is growing. The third lead conductor 23 is drawn to the end surface 2 a of the base 2 and connected to the ground terminal electrode 3 c, and the inner end 23 b of the third lead conductor 23 extends to the center side of the base 2.

  Between the second lead conductor 22 and the third lead conductor 23, a chip capacitor (chip part, capacitive element) C1, which is an electronic part for a filter circuit, is provided. The chip capacitor C1 has a pair of terminal electrodes connected to the inner end 22b side of the second lead conductor 22 and the outer end 23a side of the third lead conductor 23, respectively. Near the outer end 23 a of the third lead conductor 23, a chip capacitor C <b> 2 is provided. That is, the chip type capacitors C1 and C2 are mounted on the substrate 10 on which the third lead conductor 23 connected to the ground terminal electrode 3c is formed, at a position close to the ground terminal electrode 3c. As a result, the line length of the third lead conductor 23 connecting the chip type capacitors C1 and C2 and the ground terminal electrode 3c is shortened, so that the equivalent series inductance (ESL: Equivalent Series Inductance) of the conduction path of the third lead conductor 23 is reduced. It is suppressed. The substrate 10 constitutes the lower surface 2c of the base 2 described above.

  The substrate 11 is disposed on the substrate 10. A fourth lead conductor 24 is formed on the surface of the substrate 11. The outer end 24a of the fourth lead conductor 24 is drawn to the end face 2b of the base 2 and connected to the input / output terminal electrode 4b. The inner end 24b of the fourth lead conductor 24 extends toward the input / output terminal electrode 3b. As shown in FIG. 6, the fourth lead conductor 24 and the first lead conductor 21 are formed at positions where the extending portions 21 c and 24 c overlap in the stacking direction when the substrate 10 and the substrate 11 are stacked. .

  A fifth lead conductor 25 is formed on the surface of the substrate 11. The outer end 25a of the fifth lead conductor 25 is drawn to the end surface 2a of the base 2 and connected to the input / output terminal electrode 3b. The inner end 25b of the fifth lead conductor 25 is connected to the center side of the base 2. It is growing. An inner end 25 b of the fifth lead conductor 25 is connected to the third lead conductor 23. Thus, the fifth lead conductor 25 is connected to the chip capacitor C2. In the base body 2, the substrate 11 is penetrated in the thickness direction at positions corresponding to the inner end 23 b of the third lead conductor 23, the inner end 21 b of the first lead conductor 21, and the inner end 22 b of the second lead conductor 22. Through-hole conductors 40, 41, and 42 are formed.

  In the substrate 11, openings (accommodating spaces) K 1 and K 2 are formed at positions corresponding to the chip capacitors C 1 and C 2 mounted on the surface of the substrate 10. With this configuration, the chip capacitors C1 and C2 are accommodated in the openings K1 and K2 in a state where the substrate 10 and the substrate 11 are laminated. As a result, the chip capacitors C1 and C2 are mounted on the inside of the base body 1 on the substrate 10 and the substrate 11 on the upper layer of the substrate 10 is positioned.

  The substrate 12 is disposed on the substrate 11. A first coil conductor 31 is formed on the surface of the substrate 12. The first coil conductor 31 has a substantially strip shape and extends in the width direction of the substrate 12. The first coil conductors 31 are provided in two rows in the width direction of the substrate 12 with a predetermined interval therebetween, and a plurality of the first coil conductors 31 are arranged in the longitudinal direction of the substrate 12. The first coil conductors 31 are electrically insulated on the substrate 12. The first coil conductor 31 formed on the input / output terminal electrode 4a side of the substrate 12 is larger in length than the other first coil conductors 31 and is bent at the center portion of the substrate 12 to have its end portion. 31a extends to the input / output terminal electrode 4b side. In the substrate 12, through-hole conductors penetrating the base 2 in the thickness direction at positions corresponding to the inner end 24 b of the fourth lead conductor 24, the inner end 25 b of the fifth lead conductor 25, and the through-hole conductors 41 and 42. 43 to 46 are formed.

  The substrate 13 is disposed on the substrate 12. A second coil conductor 32 is formed on the surface of the substrate 13. The second coil conductor 32 has a substantially strip shape and extends in the width direction of the substrate 13. The second coil conductors 32 are provided in two rows in the width direction of the substrate 13 with a predetermined interval therebetween, and a plurality of the second coil conductors 32 are arranged in the longitudinal direction of the substrate 13. The length dimension of the second coil conductor 32 is smaller than the length dimension of the first coil conductor 31, and the second coil conductors 32 are electrically insulated on the substrate 13. The second coil conductor 32 formed on the input / output terminal electrode 4a side of the substrate 13 has a length dimension larger than that of the other second coil conductors 32, and is bent at the center portion of the substrate 13 to have its end portion. 32a extends to the input / output terminal electrode 4b side. On the substrate 13, through-hole conductors 47 and 48 that penetrate the substrate 13 in the thickness direction are formed at positions corresponding to both ends of the first coil conductor 31.

  A plurality of substrates 14 (for example, six layers) are continuously stacked on the base 2. The board | substrate 14 is arrange | positioned on the board | substrate 13, and has a pair of 1st connection parts 14a and 14b and the 2nd connection part 14c. The first connection portions 14 a and 14 b are arranged to face each other in the width direction of the base 2. In the first connection portions 14a and 14b, through-hole conductors 49 and 50 penetrating in the thickness direction are formed at positions corresponding to the one end portion of the second coil conductor 32 formed on the substrate 13 and the through-hole conductor 47. Yes.

  The second connection portion 14c is provided between the pair of first connection portions 14a and 14b with a predetermined distance from the first connection portions 14a and 14b. In the second connection portion 14c, through-hole conductors 51 and 52 penetrating in the thickness direction are formed at positions corresponding to the other end portion of the second coil conductor 32 formed on the substrate 13 and the through-hole conductor 48. . The length dimension of the 2nd connection part 14c is smaller than the length dimension of the 1st connection parts 14a and 14b.

  The substrate 15 is disposed on the substrate 14. A third coil conductor (third conductor) 33 is formed on the surface of the substrate 15. The third coil conductor 33 has a substantially strip shape and extends in the width direction of the substrate 15. The third coil conductors 33 are provided in two rows in the width direction of the substrate 15 with a predetermined distance from each other, and a plurality of the third coil conductors 33 are arranged in the longitudinal direction of the substrate 15. The third coil conductors 33 are electrically insulated on the substrate 15. The third coil conductor 33 is disposed opposite to the second coil conductor 32 in the stacking direction, and the length dimension of the third coil conductor 33 is equal to the length dimension of the second coil conductor 32. In the substrate 15, through-hole conductors 53 and 54 penetrating the substrate 15 in the thickness direction are formed at positions corresponding to the through-hole conductors 50 and 52 of the first connection portions 14a and 14b and the second connection portion 14c. .

  The substrate 16 is disposed on the substrate 15. A fourth coil conductor (fourth conductor) 34 is formed on the surface of the substrate 16. The fourth coil conductor 34 has a substantially strip shape and extends in the width direction of the substrate 16. The fourth coil conductors 34 are provided in two rows in the width direction of the substrate 16 with a predetermined interval therebetween, and a plurality of the fourth coil conductors 34 are arranged in parallel in the longitudinal direction of the substrate 16. The fourth coil conductors 34 are electrically insulated on the substrate 16. The fourth coil conductor 34 is disposed to face the first coil conductor 31 in the stacking direction, and the length dimension of the fourth coil conductor 34 is equal to the length dimension of the first coil conductor 31. The substrate 17 is disposed on the substrate 16. The substrate 17 constitutes the upper surface of the base 2.

  The through-hole conductors 40 to 54 are filled with a conductor. The through-hole conductors 40 to 54 may be formed on the substrate in advance, or may be formed after the substrates 11 to 15 are laminated and plated. Further, the through-hole conductors 40 to 54 may have a configuration in which a conductor is formed on the surface in addition to a configuration in which the conductor is filled.

  The substrates 10 to 17 described above are laminated by sandwiching glass fibers impregnated with an adhesive (resin) between the layers. And by laminating | stacking the board | substrates 10-17, as shown in FIG.7 and FIG.8, the 1st coil 61 and the 2nd coil 62 are formed in the base | substrate 2. As shown in FIG. Specifically, by laminating the substrates 10 to 17, the first coil conductor 31, the second coil conductor 32, the third coil conductor 33, the fourth coil conductor 34, and the through-hole conductors 40 to 54 are electrically connected. The first coil 61 and the second coil 62 are connected and formed in the base 2.

  The first coil 61 has one end connected to the first lead conductor 21 and the other end connected to the second lead conductor 22. The first coil 61 is formed outside the second coil 62 on the side where the end is connected to the first lead conductor 21 (the right side in the figure), and the end is connected to the second lead conductor 22. On the side (the left side in the figure), it is formed inside the second coil 62.

  The second coil 62 has one end connected to the fourth lead conductor 24 and the other end connected to the fifth lead conductor 25. The second coil 62 is formed inside the first coil 61 on the side where the end is connected to the fourth lead conductor 24 (right side in the figure), and the end is connected to the fifth lead conductor 25. On the side (the left side in the figure), it is formed outside the first coil 61.

  The first coil 61 and the second coil 62 described above are wound around the cores 71 and 72. The cores 71 and 72 are made of a magnetic material (eg, ferrite) or a non-magnetic material (eg, ceramic). The cores 71 and 72 are provided between the first connection portions 14a and 14b and the second connection portion 14c. Each of the cores 71 and 72 has a U-shape, and is a space S formed by the first connection portions 14a and 14b and the second connection portion 14c that are spaced apart (see FIG. 4). Has been inserted. Specifically, as shown in FIG. 5, the cores 71 and 72 are respectively inserted from the end surfaces 2 a and 2 b side of the base 2 so that the end faces are brought into contact with each other. ). The axial center direction of the cores 71 and 72 is a direction orthogonal to the stacking direction of the base 2. The first coil 61 and the second coil 62 are bifilar wound around the cores 71 and 72.

  Specifically, as shown in FIGS. 4, 6, and 8, the first coil 61 and the second coil 62 extend over the entire peripheral surfaces of the cores 71 a, 71 b, 72 a, 72 b of the cores 71, 72. The first coil 61 and the second coil 62 are wound in a direction that is perpendicular to the axial direction in the pair of core parts 71a and 72a and the core parts 71b and 72b. Has been. More specifically, as shown in FIG. 8, in one of the core parts 71a and 72a, the first coil 61 is wound on the core parts 71a and 72a, and the second coil 62 is wound on the upper layer. In the other core parts 71b and 72b, the second coil 62 is wound on the core parts 71b and 72b, and the first coil 61 is wound on the upper layer. More specifically, the upper second coil 62 is wound so as to be disposed in a valley formed between the lower first coils 61. Similarly, the upper first coil 61 is wound so as to be disposed in a valley formed between the lower second coils 62.

  Such winding of the first coil 61 and the second coil 62 around the cores 71 and 72 is performed by the end 31 a of the first coil conductor 31 formed on the substrate 12 and the second coil conductor 32 formed on the substrate 13. It is comprised by the edge part 32a. Specifically, by the end 31a of the first coil conductor 31 formed on the substrate 12, the second coil 62 wound outward is inside (the second coil 62 wound inside is outside), Due to the end portion 32a of the second coil conductor 32 formed on the substrate 13, the first coil 61 wound inward becomes the outside (the first coil 61 wound outward is inside). With such a configuration, the lengths of the windings (line lengths) wound around the cores 71 and 72 of the first coil 61 and the second coil 62 can be made closer to each other.

  FIG. 9 is a diagram illustrating an equivalent circuit of the common mode filter. As shown in FIG. 9, the common mode filter 1 includes a pair of coils L1 and L2 that are magnetically coupled to each other, and chip capacitors C1 and C2. The coil L1 and the coil L2 are formed of a first coil 61 and a second coil 62, and are connected between the input / output terminal electrodes 3a and 3b and the input / output terminal electrodes 4a and 4b, respectively. The chip capacitors C1 and C2 are connected in parallel to the input / output terminal electrodes 3a and 3b, and the chip capacitors C1 and C2 are connected to the ground G.

  As described above, in the common mode filter 1, the chip capacitors C1 and C2 are provided on the substrate 10 on which the third lead conductor 23 connected to the ground terminal electrode 3c is formed, and the third lead of the substrate 10 is provided. It is located at the lamination position of the substrate 11 arranged on the side where the conductor 23 is formed. Thereby, the line length of the 3rd lead conductor 23 which connects chip type capacitors C1 and C2 located in base 2, and ground terminal electrode 3c can be shortened. Therefore, the equivalent series inductance of the conduction path of the third lead conductor 23 can be suppressed, and as a result, the filter characteristics can be improved.

  Further, since the chip type capacitors C1 and C2 are accommodated in the openings K1 and K2 provided in the substrate 11, they can be surely mounted in the base 2, and the line length of the third lead conductor 23 is further increased. It can be surely suppressed.

  Further, the first lead conductor 21 that connects the input / output terminal electrode 4 a disposed on the end surface 2 b of the base 2 and the end of the first coil 61, and the input / output terminal electrode 4 b and the end of the second coil 62 are connected. A fourth lead conductor 24 to be connected. The first lead conductor 21 and the fourth lead conductor 24 are formed on the substrates 10 and 11 adjacent to each other in the stacking direction of the substrates 10 to 17, respectively. 11 is formed at a position overlapping in the stacking direction. According to such a configuration, since the first lead conductor 21 and the fourth lead conductor 24 are arranged close to each other in the stacking direction, the magnetic coupling between the first lead conductor 21 and the fourth lead conductor 24 is enhanced. Can do.

  Moreover, the axial center direction of the core parts 71a, 71b, 72a, 72b of the cores 71, 72 around which the first coil 61 and the second coil 62 are wound is a direction orthogonal to the stacking direction of the substrates 10-17. . In this case, since the cores 71 and 72 extend in a direction perpendicular to the stacking direction, the first coil 61 and the second coil 62 can be reduced in size while suppressing an increase in the height dimension of the base 2. The number of windings can be increased.

  Further, since the first coil 61 and the second coil 62 are bifilar wound around the cores 71 and 72, the magnetic coupling between the first coil 61 and the second coil 62 can be enhanced.

  The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the input / output terminal electrodes 3 a and 3 b and the ground terminal electrode 3 c are formed on the end surface 2 a side of the base 2, but the ground terminal electrode is also formed on the end surface 2 b side of the base 2. There may be. That is, a configuration in which the chip capacitors C1 and C2 are also provided on the end surface 2b side of the base 2 may be employed.

  Further, in the above embodiment, the openings K1 and K2 are provided in the substrate 11, but the accommodation space in which the chip capacitors C1 and C2 are accommodated may be formed in the boundary portion between the substrate 10 and the substrate 11. For example, the housing space may be formed by providing a recessed portion in each of the substrate 10 and the substrate 11 and opposing the recessed portion.

  DESCRIPTION OF SYMBOLS 1 ... Common mode filter (coil component), 2 ... Base | substrate, 61 ... 1st coil, 62 ... 2nd coil, 10 ... Board | substrate, 11 ... Board | substrate, 21 ... 1st extraction conductor, 22 ... 4th extraction conductor (2nd Lead conductor), 31 ... first coil conductor (conductor), 32 ... second coil conductor (conductor), 33 ... third coil conductor (conductor), 34 ... fourth coil conductor (conductor), 49-52 ... through hole Conductor (conductor), 71, 72... Core, 71a, 71b, 72a, 72b... Core portion, C1, C2.

Claims (6)

A substrate formed by laminating a plurality of substrates;
A coil formed in the substrate;
A chip component connected to the coil;
A coil component including a terminal electrode disposed on at least one end face of the base,
The coil is formed in the base body by laminating a substrate on which a conductor is formed,
The chip component is provided on a substrate on which a lead conductor connected to the terminal electrode is formed, and is located in the base.   An accommodation space for accommodating the chip component is formed in a boundary portion between the substrate on which the chip component is provided and the substrate disposed on the side where the lead conductor is formed on the substrate. The coil component according to claim 1. The coil has a first coil and a second coil,
A first lead conductor connecting the first terminal electrode disposed on the end face of the base and the end of the first coil;
A second lead conductor connecting the second terminal electrode disposed on the end face of the substrate and the end of the second coil;
The first lead conductor and the second lead conductor are respectively formed on substrates adjacent to each other in the stacking direction of the substrates, and are formed at positions overlapping the stacking direction on the substrate. The coil component according to claim 1 or 2. A core around which the first coil and the second coil are wound;
4. The coil component according to claim 3, wherein an axial direction of a core portion of the core around which the first coil and the second coil are wound is a direction orthogonal to a stacking direction of the substrate.   The coil component according to claim 4, wherein the first coil and the second coil are bifilar wound around the core.   The coil component according to any one of claims 1 to 4, wherein the chip component is a capacitive element.

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