JP4500014B2 - 分散メモリマルチプロセッサシステムにおけるメモリ移行のためのシステムおよび方法 - Google Patents

分散メモリマルチプロセッサシステムにおけるメモリ移行のためのシステムおよび方法 Download PDF

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JP4500014B2
JP4500014B2 JP2003181949A JP2003181949A JP4500014B2 JP 4500014 B2 JP4500014 B2 JP 4500014B2 JP 2003181949 A JP2003181949 A JP 2003181949A JP 2003181949 A JP2003181949 A JP 2003181949A JP 4500014 B2 JP4500014 B2 JP 4500014B2
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memory
cell
migration
cache
line
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Japanese (ja)
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JP2004054931A (ja
JP2004054931A5 (https=
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デベンドラ・ダス・シャルマ
アシシュ・グプタ
ウィリアム・アール・ブライグ
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Hewlett Packard Development Co LP
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
JP2003181949A 2002-07-23 2003-06-26 分散メモリマルチプロセッサシステムにおけるメモリ移行のためのシステムおよび方法 Expired - Fee Related JP4500014B2 (ja)

Applications Claiming Priority (1)

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US10/201,180 US7103728B2 (en) 2002-07-23 2002-07-23 System and method for memory migration in distributed-memory multi-processor systems

Publications (3)

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JP2004054931A JP2004054931A (ja) 2004-02-19
JP2004054931A5 JP2004054931A5 (https=) 2006-08-03
JP4500014B2 true JP4500014B2 (ja) 2010-07-14

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JP2003181949A Expired - Fee Related JP4500014B2 (ja) 2002-07-23 2003-06-26 分散メモリマルチプロセッサシステムにおけるメモリ移行のためのシステムおよび方法

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US (1) US7103728B2 (https=)
JP (1) JP4500014B2 (https=)

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US6959370B2 (en) * 2003-01-03 2005-10-25 Hewlett-Packard Development Company, L.P. System and method for migrating data between memories
JP3977803B2 (ja) * 2003-12-17 2007-09-19 株式会社日立製作所 バックアップシステム及び方法並びにプログラム
US8806103B2 (en) * 2004-04-28 2014-08-12 Hewlett-Packard Development Company, L.P. System and method for interleaving memory
US7882307B1 (en) * 2006-04-14 2011-02-01 Tilera Corporation Managing cache memory in a parallel processing environment
US8621120B2 (en) * 2006-04-17 2013-12-31 International Business Machines Corporation Stalling of DMA operations in order to do memory migration using a migration in progress bit in the translation control entry mechanism
US20080010417A1 (en) * 2006-04-28 2008-01-10 Zeffer Hakan E Read/Write Permission Bit Support for Efficient Hardware to Software Handover
US7734843B2 (en) * 2006-05-25 2010-06-08 International Business Machines Corporation Computer-implemented method, apparatus, and computer program product for stalling DMA operations during memory migration
JP4868246B2 (ja) * 2007-09-12 2012-02-01 エヌイーシーコンピュータテクノ株式会社 マルチプロセッサ及びメモリリプレース方法
US20090150511A1 (en) 2007-11-08 2009-06-11 Rna Networks, Inc. Network with distributed shared memory
US20090144388A1 (en) * 2007-11-08 2009-06-04 Rna Networks, Inc. Network with distributed shared memory
JP2009187272A (ja) 2008-02-06 2009-08-20 Nec Corp 分散メモリマルチプロセッサシステムにおけるメモリ移行のための装置及び方法
WO2010052799A1 (ja) * 2008-11-10 2010-05-14 富士通株式会社 情報処理装置及びメモリ制御装置
US9239765B2 (en) * 2010-08-31 2016-01-19 Avaya Inc. Application triggered state migration via hypervisor
WO2012091702A1 (en) * 2010-12-29 2012-07-05 Empire Technology Development Llc Accelerating cache state transfer on a directory-based multicore architecture
JP5712451B2 (ja) 2011-07-28 2015-05-07 ▲ホア▼▲ウェイ▼技術有限公司 メモリ移行を実施するための方法およびデバイス
US9135172B2 (en) 2012-08-02 2015-09-15 Qualcomm Incorporated Cache data migration in a multicore processing system
US9495301B2 (en) 2012-08-07 2016-11-15 Dell Products L.P. System and method for utilizing non-volatile memory in a cache
US9852073B2 (en) 2012-08-07 2017-12-26 Dell Products L.P. System and method for data redundancy within a cache
US9549037B2 (en) 2012-08-07 2017-01-17 Dell Products L.P. System and method for maintaining solvency within a cache
CN105353980B (zh) * 2013-11-22 2019-10-22 华为技术有限公司 一种内存数据的迁移方法、计算机和装置
EP3206127B1 (en) * 2013-11-22 2019-03-06 Huawei Technologies Co., Ltd. Method, computer, and apparatus for migrating memory data
US10526785B2 (en) * 2017-04-26 2020-01-07 Opterus Research and Development, Inc. Deformable structures
US20240427702A1 (en) * 2023-06-26 2024-12-26 Google Llc Memory Copy in Mesh Networks

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JPS62206658A (ja) * 1986-03-07 1987-09-11 Hitachi Ltd 記憶管理装置
US5146605A (en) * 1987-11-12 1992-09-08 International Business Machines Corporation Direct control facility for multiprocessor network
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US5293607A (en) * 1991-04-03 1994-03-08 Hewlett-Packard Company Flexible N-way memory interleaving
US6049851A (en) * 1994-02-14 2000-04-11 Hewlett-Packard Company Method and apparatus for checking cache coherency in a computer architecture
US5530933A (en) * 1994-02-24 1996-06-25 Hewlett-Packard Company Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus
US5530837A (en) * 1994-03-28 1996-06-25 Hewlett-Packard Co. Methods and apparatus for interleaving memory transactions into an arbitrary number of banks
EP0681240B1 (en) * 1994-05-03 2001-01-10 Hewlett-Packard Company Duplicate cache tag memory system
JPH07311749A (ja) * 1994-05-19 1995-11-28 Toshiba Corp マルチプロセッサシステム及びカーネル置換方法
JP3889044B2 (ja) * 1995-05-05 2007-03-07 シリコン、グラフィクス、インコーポレイテッド 不均一メモリ・アクセス（ｎｕｍａ）システムにおけるページ移動
US6055610A (en) * 1997-08-25 2000-04-25 Hewlett-Packard Company Distributed memory multiprocessor computer system with directory based cache coherency with ambiguous mapping of cached data to main-memory locations
JPH11238047A (ja) * 1998-02-20 1999-08-31 Nec Corp 分散共有メモリシステム及びプログラムを記録した機械読み取り可能な記録媒体
US6785783B2 (en) * 2000-11-30 2004-08-31 International Business Machines Corporation NUMA system with redundant main memory architecture

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JP2004054931A (ja) 2004-02-19
US20040019751A1 (en) 2004-01-29
US7103728B2 (en) 2006-09-05

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