JP4496756B2 - Electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to an electro-optical device in which a large number of pixels are arranged in a matrix, and an electronic apparatus including the electro-optical device.

  Among various electro-optical devices, an electroluminescence (hereinafter referred to as EL) display device includes an EL element in each of a large number of pixels arranged in a matrix, and each pixel receives a current applied to the EL element. Provided with a plurality of switching elements such as a driving transistor to be supplied and a thin film transistor (hereinafter referred to as TFT) that is connected in series to a storage capacitor connected to the gate of the driving transistor and controls the timing of writing a data signal to the storage capacitor ing. Then, by turning on / off the TFT and storing a predetermined voltage in the storage capacitor, the voltage of the power supply line is controlled by the gate voltage of the driving transistor, and the current flowing through the EL element is controlled (for example, patents) References 1 and 2).

In addition, although an inorganic material has been conventionally studied as an EL element, a display device using an organic EL element of an organic material having a lower voltage and higher luminous efficiency has recently been put into practical use.
JP 2003-150118 A Japanese Patent Application Laid-Open No. 2003-66868, page 9

  In the EL display device, since the driving transistor is operated in the saturation region, the current change with respect to the change in the gate voltage is steep. Accordingly, it is necessary to accurately apply the gate bias, and for that purpose, it is necessary to accurately hold the charge in the storage capacitor.

  However, conventionally, in a switching element connected in series with a storage capacitor, no measures have been taken to suppress the current that flows during off (off-leakage current) to a small value, so that the charge cannot be accurately held in the storage capacitor. . As a result, the gate bias of the driving transistor changes, and the current flowing through the EL element also changes. The change in the gate bias reflects the manufacturing variation of the element well, and there is a problem that uniform and high-quality gradation display cannot be performed.

  In particular, in an EL display device, since a relatively large current needs to flow through the EL element, an active layer is formed of a low-temperature polysilicon film for the TFT. A TFT using a low-temperature polysilicon film has many defects at the polycrystalline grain boundaries. For this reason, the off-leakage current due to tunneling through the energy level formed by such a defect is quite large, and it is difficult to make the off-leakage current as small as a transistor using a single crystal silicon film. .

  In view of the above problems, in the present invention, in an electro-optical device in which a large number of pixels are arranged in a matrix and an electronic apparatus including the same, a TFT with reduced off-leakage current is used for each pixel in an appropriate place. Accordingly, it is an object of the present invention to provide a configuration capable of improving display quality.

In order to solve the above problems, in the present invention, each of a number of pixels arranged in a matrix, at least, with a multiple transistors for driving electroluminescent (EL) element, and the EL element In the electro-optical device, each of the plurality of pixels includes, as the transistor, at least a driving transistor for controlling a current applied to the EL element, a storage capacitor connected to a gate of the driving transistor, and the storage A first transistor that is connected in series to a capacitor and controls the timing of writing a data signal to the storage capacitor, and is connected in series between the driving transistor and the EL element to turn on and off a current that flows through the EL element. A second transistor that is opposite to the storage capacitor with respect to the first transistor. A third transistor connected in a column, and an electrical connection point between the first transistor and the third transistor and a short circuit between the electrical connection point between the driving transistor and the second transistor As the first transistor, a thin film transistor ( TFT ) having an asymmetric structure in which a channel width dimension on the source region side and a channel width dimension on the drain region side are different is used , and the TFT having the asymmetric structure is an n-channel type. Of the source / drain region, the one with the smaller channel width dimension is arranged on the higher potential side when the TFT is turned off, and when the TFT having the asymmetric structure is a p-channel type, of, smaller channel width dimension for those a lower potential side when off of the TFT is disposed, characterized in Rukoto.

  The channel width dimension in the present specification means a dimension in a direction orthogonal to the channel length direction when the channel is viewed in a plane. Further, when the boundary portion between the channel region and the source / drain region is arcuate, it means the dimension in the circumferential direction.

  In the present invention, there are cases where a plurality of types of EL elements corresponding to the respective colors are formed as the EL elements. In this case, in the pixels corresponding to any color, the channel width dimension in the source / drain regions. A configuration may be adopted in which the smaller one is connected to the storage capacitor side or the larger channel width dimension is connected to the storage capacitor side.

  In addition, a plurality of types of EL elements corresponding to the respective colors may be formed as the EL elements. In this case, the smaller channel width dimension of the source / drain regions is connected to the storage capacitor side. In other cases, the pixel may be different depending on the corresponding color depending on whether the larger channel width dimension is connected to the storage capacitor. In the case of an EL element, the diode characteristics may differ depending on the color. In this case, when the TFT having the asymmetric structure is turned off, the direction of the voltage applied to the TFT may change. Therefore, it is preferable to match the orientation of the asymmetrical TFT with the characteristics of the EL element.

  The present invention is effective in reducing off-leakage current when applied to the case where the active layer of the TFT having the asymmetric structure is composed of a low-temperature polysilicon film. When the active layer is formed of a low-temperature polysilicon film, there is an advantage that a glass substrate can be used as a substrate, but there is a disadvantage that off-leakage current is large. Therefore, if this disadvantage is eliminated by the non-target structure, the advantages of the TFT using the low-temperature polysilicon film can be utilized to the maximum extent.

  In the present invention, in the TFT having the asymmetric structure, the source region, the channel region, and the drain region are arranged concentrically in this order, and the source region, the channel region, and the drain region are arranged in an arc shape in this order. And a structure in which the semiconductor film is formed with a triangular or trapezoidal planar shape, and in the height direction, the source region, the channel region, and the drain region are arranged in this order. If such a structure is employed, the channel width dimension on the source region side and the channel width dimension on the drain region side can be made different.

  In the present invention, the asymmetric TFT may have a double gate structure.

  In the present invention, the asymmetric TFT preferably has an LDD structure or an offset gate structure. This configuration has an advantage that the off-leakage current can be further reduced.

  The electro-optical device to which the present invention is applied is used as a display unit of an electronic apparatus such as a mobile computer or a mobile phone.

  In the present invention, a large number of pixels arranged in a matrix use an asymmetric TFT in which the channel width dimension on the source region side and the channel width dimension on the drain region side are different. In the case of the type, of the source / drain regions, the one with the smaller channel width dimension is arranged on the higher potential side when off, and when the TFT having an asymmetric structure is a p-channel type, the source / drain regions Of these, the one with the smaller channel width dimension is disposed on the low potential side when turned off. In such an asymmetric TFT, the off-leakage current is extremely small, so that the electro-optic element can be driven under stable conditions. Therefore, display quality can be improved, such as good gradation display.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 and FIG. 2 are a block diagram of an active matrix EL display device to which the present invention is applied, and an explanatory diagram showing a configuration of the pixel. FIG. 3 is an explanatory diagram showing a state of current programming of the EL display device to which the present invention is applied.

  As shown in FIGS. 1 and 2, in the EL display device 1, a large number of pixels 11 are arranged in a matrix in an image display region 13 on a substrate 10, and a data line driving circuit 12 and a peripheral region are arranged in the peripheral region. A scanning line driving circuit 14 is configured. In the EL display device 1, each of a large number of pixels 11 includes a drive composed of an EL element 20 as a current-driven light-emitting element (electro-optical element) and a p-channel TFT that controls a current applied to the EL element 20. Transistor 30, a storage capacitor 40 connected to the gate of the driving transistor 30, and a first n-channel TFT 50 connected in series to the storage capacitor 40 to control the timing of writing a data signal to the storage capacitor 40. (First switching element). In addition to the driving transistor 30 and the first TFT 50, each of the large number of pixels 11 includes an n-channel type that is connected in series to the driving transistor 50 and turns on and off a current flowing through the EL element 20. A second TFT 60 (second switching element) and an n-channel third TFT 70 (third switching element) connected in series on the opposite side of the storage capacitor 40 with respect to the first TFT 50 are configured. The electrical connection point 55 between the first TFT 50 and the third TFT 70 and the electrical connection point 35 between the driving transistor 30 and the second TFT 60 are short-circuited.

  Although not shown, the EL element 20 has at least one organic functional layer (EL layer) composed of an electron transport layer, a light emitting layer, a hole transport layer, and the like, and a metal electrode (reflection film) on the pixel electrode. The organic functional layer (EL layer) emits light when a voltage is applied between the pixel electrode and the metal electrode.

  The data line driving circuit 12 supplies a video signal for one line converted into grayscale data in accordance with the horizontal synchronization signal to the data line 16, while the scanning line driving circuit 14 includes the first TFT 50 and the third TFT. A signal for controlling the on / off operation of the TFT 70 is supplied to the first scanning line 17, and a signal for controlling the on / off operation of the second TFT 60 is supplied to the second scanning line 18.

  In such an EL display device 1, a signal for turning on the first TFT 50 and the third TFT 70 is supplied to the selected row via the first scanning line 17, and the second scanning line 18. Is supplied with a signal for turning off the second TFT 60. On the other hand, in the non-selected row, a signal for turning off the first TFT 50 and the third TFT 70 is supplied via the first scanning line 17, and the second scanning line 18 is supplied with the second scanning line 18. A signal for turning on the TFT 60 is supplied.

Accordingly, in the selected row, a predetermined current flows from the data line 16 by turning on the first TFT 50 and the third TFT 70. As a result, the gate and drain of the driving transistor 30 are short-circuited to have substantially the same potential, and a predetermined current (current value to be passed through the EL element 20) flows through the driving transistor 30 and the third TFT 70. At this time, the gate of the driving transistor 30 - the drain voltage becomes the driving transistor voltage value such as a predetermined current flows to 30, the storage capacitor 40 is the gate voltage of the charge at that time is accumulated. That is, by applying an ON voltage to the first scanning line 17, a predetermined current to be passed to the EL element 20 is caused to flow to the driving transistor 30 via the third TFT 70, and the storage capacitor 40 causes this current to flow. The gate voltage value of the driving transistor 30 commensurate with the flow is stored (current program).

  When performing such a current program, the driving transistor 30 is always in the saturation region because the gate and the drain are short-circuited and become substantially at the same potential. That is, the operation of the driving transistor 30 is allowed only on the bias curve satisfying Vds = Vgs shown by the solid line L10 in the characteristic curve (drain-source voltage Vds vs. drain-source current I) of the p-channel transistor of FIG. The

  On the other hand, in the non-selection period, the second TFT 60 is turned on, and the first TFT 50 and the third TFT 70 are turned off. The current flowing from the power supply line 19 to the driving transistor 30 is defined by the gate voltage Vgs held in the storage capacitor 40 during the selection period. This current value should match the current programmed predetermined current value described above. As a result, the predetermined current flows through the EL element 20 and the EL element 20 should emit light with a desired luminance.

However, the bias variation occurs when the second TFT 60 is turned on to shift to an operation in which a current flows through the EL element 20 . Since the gate voltage Vgs of the driving transistor 30 is kept constant, the driving transistor 30 can change only on the solid line L1 is a current curve when the constant gate voltage Vgs. On the other hand, since the EL element 20 has a diode type characteristic, it operates according to the current curve of the solid line L21. The bias point of operation is determined by the intersection of the solid line L1 that is the operation curve of the driving transistor and the solid line L21 that is the current curve of the EL element.

That is, when shifting from the current programming to the EL light emission operation, the drain-source voltage Vds of the driving transistor 30 is shifted from the point P11 to the position indicated by the point P12. In the first TFT 50 in the off state, the source potential and drain potential, which were substantially equal during current programming, are higher than the drain potential in response to this voltage change. Therefore, would be to first charge held and the storage capacitor 40 is larger off-leak current of the TFT50 is changed, the gate bias for the driving transistor motor 3 0 is increased. As a result, the luminance of the light emitting element is changed.

  Therefore, in this embodiment, the following asymmetric structure TFT is used as the first TFT 50.

[Configuration of TFT with asymmetric structure]
4A and 4B are a plan view and a cross-sectional view of a TFT having an asymmetric structure according to the present invention. FIG. 5 is a graph showing the relationship between the gate-source voltage and the drain-source current of an asymmetric TFT, a conventional self-aligned TFT, and a conventional LDD TFT.

  In this embodiment, as shown in FIG. 4, the asymmetric TFT used as the first TFT 50 is a high-concentration source region with respect to the circular low-temperature polycrystalline silicon film 100 from the center side toward the outer peripheral side. A source region 120 including 121 and a low concentration source region 122, a channel region 110, and a drain region 130 including a low concentration drain region 132 and a high concentration drain region 131 are formed concentrically in this order. A source electrode 125 and a drain electrode 135 are electrically connected to the high-concentration source region 121 and the high-concentration drain region 131, respectively, and a gate electrode 115 is connected to the channel region 110 through a gate insulating film 140. Confronted.

Here, since the source region 120 is on the center side and the drain region 130 is on the outer peripheral side, the length dimension (channel width dimension) in the circumferential direction of the interface between the low concentration source region 122 and the channel region 110 is low. It is shorter than the length dimension (channel width dimension) in the circumferential direction of the interface between the concentration drain region 132 and the channel region 110. Therefore, the TFT shown in FIG. 4 is a TFT having an asymmetric structure in which the channel width dimension on the source region 120 side and the channel width dimension on the drain region 130 side are different. In addition, the TFT shown here has an LDD structure including a low concentration source region 122 and a low concentration drain region 132. If an impurity is not introduced into the regions corresponding to the low concentration source region 122 and the low concentration drain region 132 and a silicon film similar to the channel region 110 is used, an asymmetric TFT having an offset gate structure is formed. Can do.

Thus the gate of the TFT structure, non-symmetrical structure - source voltage and the drain - relationship of the source current, as shown by the solid line L31 in FIG. 5, as compared with the TFT of the conventional self-aligned structure shown by the solid line L32 The off-leakage current is considerably small, and the off-leakage current is small even when compared with a conventional general parallel electrode type LDD structure TFT indicated by a solid line L33.

Therefore, when the asymmetric TFT shown in FIG. 5 is used as the first TFT 50, when the first TFT 50 is in the OFF state, the source region 120 side with a small channel width dimension is the high potential side, and the channel width dimension Since the large drain region 130 side becomes the low potential side, the off-leak current is small in the first TFT 50. Therefore, since the charge storage capacitor 40 is accurately retained, the gate bias of the driving transistor 30 does not change. Therefore, since a predetermined current continues to flow through the EL element 20, high-quality gradation display can be performed.

[Other configuration of asymmetric TFT]
6A, 6B, 6C, and 6D are plan views of another asymmetric TFT according to the present invention. Note that the TFTs shown in FIGS. 6A, 6B, 6C, and 6D have the same basic configuration as the TFTs shown in FIGS. 4A and 4B, and are therefore common. Parts are denoted by the same reference numerals, and description thereof is omitted.

  In the present invention, as an asymmetrical TFT that can be used as the first TFT 50, as shown in FIG. 6A, the semicircular low-temperature polycrystalline silicon film 100 is changed from the inner peripheral side to the outer peripheral side. The source region 120 including the high concentration source region 121 and the low concentration source region 122, the channel region 110, and the drain region 130 including the low concentration drain region 132 and the high concentration drain region 131 are formed in an arc shape in this order. It may be arranged.

  Further, as shown in FIG. 6B, two TFTs shown in FIG. 6A are arranged in the same direction, and the high concentration source region of one TFT and the drain electrode of the other TFT are connected to the relay electrode 160. In this way, an asymmetric TFT having a double gate can be formed.

  Further, as shown in FIG. 6C, two TFTs shown in FIG. 6A are arranged so that the linear portions face each other, and the high concentration source region 121 of one TFT and the drain electrode of the other TFT are arranged. 135 is electrically connected by the relay electrode 170, a single gate electrode 115 can constitute an asymmetric TFT having a double gate. In this case, a double-gate TFT can be formed in a smaller area than the double-gate TFT shown in FIG.

Furthermore, as shown in FIG. 6D, a high-concentration drain region 131 and a low-concentration drain region 132 are formed in the height direction from the bottom side of the low-temperature polycrystalline silicon film 100 having a triangular or trapezoidal planar shape. The provided drain region 130, the channel region 110, and the source region 120 including the low-concentration source region 122 and the high-concentration source region 121 may be arranged in this order. Even in such a configuration, the length dimension (channel width dimension) of the interface between the low-concentration source region 122 and the channel region 110 is equal to the length dimension (channel width) of the interface between the low-concentration drain region 132 and the channel region 110. TFT) having a shorter asymmetric structure.

[Other embodiments]
When the EL display device 1 according to the above configuration is configured for color display, as the EL element 20, the EL elements 20 of red (R), green (G), and blue (B) are formed. If any of the red (R) EL element, the green (G) EL element, and the blue (B) EL element has the diode characteristic indicated by the solid line L21 in FIG. In any pixel 11 of R), green (G), and blue (B), when the second TFT 60 is turned on, the drain-source voltage Vds is shifted from the point P11 to the position indicated by the point P12. Therefore, in the first TFT 50 in the off state, the source potential is higher than the drain potential. Therefore, in any of the red (R), green (G), and blue (B) pixels 11, the TFT having the asymmetric structure described with reference to FIGS. 4 and 6 may be used as the first TFT 50. .

  However, the EL element 20 for red (R) has a diode characteristic indicated by a solid line L21 in FIG. 3, and the EL element 20 for green (G) has a diode characteristic indicated by a solid line L22 in FIG. When the blue (B) EL element 20 has the diode characteristic indicated by the solid line L23 in FIG. 3, the second TFT 60 is turned on in the green (G) and blue (B) pixels 11. In this case, the drain-source voltage Vds shifts from the point P21 to the position indicated by the point P22, for example. Accordingly, in the green (G) and blue (B) pixels 11, the drain potential is higher than the source potential in the first TFT 50 in the off state, contrary to the red (R) pixel 11. Therefore, when the off-leakage current of the first TFT 50 is large, the gate bias for the driving transistor TFT 30 is lowered.

In such a case, for the red (R) pixel 11, the TFT having the asymmetric structure described with reference to FIGS. 4 and 6 is used, while in the green (G) and blue (B) pixels 11, As the first TFT 50, a TFT having a structure in which the source region and the drain region are interchanged as they are in the TFT having the asymmetric structure described with reference to FIGS. 4 and 6 is used. That is, in the green (G) and blue (B) pixels 11, when the first TFT 50 is in the OFF state, the drain region side with a small channel width dimension is the high potential side, and the source region side with a large channel width dimension is low. The first TFT 50 may be configured to be on the potential side.

  With this configuration, even in the green (G) and blue (B) pixels 11, the off-leak current of the first TFT 50 is small, so that the gate bias of the driving transistor 30 does not vary. Therefore, since a predetermined current continues to flow through the EL element 20, high-quality gradation display can be performed.

  In the above embodiment, the driving transistor 30 is a p-channel TFT and the first to third TFTs 50, 60, and 70 are n-channel type. However, all of them may be p-channel type or n-channel type. . In this case, the direction of the off-leak current that the first TFT 50 tends to flow when turned off may be reversed. In that case, if the TFT having an asymmetric structure is an N-channel type, it is only necessary to arrange the smaller channel width dimension in the source / drain region on the higher potential side when the TFT is turned off. In the case of the P-channel type, the smaller channel width dimension may be disposed on the side of the source / drain region that is on the low potential side when the TFT is turned off.

  In the above embodiment, the first TFTs 50 of all the pixels 11 are asymmetrical TFTs. However, depending on the diode characteristics of the EL element 20, asymmetrical TFTs are used for some pixels 11, For the pixel 11, a conventional LDD structure, offset gate structure, or self-aligned TFT may be used.

  Further, the direction of the source / drain of the TFT having the asymmetric structure should be appropriately selected according to transistor connection and bias connected to the storage capacitor and the like, and is not limited to the embodiment shown here.

[Application to electronic devices]
7A and 7B are an explanatory diagram of a mobile personal computer as an example of an electronic apparatus using the EL display device 1 (electro-optical device) according to the present invention, and an explanatory diagram of a mobile phone, respectively. is there.

  The electronic apparatus equipped with the EL display device 1 to which the present invention is applied includes a multimedia-compatible personal computer (PC), an engineering workstation (EWS), a pager or a mobile phone, a word processor, a television, a viewfinder type, or a monitor. There are direct-view type video tape recorders, electronic notebooks, car navigation devices, POS terminals, home appliance display monitors, and pocket game machines.

  More specifically, as shown in FIG. 7A, the personal computer 180 includes a main body 182 provided with a keyboard 181 and a display unit 183. The display unit 183 includes the EL display device 1 described above. As shown in FIG. 7B, the mobile phone 190 has a plurality of operation buttons 191 and a display unit including the EL display device 1 described above.

  In the present invention, a large number of pixels arranged in a matrix use an asymmetrical TFT in which the channel width dimension on the source region side and the channel width dimension on the drain region side are different. In the case of the type, of the source / drain regions, the one with the smaller channel width dimension is arranged on the higher potential side when off, and when the TFT with an asymmetric structure is a P-channel type, the source / drain regions Of these, the one with the smaller channel width dimension is disposed on the low potential side when turned off. In such an asymmetric TFT, the off-leakage current is extremely small, so that the electro-optic element can be driven under stable conditions. Therefore, display quality can be improved, such as good gradation display.

1 is a block diagram of an active matrix EL display device to which the present invention is applied. FIG. 11 is an explanatory diagram illustrating a pixel configuration of an active matrix EL display device to which the present invention is applied. It is explanatory drawing which shows the mode of the electric current program of the EL display apparatus to which this invention is applied. (A) and (B) are the top view and sectional drawing of TFT of the asymmetrical structure which concern on this invention. 6 is a graph showing the relationship between the gate-source voltage and the drain-source current of a TFT having an asymmetric structure to which the present invention is applied, a TFT having a conventional self-aligned structure, and a TFT having a conventional LDD structure. (A)-(D) are top views of TFT of another asymmetric structure concerning the present invention. FIGS. 7A and 7B are an explanatory diagram of a mobile personal computer as an example of an electronic apparatus using the EL display device 1 (electro-optical device) according to the present invention, and an explanatory diagram of a mobile phone, respectively.

Explanation of symbols

1 EL display device (electro-optical device), 10 substrate, 11 pixels, 13 image display area, 12 data line driving circuit, 14 scanning line driving circuit, 20 EL element (current-driven light emitting element / electro-optical element), 30 driving Transistor, 40 storage capacitor, 50 first TFT (first switching element), 60 second TFT (second switching element), 70 third TFT (third switching element), 100 low temperature polycrystal Silicon film, 110 channel region, 120 source region, 130 drain region

Claims (10)

In each of a number of pixels arranged in a matrix, at least, in the electro-optical device equipped with multiple transistors for driving electroluminescent device, and the electroluminescence element,
Each of the plurality of pixels includes, as the transistor, at least a driving transistor for controlling a current applied to the electroluminescence element, a storage capacitor connected to a gate of the driving transistor, and the storage capacitor in series. A first transistor connected to control a timing for writing a data signal to the storage capacitor; and a first transistor connected in series between the driving transistor and the electroluminescence element to turn on and off a current flowing through the electroluminescence element. 2 transistors, and a third transistor connected in series to the opposite side of the storage capacitor with respect to the first transistor,
The electrical connection point of the first transistor and the third transistor and the electrical connection point of the driving transistor and the second transistor are short-circuited,
As the first transistor, a thin film transistor having an asymmetric structure in which the channel width dimension on the source region side and the channel width dimension on the drain region side are different, is used .
In the case where the asymmetric thin film transistor is an n-channel type, the smaller channel width dimension is arranged on the higher potential side when the thin film transistor is turned off in the source / drain region,
When the thin film transistor of the asymmetric structure of the p-channel type, of the source and drain regions, electro optics smaller channel width dimension for those a lower potential side when off the thin film transistor is characterized Rukoto disposed apparatus. In claim 1 , a plurality of types of electroluminescent elements corresponding to each color are formed as the electroluminescent elements.
In the pixel corresponding to any color, the source / drain region having the smaller channel width dimension is connected to the storage capacitor side or the larger channel width dimension is connected to the storage capacitor side. The electro-optical device is characterized in that they are the same. In claim 1 , a plurality of types of electroluminescent elements corresponding to each color are formed as the electroluminescent elements.
Of the source / drain regions, whether the smaller channel width dimension is connected to the storage capacitor side or the larger channel width dimension is connected to the storage capacitor side depends on the color corresponding to the pixel. An electro-optical device characterized by being different. In any one of claims 1 to 3, the thin film transistor of the asymmetric structure, the electro-optical device, characterized in that the active layer is composed of a low-temperature polysilicon film. In any one of claims 1 to 4, the thin film transistor of the asymmetric structure, the source region by a channel region, and a drain region are arranged concentrically in this order, the source region side of the channel width to the drain region side An electro-optical device having different channel widths. In any one of claims 1 to 4, the thin film transistor of the asymmetric structure, the source region by a channel region, and a drain region are arranged in an arc shape in this order, the channel width of the source region side and drain region side The electro-optical device is characterized in that the channel width dimensions are different. In any one of claims 1 to 4, the thin film transistor of the asymmetric structure is formed with a semiconductor film is triangular or trapezoidal shape in plan view, in its height direction, the source region, the channel region, and a drain region are arranged in this order Therefore, the channel width dimension on the source region side and the channel width dimension on the drain region side are different from each other. In any one of claims 1 to 7, the thin film transistor of the asymmetric structure, the electro-optical device characterized in that it comprises a double-gate structure. In any one of claims 1 to 8, the thin film transistor of the asymmetric structure, the electro-optical device characterized in that it comprises a LDD structure or offset gate structure. An electronic apparatus using the electro-optical device defined in any one of claims 1 to 9 .

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