JP4495924B2 - Interface circuit, electronic device, and medium storage device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an interface circuit, an electronic device, and a medium storage device for exchanging serial data using a serial line, and more particularly, a serial clock, enable, and serial for output control of serial data for transmission / reception of serial data. The present invention relates to an interface circuit for generating a pattern, an electronic device, and a medium storage device.
[0002]
[Prior art]
Due to recent advances in LSI technology, various circuits have been integrated into a single chip. Various electronic devices are configured by combining these LSI chips according to required functions. Such LSI chips include an LSI chip having a parallel bus interface for connection to an MPU and an LSI chip having a serial interface.
[0003]
In order to exchange data between the parallel interface LSI chip and the serial interface LSI chip, a method of providing an interface circuit between these LSIs is effective. This interface circuit synchronizes and outputs parallel data serially, and conversely outputs serial data in parallel.
[0004]
FIG. 10 is a configuration diagram of a conventional interface circuit, and FIGS. 11A and 11B are explanatory diagrams of serial output. As shown in FIG. 10, an interface circuit 100 is provided between a serial interface LSI chip 110 and a parallel interface LSI chip (not shown) for data transfer with the serial interface LSI chip 110.
[0005]
The serial interface 120 normally supplies a serial clock, enable, and address / data via a serial line. Therefore, the interface circuit 100 converts the serial data from the serial clock driver 102 and the enable signal driver 106 into serial data, outputs the serial data to the address / data line, and converts the serial data from the address / data line into the parallel data. And a bi-directional driver 104 for conversion into
[0006]
The serial output generation circuit 108 outputs a serial pattern for operating the drivers 102, 104, 106 in response to an external (LSI chip) serial output request. That is, as shown in FIG. 11A, in order to serially output 16-bit data “f” to “0”, first, the serial enable signal is made valid (low level in FIG. 11A), Next, a serial clock is generated, and in parallel with this, parallel data is converted into serial data and transmitted.
[0007]
Then, the serial clock is stopped by sending a predetermined number (16 bits) of serial data, and then the serial enable signal is disabled (high level in FIG. 11A).
[0008]
The transmitted LSI chip 110 recognizes that the data on the data line is valid by the serial enable signal, and determines each bit of the serial data by the serial clock. In FIG. 11A, data on the data line is determined at the falling edge of the serial clock.
[0009]
In order to output such serial clock, serial enable, and serial data, the serial output generation circuit 108 generates a serial pattern and drives the drivers 102, 104, and 106.
[0010]
Conventionally, since such a serial pattern is constant according to the specification of the other LSI chip 110, the serial output generation circuit is constituted by a wired logic circuit that generates this constant serial pattern.
[0011]
[Problems to be solved by the invention]
In recent years, various types of LSIs have been provided in abundance due to advances in LSI technology. For this reason, such LSIs are also provided that have slightly different serial pattern specifications depending on the type and specification change. For example, in the example of FIG. 11B, the serial enable signal is valid at a high level, and serial data is output so that the serial data is determined at the rising edge of the serial clock.
[0012]
When an LSI whose data is determined on the basis of the rising edge of the serial clock is connected to the interface in which the serial data is determined on the basis of the falling edge of the serial clock in FIG. 11A, the data as shown in “B” in FIG. Data is determined at the boundary between (bit) 3 and data (bit) 2. For this reason, any data is set in the register, and the set value may differ depending on the condition, and the data becomes indefinite.
[0013]
For this reason, it is necessary to generate a serial output pattern that matches the specifications of the LSI chip. However, in the prior art, a fixed serial pattern determined in advance is specified by a wired logic circuit. When the specification was changed, it was necessary to recreate this serial pattern generation circuit. For this reason, the development process such as the evaluation of a new LSI chip cannot be reduced, and there arises a problem that the revision cost increases due to remanufacturing.
[0014]
Accordingly, it is an object of the present invention to provide an interface circuit, an electronic device, and a medium storage device that can easily change the serial output pattern and conform to various serial interface specifications.
[0015]
Another object of the present invention is to provide an interface circuit, an electronic device, and a medium storage device for easily adapting to various serial interface specifications.
[0016]
Furthermore, another object of the present invention is to provide an interface circuit, an electronic device, and a medium storage device that can easily realize correction and debugging of a serial output pattern defect.
[0017]
[Means for Solving the Problems]
In order to achieve this object, in the interface circuit for synchronously outputting the serial clock, serial enable and serial data of the present invention, Each On the bus Connected to read register and write register Connected, Parallel day Store A pair of A register; a clock driver that outputs the serial clock to a clock line; an enable driver that outputs the serial enable to an enable line; and a serial data line, the serial data being output to the serial data line; A data driver for receiving the serial data from the data line, a serial pattern memory for storing the serial clock, the high / low bits of the serial enable, and the address of the register in successive memory addresses according to a serial output sequence; The memory address of the serial pattern memory is sequentially incremented, the clock driver is driven with the high / low bits of the serial clock of the memory, and the serial enable Drives said enable driver Lee / low bit, and a memory read circuit for driving the register address of the register, the serial pattern memory, To other electronic circuits Write serial pattern that defines the serial output sequence when writing data, and From the other electronic circuit Stores the read serial pattern that defines the serial output sequence when reading data, The memory The read circuit reads the write serial pattern and writes the address during the data write. To the one register to which parallel data is written from the bus of the pair of registers, the one register, Parallel data written from the bus is converted into serial data, and output from the data driver in synchronization with the serial clock and the serial enable, and at the time of data read, the read serial pattern is read, address Is output to the other of the pair of registers, and the other register The serial data received by the data driver in synchronization with the serial clock and the serial enable, The other The register is assembled into parallel data of the bus.
[0018]
The electronic device according to the present invention is an electronic device that transfers data from an interface circuit connected to one circuit via a bus to another circuit using a serial interface. Each On the bus Connected to read register and write register Connected, Parallel day Store A pair of Registers, Said A clock driver that outputs a serial clock to the clock line; Said An enable driver for outputting a serial enable to an enable line; a data driver connected to a serial data line; outputting the serial data to the serial data line; and receiving the serial data from the serial data line; and a serial output sequence The serial pattern memory for storing the serial clock, the high / low bit of the serial enable and the address of the register in successive memory addresses, and sequentially incrementing the memory address of the serial pattern memory, and the serial clock of the memory The high / low bit drives the clock driver, the serial enable high / low bit drives the enable driver, and the register address is used to register the register. And a memory read circuit for driving the motor, the serial pattern memory, To other circuit Write serial pattern defining the serial output sequence at the time of data write, From the other circuit Stores the read serial pattern that defines the serial output sequence when reading data, The memory The read circuit reads the write serial pattern and writes the address during the data write. To the one register to which parallel data is written from the bus of the pair of registers, the one register, Parallel data written from the bus is converted into serial data, and output from the data driver in synchronization with the serial clock and the serial enable, and at the time of data read, the read serial pattern is read, address Is output to the other of the pair of registers, and the other register The serial data received by the data driver in synchronization with the serial clock and the serial enable, The other The register is assembled into parallel data of the bus.
[0019]
In addition, a medium storage device that reads at least data from the medium of the present invention is connected to a control unit, a drive circuit that drives a mechanism unit of the medium storage device, and a parallel interface of the control unit. An interface circuit for outputting a clock, serial enable and serial data in synchronization with each other. Each On the bus Connected to read register and write register Connected, Parallel day Store A pair of A register; a clock driver that outputs the serial clock to a clock line; an enable driver that outputs the serial enable to an enable line; and a serial data line, the serial data being output to the serial data line; A data driver for receiving the serial data from the data line, a serial pattern memory for storing the serial clock, the high / low bits of the serial enable, and the address of the register in successive memory addresses according to a serial output sequence; The memory address of the serial pattern memory is sequentially incremented, the clock driver is driven with the high / low bits of the serial clock of the memory, and the serial enable Drives said enable driver Lee / low bit, and a memory read circuit for driving the register address of the register, the serial pattern memory, To the drive circuit Write serial pattern defining the serial output sequence at the time of data write, From the drive circuit Stores the read serial pattern that defines the serial output sequence when reading data, The memory The read circuit reads the write serial pattern and writes the address during the data write. To the one register to which parallel data is written from the bus of the pair of registers, the one register, Parallel data written from the bus is converted into serial data, and output from the data driver in synchronization with the serial clock and the serial enable, and at the time of data read, the read serial pattern is read, address Is output to the other of the pair of registers, and the other register The serial data received by the data driver in synchronization with the serial clock and the serial enable, The other The register is assembled into parallel data of the bus.
[0020]
In the present invention, a serial output pattern for controlling the timing of serial enable, serial clock, and serial data necessary for the serial interface is developed in a writable memory, the memory is incremented, and the serial output pattern is sequentially output. Controls the timing of serial enable, serial clock, and serial data required for data.
[0021]
For this reason, the serial output pattern can be easily changed, and the correction and debugging of the serial output pattern can be realized by changing the memory pattern. As a result, the development process of an electronic device using various LSI chips connected to the serial interface can be reduced, and the revision cost can be reduced.
[0022]
In the present invention, it is preferable that the memory stores a halt bit indicating the end of the serial output sequence, and the reading circuit stops reading of the memory according to the halt bit. Thereby, the stop of serial output can also be controlled.
[0023]
In the present invention, preferably, a write serial pattern defining the serial output sequence at the time of data writing and a read serial pattern defining the serial output sequence at the time of data reading are stored, and the reading circuit provides The write serial pattern and the read serial pattern are selected and read sequentially according to the start address.
[0024]
Thus, the write and read sequences can be individually serially controlled by setting the memory.
[0025]
In the present invention, it is preferable that the read serial pattern of the memory includes an input / output direction bit of the data driver and a read strobe bit of the read data. This further facilitates the sequence during reading.
[0026]
The present invention preferably further includes a clock selection circuit for selecting a base clock for sequentially incrementing the memory address. Thereby, the transfer rate can also be changed.
[0027]
In the present invention, it is preferable that the data driver further includes a read register configured by an input / output driver and assembling serial data from the data driver into parallel data. This facilitates read processing.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in the order of a medium storage device, an interface circuit, and other embodiments.
[0029]
[Media storage device]
FIG. 1 is a configuration diagram of a medium storage device according to an embodiment of the present invention. FIG. 1 shows an example of a magnetic disk device (HDD) that reads / writes data on a magnetic disk as a medium storage device. The magnetic disk device 10 is connected to a host 8 such as a personal computer via an ATA (AT Attachment) standard interface cable 9.
[0030]
The magnetic disk device 10 includes a magnetic disk 19, a spindle motor 20 that rotates the magnetic disk 19, a magnetic head 25 that reads / writes data on the magnetic disk 19, and the magnetic head 25 in the radial direction of the magnetic disk 19 (track crossing). And an actuator (VCM) 22 that moves in the direction).
[0031]
As control units, an HDC (Hard Disk Controller) 12, a data buffer 14, an MCU (Micro Control Unit) 11, a memory 13, a DSP (Digital Signal Processor) 15, and a read / write circuit (LSI) 16 are provided. , A drive interface circuit 17, a head IC 18, a servo driver 23 including a spindle motor driver and a VCM driver, a drive transistor (FET) 21, and a servo demodulation circuit 24.
[0032]
The HDC 12 has an ATA interface control circuit for communicating with the host and a data buffer control circuit for controlling the data buffer 14. The read / write circuit 16 controls the format of recording data.
[0033]
The head IC 18 sends a recording current to the magnetic head 25 according to the recording data during writing, and amplifies the read signal from the magnetic head 25 during reading, and outputs a read signal (including servo information). The servo demodulation circuit 24 demodulates the servo information from the head IC 18 via the read / write circuit 16 and detects the position of the magnetic head 25.
[0034]
The spindle driver of the servo driver 23 rotationally drives the spindle motor 20 via the drive transistor 21. The VCM driver of the servo driver 23 drives the VCM 22 that moves the magnetic head 25.
[0035]
The DSP 15 servo-controls the VCM 22 according to the detection position from the servo demodulation circuit 24. The MCU 11 performs read / write control and retry control. The memory 13 stores tables and data necessary for the processing of the MCU 11. The drive interface circuit 17 performs an interface between a magnetic disk drive system and a processing system. The data / address bus 26 connects the MCU 11, the memory 13, the HDC 12 and the drive interface circuit 17. The drive interface circuit 17 is also connected to the DSP 15.
[0036]
The drive interface circuit 17 is connected to the servo driver 23, the head IC 18, the servo demodulation circuit 24, and the read / write circuit 16 through each of the serial interface lines 27A to 27D, and performs address / data exchange through the serial interface.
[0037]
In FIG. 1, the drive interface circuit 17 performs P / S conversion and S / P between the parallel data MCU 11 and DSP 15, the serial data servo driver 23, the head IC 18, the servo demodulation circuit 24, and the read / write circuit 16. Perform conversion.
[0038]
[Interface circuit]
Next, the drive interface circuit of FIG. 1 will be described. 2 is a configuration diagram of the drive interface circuit of FIG. 1, FIG. 3 is a configuration diagram of the serial sequencer of FIG. 2, and FIG. 4 is an explanatory diagram of an operation procedure of the serial sequencer of FIG.
[0039]
As shown in FIG. 2, the interface circuit 17 is connected to the MCU 11 and the like through a parallel bus 26, and is connected to the servo driver 23 through serial lines 50, 51, and 52. Here, the servo driver 23 is shown as a serially connected LSI chip, but the servo demodulator circuit 24, the read / write circuit 16, and the head IC 18 are the same as shown in FIG.
[0040]
The interface circuit 17 converts the parallel data of the MCU 11 into serial data, writes it to the servo driver 23, converts the serial data of the servo driver 23 into parallel data, and the MCU 11 reads.
[0041]
The interface circuit 17 includes a write register 30 for storing write data from the bus 26, a conversion register 31 for converting parallel data in the write register 30 into serial data, and a bidirectional driver 32 connected to the conversion register 31. The assembly register 33 assembles serial data of the bidirectional driver 32 into parallel data, and a read register 34 in which parallel data of the assembly register 33 is set.
[0042]
The interface circuit 17 further includes a clock driver 35 that outputs a serial clock to the serial clock line 51, an enable driver 36 that outputs an enable signal to the enable line 52, and a serial sequencer 40 that generates a serial output pattern. .
[0043]
As shown in FIG. 3, the serial sequencer 40 is set with a memory 42 having a 16-bit width, a clock selector 43 for selecting a read clock (base clock) of the memory 42, and a start address of the memory 42. A read control circuit 41 for generating a read address of the memory 42 and sequentially reading stored data (serial output sequence data) having a 16-bit width from the memory 42.
[0044]
As 16-bit width storage data of the memory 42, bit 9 is an enable bit indicating the enable signal high and low, bit 8 is a read ready bit for notifying the MCU 11 of the read data read timing, and bit 7 is sequence data. Sets the halt bit that indicates the output stop of.
[0045]
Also, bit 6 is a clock bit indicating high and low of the serial clock, bit 5 is a direction bit indicating the data direction of the address / data line 50 (input / output of the bidirectional driver 32), and bit 4 is read. A read bit indicating the read strobe of the register 34 is set. Further, the addresses of the registers 31 and 33 are set in the bits 3 to 0, and the bits F to A are not used.
[0046]
As shown in FIG. 2, the enable bit output of the memory 42 is sent to the enable driver 36, the read ready bit output is sent to the MCU 11, the halt bit output is sent to the read control circuit 41 shown in FIG. The direction bit output is supplied to the driver 35, the read bit output is supplied to the read register 34, and the address output is supplied to the registers 31 and 33.
[0047]
As shown in FIG. 4, in the memory 42, the serial output sequence W1 at the time of writing is stored in, for example, a 16-bit width area at addresses 0 to 47, and the serial output sequence R1 at the time of reading is stored at addresses 48 to 96. To store. Here, the serial output sequence W2 at the time of writing of another serial interface is stored in a 16-bit width area below address 97, and the serial output sequence R2 at the time of reading is stored at subsequent addresses.
[0048]
The operation of this configuration will be described with reference to FIG. After the serial output pattern is stored in the memory 42, a serial output request command is issued from the MCU 11 to the serial sequencer 40, for example. This instruction is the clock selection signal and the start address shown in FIG.
[0049]
The read control circuit 41 sets the start address in the address counter, and reads out the memory 42 using the address counter. The address counter counts the base clock, increments the memory address, and sequentially outputs a 16-bit serial pattern from the memory 42. The read control circuit 41 receives the halt bit of the memory 42 and stops the counting of the address counter when detecting the halt by the halt bit. As a result, the output of the serial pattern is stopped.
[0050]
Furthermore, it demonstrates concretely. FIG. 5 is a time chart of serial output at the time of writing, and FIG. 6 is a bit map of the serial sequence pattern of the memory 42 set for serial output of FIG.
[0051]
FIG. 5 shows the relationship between the base clock, the serial clock output to the serial line 51, the enable signal output to the enable line 52, and 16-bit serial write data. For this purpose, the lower 12 bits of the 16-bit serial output pattern are displayed in 4-bit quaternary display and the corresponding memory address is displayed. FIG. 6 is a binary display of the serial output pattern of each memory address.
[0052]
Here, it is assumed that “00” is designated as the start address, and the memory address of the memory 42 in FIG. 6 is sequentially incremented according to the base clock. Thereby, the serial output pattern data of the memory 42 in FIG. 6 is sequentially read from the address 00 downward in the figure.
[0053]
Here, first, the serial enable signal is set to high (EN = 1, invalid) for two base clocks, and then the serial enable signal is set to low (EN = 0, valid). Next, at the memory address “03”, the direction DIR is set to high (data output), the serial clock CLK is set to high, the data address is set to “f”, and the bit of the address f in the register 31 is output from the bidirectional driver 50. .
[0054]
Next, at the memory address “04”, the serial clock CLK is set to low, the data address is set to “f”, and the bit of the address f in the register 31 is output from the bidirectional driver 50.
[0055]
That is, a serial clock is generated, and in parallel with this, parallel data is converted into serial data and transmitted. In this example, it corresponds to the specification of the servo driver 23 that determines data at the falling edge of the serial clock.
[0056]
Thereafter, the data address is changed by repeating high / low of the serial clock. As a result, transmission of a predetermined number (16 bits) of serial data (8-bit address + 8-bit data) in the register 31 is performed up to the memory address “34”. Then, the serial clock is stopped at the memory addresses “35” and “36” (CLK = 0), and then the serial enable signal is invalidated (EN = 1, high level) from the memory address “37”.
[0057]
Thereafter, after generating two serial clocks for the serial output end sequence, the memory address increment is stopped by the halt (HLT = 1) of the memory address “47”, and the serial output is ended.
[0058]
Next, the read operation will be described. FIG. 7 is a time chart of serial output at the time of reading, and FIG. 8 is a bit map of the serial sequence pattern of the memory 42 set for serial output of FIG.
[0059]
FIG. 7 shows the relationship between the base clock, the serial clock output to the serial line 51, the enable signal output to the enable line 52, the 8-bit serial read address, and the 8-bit read data. For this purpose, the lower 12 bits of the 16-bit serial output pattern are displayed in 4-bit quaternary display and the corresponding memory address is displayed. FIG. 8 is a binary display of the serial output pattern of each memory address.
[0060]
Here, it is assumed that “48” is designated as the start address, and the memory address of the memory 42 in FIG. 8 is sequentially incremented according to the base clock. As a result, the serial output pattern data of the memory 42 in FIG. 8 is sequentially read from the address 48 downward in the figure.
[0061]
Here, first, the serial enable signal is set to high (EN = 1, invalid) for two base clocks, and then the serial enable signal is set to low (EN = 0, valid). Next, at the memory address “03”, the direction DIR is set to high (data output), the serial clock CLK is set to high, the data address is set to “f”, and the bit of the address f in the register 31 is output from the bidirectional driver 50. .
[0062]
Next, at the memory address “04”, the serial clock CLK is set to low, the data address is set to “f”, and the bit of the address f in the register 31 is output from the bidirectional driver 50.
[0063]
That is, a serial clock is generated, and in synchronization with this, 8-bit parallel data in the register 31 is converted into serial data and transmitted. In this example, it corresponds to the specification of the servo driver 23 that determines data at the falling edge of the serial clock.
[0064]
Thereafter, the data address is changed by repeating high / low of the serial clock. As a result, the predetermined number (8-bit address) of the register 31 is transmitted up to the memory address “67”.
[0065]
Next, at the memory address “68”, the direction DIR is set to low (data input), and the bidirectional register 50 is switched to input. Next, at the memory address “69”, the direction DIR is kept low, the serial clock CLK is high, the data address is “7”, and the serial data from the bidirectional driver 50 is set to the address “7” of the register 33. Output to.
[0066]
Next, at the memory address “70”, the serial clock CLK is set to low, the data address is set to “7”, and the serial data is stored from the bidirectional driver 50 to the address “7” of the register 33.
[0067]
That is, a serial clock is generated, and 8-bit serial data is stored in the register 33 in synchronization therewith. In this example, it corresponds to the specification of the servo driver 23 that determines data at the falling edge of the serial clock.
[0068]
Thereafter, the data address is changed by repeating high / low of the serial clock. As a result, a predetermined number (8-bit address) is sent to the register 33 up to the memory address “84”. Then, at the memory address “85”, the serial clock is stopped, the read strobe is set high (RR = 1), and the data of the 16-bit register 33 is set in the read register 34. Thereafter, the serial enable signal is invalidated (EN = 1, high level) from the memory address “86”.
[0069]
Thereafter, after generating two serial clocks for the serial output end sequence, the memory address increment is stopped by halting the memory address “96” (HLT = 1), and the serial output is ended.
[0070]
In this way, the serial output pattern that controls the serial enable, serial clock, and serial data timing required for the serial interface is expanded to a writable memory, the memory is incremented, and the serial output pattern is sequentially output to the serial interface. Controls the timing of serial enable, serial clock, and serial data required for data.
[0071]
For this reason, the serial output pattern can be easily changed, and the correction and debugging of the serial output pattern can be realized by changing the memory pattern. As a result, the development process of an electronic device using various LSI chips connected to the serial interface can be reduced, and the revision cost can be reduced.
[0072]
Further, different patterns can be set for writing and reading, and reading / writing can be performed with a serial interface suitable for the LSI chip to be connected. Further, since the base clock can be selected, the operation clock for serial output can be changed by making the base clock variable. That is, the interface speed can be easily changed.
[0073]
In addition, the ratio between the address part and the data part of the serial read output can be made variable by changing the direction DIR of the memory 42 and the read strobe RR. Further, the length (number of bits) of the serial output can be changed by changing the length of the data portion.
[0074]
[Other embodiments]
FIG. 9 is a configuration diagram of another embodiment of the present invention. In this example, the memory 42 of the serial sequencer 40 stores one type of write / read serial output pattern. On the other hand, the memory 11 of the MCU 11 stores a plurality of types of write / read serial output patterns.
[0075]
A setting board 60 is provided on the printed board on which the circuit of FIG. 1 is mounted, and the type is set according to the specifications of the mounted servo driver 23 and the like. The MCU 11 reads this setting pin 60, automatically recognizes the connected serial interface specification, reads the corresponding write / read serial output pattern from the memory 13, and loads it into the memory 42 of the serial sequencer 40.
[0076]
Thereby, the interface circuit 17 can automatically have a serial output pattern generation circuit of the serial interface specification of the LSI chip to be connected.
[0077]
In the above-described embodiment, the medium of the medium storage device has been described as a magnetic disk. However, the present invention can also be applied to an optical disk, a magneto-optical disk, and other storage media. Further, although the electronic device has been described with the hard disk control unit, it can be applied to other electronic devices such as other control units. Furthermore, the interface is not limited to ATA, and can be applied to other interfaces.
[0078]
As mentioned above, although this invention was demonstrated by embodiment, in the range of the meaning of this invention, this invention can be variously deformed, These are not excluded from the scope of the present invention.
[0079]
(Supplementary Note 1) In an interface circuit that outputs serial clock, serial enable, and serial data in synchronization, a register that stores the data, a clock driver that outputs the serial clock to a clock line, and the serial enable as an enable line An enable driver for outputting, a data driver for outputting the serial data to a data line, and a serial for storing the serial clock, the high / low bits of the serial enable, and the address of the register in successive memory addresses according to a serial output sequence The memory address of the pattern memory and the serial pattern memory is sequentially incremented, and the clock driver is driven by the high / low bits of the serial clock of the memory The drives said enable driver serial enable high / low bit, interface circuit and having a memory reading circuit for driving the register address of the register.
[0080]
(Supplementary note 2) The interface according to supplementary note 1, wherein the memory stores a halt bit indicating the end of the serial output sequence, and the reading circuit stops reading of the memory according to the halt bit. circuit.
[0081]
(Supplementary Note 3) A write serial pattern that defines the serial output sequence at the time of data write and a read serial pattern that defines the serial output sequence at the time of data read are stored, and the read circuit receives the given start address Accordingly, the interface circuit according to appendix 1, wherein the write serial pattern and the read serial pattern are selected and read sequentially.
[0082]
(Supplementary note 4) The interface circuit according to supplementary note 3, wherein the read serial pattern of the memory includes an input / output direction bit of the data driver and a read strobe bit of the read data.
[0083]
(Supplementary note 5) The interface circuit according to supplementary note 1, further comprising a clock selection circuit for selecting a base clock for sequentially incrementing the memory address.
[0084]
(Supplementary note 6) The interface circuit according to supplementary note 4, wherein the data driver further includes a read register configured by an input / output driver and assembling serial data from the data driver into parallel data.
[0085]
(Supplementary Note 7) In an electronic device that transfers data from an interface circuit to another circuit through a serial interface, the interface circuit includes a register that stores the data, a clock driver that outputs a serial clock to a clock line, and a serial enable The enable driver that outputs to the enable line, the data driver that outputs serial data to the data line, and the serial clock, the serial enable high / low bits, and the register address are stored in successive memory addresses according to the serial output sequence. Serial pattern memory and the memory address of the serial pattern memory are sequentially incremented, and the clock driver is activated by the high / low bits of the serial clock of the memory. Dynamic and, the drives said enable driver serial enable high / low bit, the electronic apparatus characterized by having a memory reading circuit for driving the register address of the register.
[0086]
(Supplementary note 8) The electronic device according to supplementary note 7, wherein the memory stores a halt bit indicating the end of the serial output sequence, and the reading circuit stops reading of the memory according to the halt bit. apparatus.
[0087]
(Supplementary Note 9) A write serial pattern that defines the serial output sequence at the time of data write and a read serial pattern that defines the serial output sequence at the time of data read are stored, and the read circuit receives the given start address Accordingly, the electronic device according to appendix 7, wherein the write serial pattern and the read serial pattern are selected and read sequentially.
[0088]
(Supplementary note 10) The electronic device according to supplementary note 9, wherein the read serial pattern of the memory includes an input / output direction bit of the data driver and a read strobe bit of the read data.
[0089]
(Supplementary note 11) The electronic device according to Supplementary note 7, further comprising a clock selection circuit for selecting a base clock for sequentially incrementing the memory address.
[0090]
(Supplementary note 12) The electronic device according to supplementary note 10, wherein the data driver further includes a read register configured by an input / output driver and assembling serial data from the data driver into parallel data.
[0091]
(Supplementary Note 13) In a medium storage device that reads at least data from a medium, the control unit, a drive circuit that drives a mechanism unit of the medium storage device, and a parallel interface of the control unit are connected to the drive circuit. And an interface circuit for outputting serial enable and serial data in synchronization, the interface circuit enabling a register for storing the data, a clock driver for outputting the serial clock to a clock line, and enabling the serial enable. An enable driver for outputting to the line; a data driver for outputting the serial data to the data line; and a serial output sequence, the serial clock and the serial enable high / low Serial pattern memory for storing the address of the register and the register, the memory address of the serial pattern memory are sequentially incremented, the clock driver is driven by the high / low bits of the serial clock of the memory, and the serial enable high / low And a memory read circuit for driving the enable driver with a low bit and driving the register with an address of the register.
[0092]
(Supplementary note 14) The medium according to supplementary note 13, wherein the memory stores a halt bit indicating the end of the serial output sequence, and the reading circuit stops reading of the memory according to the halt bit. Storage device.
[0093]
(Supplementary Note 15) A write serial pattern that defines the serial output sequence at the time of data write and a read serial pattern that defines the serial output sequence at the time of data read are stored, and the read circuit receives the given start address Accordingly, the medium storage device according to appendix 13, wherein the write serial pattern and the read serial pattern are selected and read sequentially.
[0094]
(Supplementary note 16) The medium storage device according to supplementary note 15, wherein the read serial pattern of the memory includes an input / output direction bit of the data driver and a read strobe bit of the read data.
[0095]
(Supplementary note 17) The medium storage device according to supplementary note 13, further comprising a clock selection circuit for selecting a base clock for sequentially incrementing the memory address.
[0096]
(Supplementary note 18) The medium storage device according to supplementary note 16, wherein the data driver is configured by an input / output driver and further includes a read register for assembling serial data from the data driver into parallel data.
[0097]
【The invention's effect】
As described above, in the present invention, a serial output pattern for controlling the timing of serial enable, serial clock, and serial data necessary for the serial interface is developed in a writable memory, the memory is incremented, and the serial output pattern is sequentially output. It controls the timing of serial enable, serial clock, and serial data required for the serial interface.
[0098]
For this reason, the serial output pattern can be easily changed, and the correction and debugging of the serial output pattern can be realized by changing the memory pattern. As a result, the development process of an electronic device using various LSI chips connected to the serial interface can be reduced, and the revision cost can be reduced.
[0099]
In addition, the development of a medium storage device having a drive interface for connecting a plurality of LSIs through a serial interface can be facilitated, and various LSIs can be specified, contributing to further cost reduction.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a medium storage device according to an embodiment of the present invention.
FIG. 2 is a configuration diagram of the drive interface circuit of FIG. 1;
FIG. 3 is a configuration diagram of the serial sequencer of FIG. 2;
4 is an operation explanatory diagram of the serial sequencer of FIG. 3;
5 is a time chart diagram of a write sequence of the drive interface circuit of FIG. 2. FIG.
6 is an explanatory diagram of a memory serial output pattern for the write sequence of FIG. 5;
7 is a time chart diagram of a read sequence of the drive interface circuit of FIG. 2; FIG.
8 is an explanatory diagram of a serial output pattern of the memory for the read sequence of FIG. 7;
FIG. 9 is a configuration diagram of another embodiment of the present invention.
FIG. 10 is a configuration diagram of a conventional serial interface circuit.
FIG. 11 is a time chart diagram of a conventional serial interface.
[Explanation of symbols]
8 Host
9 ATA interface
10 Medium storage device (magnetic disk device)
11 MCU (processing unit)
12 HDC
13 memory
14 Data buffer
15 DSP
16 Read / write LSI
17 Drive interface circuit
18 head IC
19 Medium (Magnetic Disk)
20 Spindle motor
22 Actuator (VCM)
23 Servo driver
24 Servo demodulation circuit
25 head (magnetic head)
26 Bus
27A-27D serial line
30, 31, 33, 34 registers
32 bidirectional driver
35, 36 output driver
40 Serial sequencer
41 Read control circuit
42 memory
43 Clock selector
50-52 serial line

Claims (7)

In the interface circuit that outputs serial clock, serial enable and serial data synchronously,
Each read register connected to the bus, is connected to the write register, and a pair of registers for storing the parallel data,
A clock driver for outputting the serial clock to a clock line;
An enable driver for outputting the serial enable to an enable line;
A data driver connected to a serial data line, outputting the serial data to the serial data line, and receiving the serial data from the serial data line;
A serial pattern memory for storing the serial clock, the high / low bits of the serial enable and the address of the register in successive memory addresses according to a serial output sequence;
The memory address of the serial pattern memory is sequentially incremented, the clock driver is driven with the high / low bits of the serial clock of the memory, the enable driver is driven with the high / low bits of the serial enable, and the address of the register A memory read circuit for driving the register;
The serial pattern memory includes a write serial pattern that defines the serial output sequence when data is written to another electronic circuit, and a read serial pattern that defines the serial output sequence when data is read from the other electronic circuit. Store
The memory read circuit reads the write serial pattern at the time of the data write, and outputs the address to one register to which parallel data is written from the bus of the pair of registers. Parallel data written from the bus is converted into serial data, and the data driver outputs the data in synchronization with the serial clock and the serial enable.
At the time of data read, the read serial pattern is read and the address is output to the other of the pair of registers, and the other register receives the data driver in synchronization with the serial clock and the serial enable. The serial data is assembled into parallel data of the bus in the other register. The interface circuit according to claim 1, wherein the memory stores a halt bit indicating the end of the serial output sequence, and the reading circuit stops reading of the memory in accordance with the halt bit. 2. The interface circuit according to claim 1, wherein the memory read circuit selects one of the write serial pattern and the read serial pattern from the serial pattern memory according to a given start address, and sequentially reads the selected one. . In an electronic device for transferring data from an interface circuit connected to one circuit to another circuit via a serial interface,
The interface circuit is
Each read register connected to the bus, is connected to the write register, and a pair of registers for storing the parallel data,
A clock driver for outputting the serial clock to a clock line,
And enable a driver for outputting the serial enable the enable line,
A data driver connected to a serial data line, outputting the serial data to the serial data line, and receiving the serial data from the serial data line;
A serial pattern memory for storing the serial clock, the high / low bits of the serial enable and the address of the register in successive memory addresses according to a serial output sequence;
The memory address of the serial pattern memory is sequentially incremented, the clock driver is driven with the high / low bits of the serial clock of the memory, the enable driver is driven with the high / low bits of the serial enable, and the address of the register A memory read circuit for driving the register;
The serial pattern memory includes a write serial pattern that defines the serial output sequence when data is written to the other circuit, and a read serial pattern that defines the serial output sequence when data is read from the other circuit. Store and
The memory read circuit reads the write serial pattern at the time of the data write, and outputs the address to one register to which parallel data is written from the bus of the pair of registers. Parallel data written from the bus is converted into serial data, and the data driver outputs the data in synchronization with the serial clock and the serial enable.
At the time of data read, the read serial pattern is read and the address is output to the other of the pair of registers, and the other register receives the data driver in synchronization with the serial clock and the serial enable. The electronic data is assembled into parallel data of the bus in the other register. In a medium storage device that reads at least data from a medium,
A control unit;
A drive circuit for driving the mechanism of the medium storage device;
An interface circuit connected to a parallel interface of the control unit, and outputting to the drive circuit a serial clock, serial enable and serial data in synchronization;
The interface circuit is
Each read register connected to the bus, is connected to the write register, and a pair of registers for storing the parallel data,
A clock driver for outputting the serial clock to a clock line;
An enable driver for outputting the serial enable to an enable line;
A data driver connected to a serial data line, outputting the serial data to the serial data line, and receiving the serial data from the serial data line;
A serial pattern memory for storing the serial clock, the high / low bits of the serial enable and the address of the register in successive memory addresses according to a serial output sequence;
The memory address of the serial pattern memory is sequentially incremented, the clock driver is driven with the high / low bits of the serial clock of the memory, the enable driver is driven with the high / low bits of the serial enable, and the address of the register A memory read circuit for driving the register;
The serial pattern memory stores a write serial pattern that defines the serial output sequence when data is written to the drive circuit, and a read serial pattern that defines the serial output sequence when data is read from the drive circuit. ,
The memory read circuit reads the write serial pattern at the time of the data write, and outputs the address to one register to which parallel data is written from the bus of the pair of registers. Parallel data written from the bus is converted into serial data, and the data driver outputs the data in synchronization with the serial clock and the serial enable.
At the time of data read, the read serial pattern is read and the address is output to the other of the pair of registers, and the other register receives the data driver in synchronization with the serial clock and the serial enable. The serial data is assembled into the parallel data of the bus in the other register. The data driver is composed of an input / output driver,
The interface circuit according to claim 1, wherein the read serial pattern of the memory includes an input / output direction bit of the data driver. A clock selection circuit for selecting a base clock for sequentially incrementing a memory address of the memory;
The interface circuit according to claim 1, wherein the clock selection circuit selects a base clock for incrementing the memory in response to an operation request.

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