JP4490525B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an LSI manufacturing process, and more particularly to a contact hole structure and a manufacturing process in a mixed technology of a large-capacity memory in consideration of randomness and logic and repeated portions of the same pattern.
[0002]
[Prior art]
Hereinafter, a conventional memory-embedded logic process will be described by taking up to a one-layer wiring process as an example.
Here, the area A displayed below represents the process of the memory unit, and the area B represents the process of the logic unit.
First, as shown in FIG. 16, a thin silicon oxide film 32 of, eg, 10 nm is formed on a p-type silicon substrate 31 by thermal oxidation, and polycrystalline silicon 33 is formed thereon by LP-CVD (low pressure CVD). A 200 nm-thick silicon oxide film 34 is formed thereon by LP-CVD.
Thereafter, an element isolation region formation scheduled region by STI (shallow trench isolation) is patterned with a resist 35 by photolithography. Here, STI is formed by digging a groove in a semiconductor substrate, filling the groove with a CVD oxide film such as TEOS or polycrystalline silicon, and planarizing the surface by CMP.
Next, as shown in FIG. 17, the silicon oxide film 34 is etched by anisotropic dry etching having a selection ratio with respect to the polycrystalline silicon film using the pattern of the resist 35 as a mask, and the resist 35 is peeled off. .
Using the remaining silicon oxide film 36 as a mask, the polycrystalline silicon 37 obtained by etching the polycrystalline silicon 33 and the silicon oxide film 34 are etched by anisotropic dry etching that can sufficiently select the oxide film. A silicon oxide film 38 is formed by etching the silicon oxide film 36 and the silicon oxide film 32 which is a thin thermal oxide film.
[0003]
Next, as shown in FIG. 18, the silicon substrate 31 is etched by, for example, 0.5 μm by anisotropic dry etching with a sufficient selection ratio with respect to the oxide film to form the STI groove 39.
Next, as shown in FIG. 19, a silicon oxide film 40 is deposited to a thickness of 1.5 μm by LP-CVD. Thereafter, the silicon oxide film 40 is planarized by a chemical mechanical polishing (CMP) method having a selection ratio with respect to polycrystalline silicon. After planarization, the silicon oxide film 36 and the silicon oxide film 40 are etched by NH4F or dry etching until the polycrystalline silicon 37 is just exposed.
Next, as shown in FIG. 20, the polycrystalline silicon 37 is etched by isotropic dry etching that allows a selection ratio to the silicon oxide film, and heat treatment for reducing the film stress of the buried silicon oxide film 40 is performed, for example. Perform at 1000 ° C.
Thereafter, the silicon oxide film 38 on the silicon substrate 31 is etched with NH4F.
Thereafter, a silicon oxide film 41 is formed, for example, by thermal oxidation at 800 ° C., and B (boron) is implanted at an acceleration voltage of 200 KeV, for example, at an acceleration voltage of 200 KeV to form a P well region 42 to form a P well region.
[0004]
Further, for controlling the threshold value of the nMOSFET, B (boron) is implanted at a dose of 1E13 cm.sup.-2 at an acceleration voltage of 50 KeV, for example. Thereafter, the introduced impurities were activated by heat treatment at 1000 ° C. for 30 seconds.
Next, as shown in FIG. 21, the thermal oxide film on the surface of the silicon substrate such as the silicon oxide film 41 is removed, and a gate insulating film 43 is formed to a thickness of 6 nm by a thermal oxidation method at 750.degree. Thereafter, 300 nm of polycrystalline Si is deposited by LP-CVD. Thereafter, a resist pattern 45 of the gate electrode is formed by photolithography, and the gate electrode 46 is formed by anisotropic dry etching that can take a sufficient selectivity with respect to the silicon oxide film.
Next, as shown in FIG. 22, a silicon oxide film of, eg, 5 nm is formed on the silicon substrate by a thermal oxidation method at 800.degree. Thereafter, As is ion-implanted with a dose of 2E14 cm @ -2 at an acceleration voltage of 35 KeV, and a shallow diffusion layer 47 (shallow extension) is formed by heat treatment for 30 seconds in a 1000 DEG C. N2 atmosphere.
Next, as shown in FIG. 23, a silicon nitride film SiN having a thickness of 150 nm is deposited on the semiconductor substrate by LP-CVD, and the gate sidewall 48 is formed by anisotropic etching with a silicon oxide film and an etching selection ratio. Form. Thereafter, for example, As is ion-implanted with an acceleration voltage of 60 KeV and a dose of 5E15 cm −2, using the gate 46 and the gate side wall 48 as a mask, and heat treatment for 30 seconds at 1000 ° C. in N 2 atmosphere. A drain diffusion layer 49 is formed around the ion-implanted region. For this reason, a region that is not ion-implanted with the gate 46 and the gate sidewall 48 as a mask remains as a shallow diffusion layer 47. Thereafter, the gate electrode 46 is doped n +.
[0005]
Next, as shown in FIG. 24, the silicon oxide film 43 on the deep source / drain diffusion layer 49 is removed with NH 4 F to form a region where the refractory metal is removed. Titanium nitride (Ti / TiN) is deposited at 30/20 nm, respectively. Thereafter, heat treatment is performed for 30 seconds in an N 2 atmosphere at 700 ° C. to remove silicon Si and unreacted titanium Ti in a mixed solution of sulfuric acid and hydrogen peroxide. Thereafter, heat treatment is performed in an N 2 atmosphere at 800 ° C. for 30 seconds to form a low-resistance Ti silicide compound 50.
Next, as shown in FIG. 25, a silicon nitride film SiN54 is deposited by LP-CVD.
Thereafter, a BPSG film of 100 nm or a silicon oxide film of 900 nm is deposited as the interlayer insulating film 51 and planarized by CMP (chemical / mechanical polishing method).
Next, as shown in FIG. 26, a contact resist pattern is formed by photolithography, and the interlayer insulating film 51 is removed by anisotropic etching that has an etching selectivity with respect to silicon nitride SiN, and a contact hole is to be formed. Open the area.
Next, as shown in FIG. 27, for example, Ti, which is a refractory metal, is sputtered so as to be deposited to a thickness of 10 nm at the bottom of the contact. Thereafter, for example, heat treatment is performed for 30 minutes in an N 2 atmosphere at 600 ° C. to form titanium nitride TiN on the Ti surface. Thereafter, using this titanium nitride as a starting point for selective growth, tungsten W is deposited to a thickness of 400 nm by the CVD method. Then, W on the interlayer insulating film 51 is removed by the CMP method, and a buried wiring 52 of W is formed in the contact opening. Form. Thereafter, AlCu is deposited at 400 nm and Ti / TiN is deposited at 5/60 nm, a resist pattern is formed by photolithography, and Al wiring 53 is formed by anisotropic etching using this as a mask.
[0006]
[Problems to be solved by the invention]
As described above, the MOSFET having the salicide of the prior art can be formed. However, in the prior art shown in FIG. 27, the memory part (repeated pattern part) in FIG. 27 and the logic part in part (B) are shown. Only the same lithography technique can be applied to (a highly random pattern portion). With recent progress in lithography technology development, remarkable progress has been made until a fine pattern having a wavelength equal to or smaller than the wavelength of light can be formed by shortening the wavelength of light and using a phase shift for the reticle pattern. However, in this way, in the fine pattern formation technology that also uses the interference effect of light, the optical proximity effect is obtained by repeating a pattern limited in the memory part and a highly random contact hole in the logic part. It is difficult to realize a contact that can form a finer contact by the same lithography process. For this reason, even in a logic process in which a memory is embedded, it is difficult to achieve a fine contact diameter only in the memory section, and the contact diameter of the logic section and the memory section must be made the same, which is required for a logic LSI. This is a major obstacle to realizing a highly integrated memory.
[0007]
In addition, microfabrication of the pattern can be realized by performing the above lithography process separately in the memory part and the logic part. However, in the lithography process, there is always a misalignment of the transfer pattern when transferring the pattern onto the semiconductor substrate. Therefore, in contrast to the case where contact holes are formed in the same lithography step, it is necessary to reflect this misalignment in the wiring design in the next wiring process, which is contrary to miniaturization.
In addition, performing the processes of the memory unit and the logic unit separately complicates the manufacturing process and causes a significant increase in the number of processes. An object of the present invention is to solve such problems of the prior art.
An object of the present invention is to provide a method for manufacturing a memory-embedded logic in which the contact hole process of a memory part and a logic part is unified and the number of processes is reduced. Another object of the present invention is to provide a method for manufacturing a memory-embedded logic in which elements are highly integrated.
[0008]
[Means for Solving the Problems]
According to one aspect of the present invention, a step of forming a semiconductor substrate region having a memory formation scheduled region and a logic formation scheduled region , wherein a plurality of semiconductor device formation scheduled regions in the memory formation scheduled region are formed in the semiconductor substrate region. Forming a first element isolation region for isolating a plurality of semiconductor device formation scheduled regions in the logic formation planned region in the semiconductor substrate region, and forming a second element isolation region in the semiconductor substrate region. A step of forming a third element isolation region for separating the memory formation planned region and the logic formation planned region, and forming a first first conductivity type region in a semiconductor substrate region to be the memory formation planned region, Simultaneously forming a second first conductivity type region in the semiconductor substrate region to be the logic formation planned region, the first first conductivity type region, and the second first conductivity type. Applying a gate oxide film on the mold region; forming a plurality of gates in the plurality of semiconductor device formation scheduled regions in the memory formation scheduled region; and forming the plurality of semiconductor devices in the logic formation scheduled region Forming a plurality of second gates in the region; forming a first second conductivity type impurity diffusion region in a part of the first first conductivity type region; and Forming a second second conductivity type impurity diffusion region in a part of the mold region, forming a first gate sidewall insulating film on the sidewall of the first gate, and forming a first gate sidewall insulating film on the sidewall of the second gate. Forming a second gate sidewall insulating film; on the first gate; on the second gate; on the impurity diffusion region of the first second conductivity type; and on the second second conductivity type. Forming an interlayer insulating film on the impurity diffusion region; and the first second The interlayer insulating film provided on the electric type impurity diffusion region and a part of the first gate sidewall insulating film are removed until the first second conductivity type impurity diffusion region is exposed, and the first contact is removed. Simultaneously with the step of forming a hole and the step of forming the first contact hole, an interlayer insulating film buried on the impurity diffusion region of the second second conductivity type is formed with the impurity of the second second conductivity type. Removing the diffusion region until it is exposed, forming a second contact hole equal to the contact diameter of the first contact hole, and the bottom and side portions of the first contact hole, the second contact hole A step of forming an insulating film on the bottom and side portions, and the surface of the interlayer insulating film; a step of removing the insulating film leaving only the insulating film on the side surface portion of the first contact hole; There is provided a method of manufacturing a semiconductor device comprising a first contact hole and a step of forming a wiring in the second contact hole.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a logic process used for memory embedding according to an embodiment of the present invention will be described.
Here, the area A displayed below represents the process of the memory unit, and the area B represents the process of the logic unit.
First, as shown in FIG. 2, a thin silicon oxide film 2 of, eg, 10 nm is formed on a p-type silicon substrate 1 by thermal oxidation, and a polycrystalline silicon 3 is formed thereon by LP-CVD (low pressure CVD). A 200 nm thick silicon oxide film 4 is formed thereon by LP-CVD.
Thereafter, an element isolation region formation scheduled region by STI is patterned with a resist 5 by photolithography.
Next, as shown in FIG. 3, the silicon oxide film 4 is etched by anisotropic dry etching having a selectivity with respect to the polycrystalline silicon film using the pattern of the resist 5 as a mask, and the resist 5 is peeled off.
By using the remaining silicon oxide film 6 as a mask, the polycrystalline silicon 7 obtained by etching the polycrystalline silicon 3 and the silicon oxide film 4 are etched by anisotropic dry etching that can have a sufficient selectivity with respect to the oxide film. A silicon oxide film 8 is formed by etching the silicon oxide film 6 and the silicon oxide film 2 which is a thin thermal oxide film.
[0010]
Next, as shown in FIG. 4, the silicon substrate 1 is etched by, for example, 0.5 μm by anisotropic dry etching with a sufficient selectivity with respect to the oxide film, thereby forming the STI trench 9.
Next, as shown in FIG. 5, a silicon oxide film 10 is deposited to a thickness of 1.5 μm by LP-CVD. Thereafter, the silicon oxide film 10 is planarized by a chemical mechanical polishing (CMP) method having a selection ratio with respect to polycrystalline silicon. After planarization, the silicon oxide film 6 and the silicon oxide film 10 are etched by NH4F or dry etching until the polycrystalline silicon 7 is just exposed.
Next, as shown in FIG. 6, the polycrystalline silicon 7 is etched by isotropic dry etching with a selective ratio with respect to the silicon oxide film 2, and heat treatment for reducing the film stress of the buried silicon oxide film 10 is performed. Is performed at 1000 ° C., for example.
Thereafter, the silicon oxide film 8 on the silicon substrate 1 is etched with NH4F.
Thereafter, the silicon oxide film 11 is formed by thermal oxidation at, for example, 800 ° C., and B (boron) is implanted at an acceleration voltage of 200 KeV, for example, at an acceleration voltage of 200 KeV to form a P well region 12 for forming a P well region.
[0011]
Further, for controlling the threshold value of the nMOSFET, B (boron) is implanted at a dose of 1E13 cm.sup.-2 at an acceleration voltage of 50 KeV, for example. Thereafter, the introduced impurities were activated by heat treatment at 1000 ° C. for 30 seconds.
Next, as shown in FIG. 7, the thermal oxide film on the surface of the silicon substrate such as the silicon oxide film 11 is removed, and the gate insulating film 13 is formed with a thickness of 6 nm by a thermal oxidation method at 750.degree. Thereafter, 300 nm of polycrystalline Si is deposited by LP-CVD. Thereafter, a resist pattern 15 of the gate electrode is formed by photolithography, and the gate electrode 16 is formed by anisotropic dry etching that can take a sufficient selectivity with respect to the silicon oxide film.
Next, as shown in FIG. 8, a silicon oxide film of, eg, 5 nm is formed on the silicon substrate by a thermal oxidation method at 800.degree. Thereafter, As is ion-implanted with a dose of 2E14 cm @ -2 at an acceleration voltage of 35 KeV, and a shallow diffusion layer 17 is formed by heat treatment for 30 seconds in a 1000 DEG C. N2 atmosphere.
Next, as shown in FIG. 9, a silicon nitride film SiN of 150 nm is deposited on the semiconductor substrate by LP-CVD, and the gate sidewall 18 is formed by anisotropic etching with a silicon oxide film and an etching selection ratio. Form. Thereafter, for example, As is ion-implanted at an acceleration voltage of 60 KeV and a dose of 5E15 cm.sup.-2 using the gate 16 and the gate sidewall 18 as a mask, and heat treatment is performed at 1000.degree. A drain diffusion layer 19 is formed around the ion-implanted region. For this reason, the region not ion-implanted with the gate 16 and the gate sidewall 18 as a mask remains as a shallow diffusion layer 17. Thereafter, the gate electrode 16 is doped to n +.
[0012]
Next, as shown in FIG. 10, the deep source / drain diffusion layer 19 and the silicon oxide film 13 on the Si of the gate electrode are removed with NH 4 F to form a region where the refractory metal has been removed. Titanium and titanium nitride (Ti / TiN) are deposited as melting point metals at 30/20 nm, respectively. Thereafter, heat treatment is performed for 30 seconds in an N 2 atmosphere at 700 ° C. to remove silicon Si and unreacted titanium Ti in a mixed solution of sulfuric acid and hydrogen peroxide. Thereafter, heat treatment is performed for 30 seconds in an N 2 atmosphere at 800 ° C. to form a low-resistance Ti silicide compound 20.
Next, as shown in FIG. 11, a silicon nitride film SiN24 is deposited by LP-CVD.
Thereafter, a BPSG film of 100 nm or a silicon oxide film of 900 nm is deposited as the interlayer insulating film 21 and planarized by CMP (chemical / mechanical polishing method).
Next, as shown in FIG. 12, a contact resist pattern is formed by photolithography, and the interlayer insulating film 21 is removed by anisotropic etching having an etching selectivity with respect to silicon nitride SiN, thereby forming a contact hole. Open the area.
Next, as shown in FIG. 13, after opening the contact hole in the interlayer insulating film 21, silicon nitride SiN25 is deposited, for example, by 20 nm on the front surface by LPCVD.
[0013]
Next, as shown in FIG. 14, the silicon nitride film 25 is removed by etching by isotropic etching using a resist pattern 26 formed by photolithography only in the region B as a mask.
Next, as shown in FIG. 15, the resist pattern 26 is peeled off, and anisotropic etching with an etching selection ratio with respect to the silicon oxide film, silicon Si, and silicide is performed to form the bottom of the contact opening in the logic portion. The silicon nitride film 25 is peeled off, and at the same time, a contact hole is opened on the side wall of the memory portion leaving the silicon nitride film 25.
Next, as shown in FIG. 1, for example, titanium Ti, which is a refractory metal, is sputtered so as to be deposited to 10 nm at the bottom of the contact hole. Here, illustration of titanium is omitted. Thereafter, heat treatment is performed for 30 minutes in an N 2 atmosphere at 600 ° C., for example, to form titanium nitride TiN on the Ti surface at the bottom of the contact hole. Thereafter, using this titanium nitride as a starting point for selective growth, 400 nm of tungsten W is deposited by CVD, and then W on interlayer insulating film 21 is removed by CMP, and buried wiring 22 of W is formed in the contact hole opening. Form.
Thereafter, AlCu is deposited at 400 nm and Ti / TiN is deposited at 5/60 nm, a resist pattern is formed by photolithography, and Al wiring 23 is formed by anisotropic etching using the resist pattern as a mask.
[0014]
With this method, a fine contact hole can be formed in the memory portion, and the SiN film is always formed as a sidewall material between the contact hole and the gate electrode, so that the alignment margin in the lithography process is reduced, and a finer contact hole is formed. Can be formed.
This makes it possible to reduce the contact size of a repetitive pattern of a memory or the like together with the contact size relaxed from randomness in the logic part without affecting the lithography process, thereby enabling high integration of elements.
In addition, it is possible to reduce the alignment margin of the repetitive pattern such as a memory without affecting the lithography process, thereby enabling high integration of elements.
Further, it is possible to reduce the memory cell size by reducing the alignment margin without suppressing the optical proximity effect and deteriorating the manufacturing margin due to the miniaturization of the memory portion.
In addition, the contact hole diameter realized using the most advanced process technology for memory and logic can be processed in one lithography process by aligning the design when opening the contact hole to the same diameter. it can.
In addition, the insulating film forming process performed after the contact hole is opened reduces the contact hole diameter only in the memory portion, and the gate electrode and the edge film side wall formed on the side wall of the contact hole allow the insulation of the wiring between the gate electrode and the contact hole. Can be secured. Further, the contact pitch of the memory portion can be made the same as the contact pitch of the logic portion, and by forming the sidewall insulating film in the above embodiment, the margin between the base gate electrode and the contact can be reduced, and a finer memory cell design can be realized. .
[0015]
In the contact hole forming step shown in FIG. 12, the gate sidewall insulating film may be partially removed by changing the etching conditions for the gate sidewall insulating film 18.
Alternatively, the gate sidewall insulating film may be completely removed to expose the gate in the contact hole. Even in such a state, current leakage between the gate 16 and the wiring 22 does not occur because the insulating film 25 exists in the contact hole.
In addition, after opening a contact hole in the interlayer insulating film 21, a PSG film (abbreviation of PSG: Phosphorphoric Silicate Glass, which means an etching selectivity ratio with respect to a silicon oxide film, which means phosphosilicate glass. One of silicate glass. May be used in place of the silicon nitride 25. In this method, after the PSG side wall is formed only in the memory portion, the silicon nitride film formed on the surface of the interlayer insulating film 21 and the contact hole surface is simultaneously removed in the logic portion and the memory portion, and the contact hole bottom portion is opened. Is.
The process for forming the nMOSFET has been described above, but it can be applied to a normal CMOS process including a pMOSFET, and Ti silicide is formed on the diffusion layer / gate electrode to reduce resistance. Can achieve the same effect not only with Ti but also with refractory metals such as Co, Pt, Ni, W, and Mo, and even in the absence of these, this patent increases the integration of memory-embedded logic processes. It is obvious that there is an effect. Further, although the gate side wall made of silicon nitride has been described, the effect can also be obtained by this patent in the case of the side wall made of silicon oxide.
[0016]
【The invention's effect】
Accordingly, in the present invention, by forming an insulating film on the side wall of the contact hole, the contact hole process of the memory part and the logic part can be unified, and the number of processes can be reduced. Furthermore, the presence of the insulating film on the side wall of the contact hole can provide a memory-embedded logic that can reduce the distance between the gates and achieve high integration of the contact hole.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 6 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 8 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the example of the present invention.
FIG. 10 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the example of the present invention.
FIG. 11 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the example of the present invention.
FIG. 12 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the example of the present invention.
FIG. 13 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the example of the present invention.
FIG. 14 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the example of the present invention.
FIG. 15 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the example of the present invention.
FIG. 16 is a cross-sectional view showing one step in a method of manufacturing a semiconductor device according to a conventional technique.
FIG. 17 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in the prior art.
FIG. 18 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in the prior art.
FIG. 19 is a cross-sectional view showing one step in a method of manufacturing a semiconductor device in the prior art.
FIG. 20 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in the prior art.
FIG. 21 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in the prior art.
FIG. 22 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in the prior art.
FIG. 23 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in the prior art.
FIG. 24 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in the prior art.
FIG. 25 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in the prior art.
FIG. 26 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in the prior art.
FIG. 27 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in the prior art.
[Explanation of symbols]
1 Si substrate 2 SiO2
3 Polycrystalline Si
4 SiO2
5 Resist 6 SiO2
7 Polycrystalline Si
8 SiO2
9 STI (Shallow Trench Isolation) region 10 SiO 2
11 SiO2 (sacrificial oxide film)
12 pwell
13 Gate insulating film 14 Polycrystalline Si
15 resist (for gate electrode formation)
16 Polycrystalline Si (Gate electrode)
17 Shallow n + diffusion layer 18 SiN side wall 19 Deep n + diffusion layer 20 Ti silicide 21 Interlayer insulating film (SiO2 / BPSG)
22 Metal wiring (contact hole)
23 AlCu (metal wiring)
24 SiN
26 resist

Claims (1)

A first element isolation region for forming a semiconductor substrate region having a memory formation planned region and a logic formation planned region , wherein a plurality of semiconductor device formation planned regions in the memory formation planned region are separated from the semiconductor substrate region Forming a second element isolation region for separating a plurality of semiconductor device formation planned regions in the logic formation planned region in the semiconductor substrate region, and forming the memory formation planned region and the logic formation in the semiconductor substrate region Forming a third element isolation region for isolating the planned region;
Forming a first first conductivity type region in the semiconductor substrate region to be the memory formation scheduled region and simultaneously forming a second first conductivity type region in the semiconductor substrate region to be the logic formation scheduled region; ,
Applying a gate oxide film on the first first conductivity type region and the second first conductivity type region;
Forming a plurality of gates in the plurality of semiconductor device formation scheduled regions in the memory formation scheduled region, and forming a plurality of second gates in the plurality of semiconductor device formation scheduled regions in the logic formation scheduled region; ,
A first second conductivity type impurity diffusion region is formed in a part on the first first conductivity type region, and a second second conductivity type is formed in a part on the second first conductivity type region. Forming an impurity diffusion region of
Forming a first gate sidewall insulating film on the first gate sidewall and forming a second gate sidewall insulating film on the second gate sidewall;
Forming an interlayer insulating film on the first gate, on the second gate, on the first second conductivity type impurity diffusion region, and on the second second conductivity type impurity diffusion region; When,
The interlayer insulating film provided on the first second conductivity type impurity diffusion region and a part of the first gate sidewall insulating film are removed until the first second conductivity type impurity diffusion region is exposed. And forming a first contact hole;
Simultaneously with the step of forming the first contact hole, the interlayer insulating film buried on the second second conductivity type impurity diffusion region is removed until the second second conductivity type impurity diffusion region is exposed. Forming a second contact hole equal to the contact diameter of the first contact hole;
Forming an insulating film on a bottom surface and a side surface portion of the first contact hole, a bottom surface and a side surface portion of the second contact hole, and the surface of the interlayer insulating film;
Removing the insulating film leaving only the insulating film on the side surface of the first contact hole; and
Forming a wiring in the first contact hole and the second contact hole.

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