JP2001057347A - Semiconductor device and method of manufacturing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device where the same fine processing technique is used for processes through which memories and logics are formed. SOLUTION: Contact holes used in a memory and a logic are set uniform in diameter when a contact hole 22 is bored, by which processing can be carried out through one lithography process. Through an insulating film forming process which is carried out after a contact hole 22 is bored, only a contact hole bored in a memory A is lessened in diameter, and a gate electrode 16 and the contact hole 22 are ensured of insulation properties by an insulating film side wall which is formed on the side wall-of the contact hole 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI manufacturing process, and more particularly to a structure and a manufacturing process of a contact hole in a mixed technology of a logic considering randomness and a large-capacity memory considering a repeated portion of the same pattern. is there.

[0002]

2. Description of the Related Art Hereinafter, a conventional logic process with embedded memory will be described by taking a wiring process of one layer as an example.
Here, an area A displayed below represents a process of the memory unit, and an area B represents a process of the logic unit. First, as shown in FIG. 16, a thin silicon oxide film 32 of, for example, 10 nm is formed on a p-type silicon substrate 31 by thermal oxidation, and an LP-CVD method (low-pressure CV
D method), a polycrystalline silicon 33 is formed to a thickness of 200 nm, and a silicon oxide film 34 is further formed thereon by an LP-CVD method.
Is formed to a thickness of 200 nm. Thereafter, ST is applied by photolithography.
A region where an element isolation region is to be formed by I (shallow trench isolation) is patterned with a resist 35. Here, STI means that after digging a groove in a semiconductor substrate,
The trench is formed by filling a groove with a CVD oxide film such as TEOS or polycrystalline silicon, and flattening the surface by CMP. Next, as shown in FIG. 17, using the pattern of the resist 35 as a mask, the silicon oxide film 34 is etched by anisotropic dry etching having a selectivity to the polycrystalline silicon film, and the resist 35 is removed. . Using the remaining silicon oxide film 36 as a mask, the polycrystalline silicon 37 obtained by etching the polycrystalline silicon 33 and the silicon oxide film 34 were etched by anisotropic dry etching capable of obtaining a sufficient selectivity with respect to the oxide film. Silicon oxide film 3 obtained by etching silicon oxide film 36 and silicon oxide film 32 which is a thin thermal oxide film
8 is formed.

[0005] Next, as shown in FIG. 18, the silicon substrate 31 is etched by, for example, 0.5 μm by anisotropic dry etching which can sufficiently obtain a selectivity with respect to an oxide film, thereby forming an STI trench 39. Form. Next, as shown in FIG. 19, a silicon oxide film 40 is deposited to a thickness of 1.5 μm by LP-CVD. Thereafter, a chemical mechanical polishing method (CMP: Chemical) capable of obtaining a selectivity with respect to polycrystalline silicon.
Silicon oxide film 40 by mechanical polishing
Is flattened. After the planarization, the silicon oxide film 36 and the silicon oxide film 40 are etched by NH4F or dry etching until the polycrystalline silicon 37 is just exposed. Next, as shown in FIG. 20, the polycrystalline silicon 37 is etched by isotropic dry etching, which can provide a selectivity with respect to the silicon oxide film, and heat treatment for reducing the film stress of the buried silicon oxide film 40 is performed, for example. 1000 ° C
Perform at Thereafter, the silicon oxide film 38 on the silicon substrate 31 is etched with NH4F. Thereafter, a silicon oxide film 41 is formed by, for example, thermal oxidation at 800 ° C., and a P-well region 42 is formed by implanting B (boron) at an acceleration voltage of 200 KeV and a dose of 8E12 cm −2 for forming a P-well region.

Further, for controlling the threshold value of the nMOSFET, B (boron) is implanted at an acceleration voltage of 50 KeV and a dose of 1E13 cm @ -2. Thereafter, at 1000 ° C. for 30 minutes
The introduced impurities were activated by a heat treatment for 2 seconds.
Next, as shown in FIG. 21, the thermal oxide film on the silicon substrate surface such as the silicon oxide film 41 is removed, and a gate insulating film 43 is formed to a thickness of 6 nm by thermal oxidation at 750 ° C. Thereafter, polycrystalline Si is deposited to a thickness of 300 nm by the LP-CVD method. Thereafter, a resist pattern 45 for the gate electrode is formed by a photolithography method, and a gate electrode 46 is formed by anisotropic dry etching capable of obtaining a sufficient selectivity with the silicon oxide film. Next, as shown in FIG. 22, a 5 nm-thick silicon oxide film is formed on the silicon substrate by a thermal oxidation method at 800 ° C. Thereafter, As is accelerated at an acceleration voltage of 35 Ke.
V is implanted at a dose of 2E14 cm−2 at 1000 ° C.
A shallow diffusion layer 47 (shall
ow Extension). Next, as shown in FIG. 23, a silicon nitride film SiN is deposited on the semiconductor substrate by LP-CVD to a thickness of 150 nm, and the silicon nitride film and the silicon oxide film are anisotropically etched to obtain an etching selectivity. Form. Thereafter, for example, As is applied to the gate 4 at an acceleration voltage of 60 KeV and a dose of 5E15 cm−2.
6 and the gate side wall 48 are ion-implanted into
A shallow diffusion layer 47 is formed by a heat treatment for 30 seconds in an N2 atmosphere at 00 ° C.
A deeper source / drain diffusion layer 49 is formed around the ion-implanted region. For this reason, a region not ion-implanted using the gate 46 and the gate side wall 48 as a mask remains as a shallow diffusion layer 47. After this, the gate electrode 46
To n +.

Next, as shown in FIG. 24, the silicon oxide film 43 on the deep source / drain diffusion layer 49 is
4F, the high melting point metal is formed in the removed area, and for example, titanium and titanium nitride (Ti / TiN) are deposited as the high melting point metal at 30/20 nm, respectively. Thereafter, a heat treatment is performed for 30 seconds in an N2 atmosphere at 700 ° C. to remove titanium Ti unreacted with silicon Si in a mixed solution of sulfuric acid and hydrogen peroxide. After this, 800
A heat treatment is performed in an N2 atmosphere at 30 ° C. for 30 seconds to form a low-resistance Ti silicide compound 50. Next, as shown in FIG. 25, a silicon nitride film SiN is deposited by the LP-CVD method. Thereafter, a BPSG film of 100 nm or a silicon oxide film of 9
Deposited to a thickness of 00 nm, and planarized by CMP (chemical / mechanical polishing). Next, as shown in FIG. 26, a contact resist pattern is formed by photolithography,
The interlayer insulating film 51 is removed by anisotropic etching having an etching selectivity to silicon nitride SiN, and a region where a contact hole is to be formed is opened. Next, as shown in FIG. 27, for example, a high melting point metal such as Ti is sputtered so as to deposit 10 nm at the bottom of the contact. Thereafter, a heat treatment is performed for 30 minutes in an N2 atmosphere at, for example, 600 ° C. to form titanium nitride TiN on the Ti surface. Thereafter, 400 nm of tungsten W is deposited by CVD using the titanium nitride as a starting point for selective growth.
W on the interlayer insulating film 51 is removed by the P method, and a buried wiring 52 of W is formed in the contact opening. Then A
400 nm of lCu and 5/60 nm of Ti / TiN are deposited, a resist pattern is formed by photolithography, and an Al wiring 53 is formed by anisotropic etching using this as a mask.

[0006]

As described above, the MOSFET having the salicide of the prior art can be formed. However, in the prior art shown in FIG. 27, the memory portion (repeated pattern portion) shown in FIG. ) And the logic part (pattern part having high randomness) of the part (B) can be applied only to the same lithography technique. With the progress of lithography technology development in recent years, shorter wavelength of light,
Significant progress has been made until a fine pattern with a wavelength equal to or less than the wavelength of light can be formed by using a phase shift for the reticle pattern. However, as described above, in the fine pattern forming technology that also utilizes the light interference effect, the optical proximity effect is obtained by repeating the limited pattern of the contact hole having high randomness in the Logic portion and the memory portion. It has become difficult to realize contacts capable of forming finer contacts by the same lithography process. For this reason, even in a logic process in which memories are mixed, it is difficult to realize a fine contact diameter only in the memory section, and the logic section and the memory section have to have the same contact diameter, which is required for a logic LSI. This is a major obstacle to realizing a highly integrated memory.

By performing the lithography step separately in the memory section and the logic section, fine processing of the pattern can be realized. However, in the lithography process,
When a pattern is transferred onto a semiconductor substrate, misalignment of the transfer pattern always occurs. Therefore, when a contact hole is formed in the same lithography step, this misalignment is taken into consideration in the next wiring process. Therefore, it is necessary to reflect it on the wiring design, which is contrary to miniaturization. Further, performing the processes of the memory unit and the logic unit separately complicates the manufacturing process and causes a great increase in the number of processes. An object of the present invention is to solve such problems of the prior art. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a memory mixed logic in which the contact hole processes of the memory section and the logic section are unified and the number of steps is reduced. It is another object of the present invention to provide a method of manufacturing a memory embedded logic in which elements are highly integrated.

[0008]

The structure of a semiconductor device according to the present invention comprises a semiconductor substrate, a first conductivity type well provided in the semiconductor substrate, and a plurality of wells formed in the first conductivity type well. A second conductivity type impurity diffusion layer, a gate oxide film provided on the semiconductor substrate, the second conductivity type impurity diffusion layer, and a gate oxide film between the second conductivity type impurity diffusion layers. A gate, an interlayer insulating film having a contact hole provided around the gate, and on the semiconductor substrate, an insulating film provided on a contact hole surface other than a contact hole bottom in the interlayer insulating film, A conductive layer formed in the contact hole in contact with the insulating film. The method of manufacturing a semiconductor device according to the present invention includes the steps of: forming a first conductivity type region in a semiconductor substrate region; and forming a second conductivity type impurity diffusion region on a part of the first conductivity type region. Forming a gate oxide film on the first conductivity type region and on the second conductivity type impurity diffusion layer; and forming a gate on the gate oxide film between the second conductivity type impurity diffusion layers Forming a gate sidewall insulating film on the gate sidewall, forming an interlayer insulating film on the gate, on the impurity diffusion region of the second conductivity type, and on the gate sidewall insulating film; Forming the opening region by removing the interlayer insulating film on the impurity diffusion region of the mold type, exposing the impurity diffusion region of the second conductivity type, and insulating the surface of the opening region and the surface of the interlayer insulating film. Forming a film;
A method of manufacturing a semiconductor device, comprising: a step of removing the insulating film while leaving a side surface of an opening region; and a step of forming a wiring in the opening region.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a logic process used for embedding a memory according to an embodiment of the present invention will be described. Here, an area A displayed below represents a process of the memory unit, and an area B represents a process of the logic unit.
First, as shown in FIG. 2, a thin silicon oxide film 2 having a thickness of, for example, 10 nm is formed on a p-type silicon substrate 1 by thermal oxidation.
A polycrystalline silicon 3 is formed thereon by LP-CVD (low-pressure CVD) to a thickness of 200 nm, and a silicon oxide film 4 is further formed thereon by LP-CVD to a thickness of 200 nm. Thereafter, a region where an element isolation region is to be formed by STI is patterned with a resist 5 by photolithography.
Next, as shown in FIG. 3, using the pattern of the resist 5 as a mask, the silicon oxide film 4 is etched by anisotropic dry etching having a selectivity with respect to the polycrystalline silicon film, and the resist 5 is removed. By using the remaining silicon oxide film 6 as a mask, the polycrystalline silicon 7 and the silicon oxide film 4 which were obtained by etching the polycrystalline silicon 3 were etched by anisotropic dry etching capable of obtaining a sufficient selectivity with respect to the oxide film. A silicon oxide film 8 is formed by etching the silicon oxide film 6 and the silicon oxide film 2 which is a thin thermal oxide film.

Next, as shown in FIG. 4, the silicon substrate 1 is etched by, for example, 0.5 μm by anisotropic dry etching to obtain a sufficient selectivity with respect to the oxide film,
The TI groove 9 is formed. Next, as shown in FIG.
1.5 μm silicon oxide film 10 by LP-CVD
accumulate. Thereafter, a chemical mechanical polishing method (CMP: Chemical Mechanic) capable of obtaining a selectivity with respect to polycrystalline silicon.
ical polishing) to planarize the silicon oxide film 10. After the planarization, the silicon oxide film 6 and the silicon oxide film 10 are etched by NH4F or dry etching until the polysilicon 7 is just exposed. Next, as shown in FIG. 6, the polycrystalline silicon 7 is etched by isotropic dry etching, which can provide a selectivity between the silicon oxide film 2 and heat treatment for reducing the film stress of the buried silicon oxide film 10. For example, at 1000 ° C. Thereafter, the silicon oxide film 8 on the silicon substrate 1 is
Etch with H4F. After this, the silicon oxide film 1
1 is formed by, for example, thermal oxidation at 800 ° C., and B (boron) is formed at an accelerating voltage of 200 K for forming a P-well region.
P-well region 12 implanted with eV at a dose of 8E12 cm-2
To form

Further, for controlling the threshold value of the nMOSFET, B (boron) is implanted at an acceleration voltage of 50 KeV and a dose of 1E13 cm @ -2. Thereafter, at 1000 ° C. for 30 minutes
The introduced impurities were activated by a heat treatment for 2 seconds.
Next, as shown in FIG. 7, the thermal oxide film on the silicon substrate surface such as the silicon oxide film 11 is removed, and the gate insulating film 1 is removed.
3 is formed by thermal oxidation at 750 ° C. to a thickness of 6 nm. Thereafter, polycrystalline Si is deposited to a thickness of 300 nm by the LP-CVD method. Thereafter, a resist pattern 15 for the gate electrode is formed by photolithography, and a gate electrode 16 is formed by anisotropic dry etching which can provide a sufficient selectivity with the silicon oxide film. Next, as shown in FIG. 8, a silicon oxide film of, eg, 5 nm is formed on the silicon substrate by a thermal oxidation method at 800 ° C. After that, As is accelerated to 35 KeV.
At a dose of 2E14 cm-2 at 1000 ° C.
A shallow diffusion layer 17 is formed by a heat treatment for 30 seconds in two atmospheres. Next, as shown in FIG. 9, a silicon nitride film SiN is deposited to a thickness of 150 nm on the semiconductor substrate by the LP-CVD method, and this is anisotropically etched with a silicon oxide film to obtain an etching selectivity. Form.
Thereafter, for example, As is ion-implanted at an acceleration voltage of 60 KeV at a dose of 5E15 cm−2 using the gate 16 and the gate side wall 18 as a mask, and subjected to a heat treatment at 1000 ° C. in an N 2 atmosphere for 30 seconds to form a source / drain layer deeper than the shallow diffusion layer 17. The drain diffusion layer 19 is formed around the ion-implanted region.
For this reason, a region not ion-implanted using the gate 16 and the gate side wall 18 as a mask remains as a shallow diffusion layer 17. Thereafter, the gate electrode 16 is doped with n +.

Next, as shown in FIG. 10, the deep source / drain diffusion layer 19 and the silicon oxide film 13 on the Si of the gate electrode are removed by NH4F to form a region where the high melting point metal is removed. For example, titanium and titanium nitride (Ti / TiN) are used as refractory metals at 30/20, respectively.
nm. Thereafter, a heat treatment is performed for 30 seconds in an N2 atmosphere at 700 ° C. to remove titanium Ti unreacted with silicon Si in a mixed solution of sulfuric acid and hydrogen peroxide. Thereafter, heat treatment is performed for 30 seconds in an N2 atmosphere at 800 ° C. to form a low-resistance Ti silicide compound 20. Next, as shown in FIG. 11, a silicon nitride film SiN24 is deposited by the LP-CVD method. After that, a 100 nm BPSG film or a 900 nm silicon oxide film is deposited as the interlayer insulating film 21 and planarized by CMP (chemical and mechanical polishing). Next, as shown in FIG. 12, a resist pattern of a contact is formed by photolithography, and the interlayer insulating film 21 is removed by anisotropic etching capable of obtaining an etching selectivity with silicon nitride SiN.
An opening is formed in a region where a contact hole is to be formed. Next, FIG.
As shown in FIG. 3, after opening the contact hole in the interlayer insulating film 21, silicon nitride SiN 25, for example, is deposited to a thickness of 20 nm on the front surface by LPCVD.

Next, as shown in FIG. 14, the silicon nitride film 25 is formed by isotropic etching using a resist pattern 26 formed by photolithography only in the region B as a mask.
Is removed by etching. Next, as shown in FIG. 15, the resist pattern 26 is peeled off, and anisotropic etching capable of obtaining an etching selectivity with respect to a silicon oxide film, silicon Si, and silicide is performed. The silicon nitride film 25 is peeled off, and at the same time, a contact hole is opened on the side wall of the memory portion while leaving the silicon nitride film 25. Next, as shown in FIG. 1, for example, titanium Ti, which is a high melting point metal, is sputtered so that 10 nm is deposited at the bottom of the contact hole. Here, illustration of titanium is omitted. Thereafter, a heat treatment is performed for 30 minutes in an N2 atmosphere at, for example, 600 ° C. to form titanium nitride TiN on the Ti surface at the bottom of the contact hole. Thereafter, using this titanium nitride as a starting point for selective growth, tungsten W is deposited to a thickness of 400 nm by the CVD method, and then the W on the interlayer insulating film 21 is removed by the CMP method. To form Then, 400 nm of AlCu was added to Ti / Ti
N is deposited to a thickness of 5/60 nm, a resist pattern is formed by photolithography, and an Al wiring 23 is formed by anisotropic etching using this as a mask.

According to the present method, a fine contact hole can be formed in the memory portion, and the SiN film is always formed as a sidewall material between the contact hole and the gate electrode. A contact hole can be formed. As a result, miniaturization of the contact size of a repetitive pattern of a memory or the like can be realized without affecting the lithography process by making the contact size relaxed from randomness in the logic portion, and high integration of elements can be achieved. In addition, it is possible to reduce the margin of alignment of a repetitive pattern of a memory or the like without affecting the lithography process, thereby enabling high integration of elements. Further, it is possible to miniaturize a memory cell by reducing an alignment margin without suppressing an optical proximity effect and deteriorating a manufacturing margin due to miniaturization of a memory portion. In addition, the contact hole diameter realized by using the most advanced process technology for memory and logic is the same as the contact hole opening design, making it possible to process in one lithography process. it can. In addition, the insulating film forming process performed after the opening of the contact hole reduces the diameter of the contact hole only in the memory portion, and the insulating property of the wiring between the gate electrode and the contact hole is reduced by the edge film sidewall formed on the gate electrode and the contact hole sidewall. It is possible to secure. Further, the contact pitch of the memory portion can be made the same as the contact pitch of the logic portion, and the margin between the underlying gate electrode and the contact can be reduced by forming the side wall insulating film of the above embodiment, and a finer memory cell design can be realized. .

In the contact hole forming step shown in FIG. 12, a part of the gate sidewall insulating film may be removed by changing the etching conditions for the gate sidewall insulating film 18. Further, the gate side wall insulating film may be completely removed to expose the gate to the contact hole. Even in such a state, no current leaks between the gate 16 and the wiring 22 because the insulating film 25 exists in the contact hole. After the opening of the contact hole in the interlayer insulating film 21, a PSG film (PS
G: Phosophor-SilicateGlass
Stands for phosphosilicate glass. A type of silicate glass used for stabilizing semiconductor surfaces. )
May be used instead of the silicon nitride 25. In this method, after forming the PSG side wall only in the memory section, the silicon nitride film formed on the surface of the interlayer insulating film 21 and the contact hole is simultaneously removed in the logic section and the memory section, and the bottom of the contact hole is opened. Things. Although the process of forming an nMOSFET has been described above, Ti silicide is formed on a diffusion layer / gate electrode to reduce resistance, because it can be applied to a normal CMOS process including a pMOSFET. Represents not only Ti, but also Co, Pt, Ni, W,
The same effect can be obtained even with a high melting point metal such as Mo,
Further, it is obvious that the present invention is effective for the high integration of the memory embedded logic process even when these are not provided. Although the gate side wall made of silicon nitride has been described, the effect can be obtained by the present invention in the case of a side wall made of silicon oxide.

[0016]

As described above, according to the present invention, by forming the insulating film on the side wall of the contact hole, the contact hole process of the memory section and the logic section can be unified, and the number of steps can be reduced. Further, the presence of the insulating film on the side wall of the contact hole can shorten the distance between gates and provide a memory-embedded logic capable of achieving high integration of the contact hole.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an example of the present invention.

FIG. 5 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an example of the present invention.

FIG. 6 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an example of the present invention.

FIG. 7 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an example of the present invention.

FIG. 8 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an example of the present invention.

FIG. 9 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an example of the present invention.

FIG. 10 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an example of the present invention.

FIG. 11 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an example of the present invention.

FIG. 12 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an example of the present invention.

FIG. 13 is a sectional view showing one step of a method of manufacturing a semiconductor device according to an example of the present invention.

FIG. 14 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to an example of the present invention.

FIG. 15 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to an example of the present invention.

FIG. 16 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in a conventional technique.

FIG. 17 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in a conventional technique.

FIG. 18 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in a conventional technique.

FIG. 19 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in a conventional technique.

FIG. 20 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in a conventional technique.

FIG. 21 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in a conventional technique.

FIG. 22 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to a conventional technique.

FIG. 23 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in a conventional technique.

FIG. 24 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in a conventional technique.

FIG. 25 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in a conventional technique.

FIG. 26 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in a conventional technique.

FIG. 27 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Si substrate 2 SiO2 3 Polycrystalline Si 4 SiO2 5 Resist 6 SiO2 7 Polycrystalline Si 8 SiO2 9 STI (Shallow Trench Isol)
) region 10 SiO2 11 SiO2 (sacrificial oxide film) 12 pwell 13 gate insulating film 14 polycrystalline Si 15 resist (for forming gate electrode) 16 polycrystalline Si (gate electrode) 17 shallow n + diffusion layer 18 SiN sidewall 19 deep n + diffusion Layer 20 Ti silicide 21 Interlayer insulating film (SiO2 / BPSG) 22 Metal wiring (contact hole) 23 AlCu (metal wiring) 24 SiN 26 Resist

Continued on the front page F-term (reference) 4M104 AA01 BB01 BB30 BB40 CC05 DD04 DD16 DD19 DD26 DD37 DD43 DD66 DD75 DD79 DD84 EE09 EE17 FF13 FF14 FF18 FF22 FF28 GG09 GG10 GG14 GG16 HH14 HH16 HH20 5F048 AB01A01BB BE04 BF06 BF12 BF16 BG14 5F083 AD10 BS05 GA02 GA09 GA28 JA02 JA19 JA32 JA35 JA53 JA56 MA06 MA19 NA01 PR03 PR05 PR10 PR12 PR15 PR21 PR22 PR33 PR36 PR40 PR43 PR44 PR53 PR54 ZA12

Claims (6)

[Claims] A semiconductor substrate; a first conductivity type well provided in the semiconductor substrate; a plurality of second conductivity type impurity diffusion layers formed in the first conductivity type well; A gate oxide film provided on the impurity diffusion layer of the second conductivity type, a gate provided on a gate oxide film between the impurity diffusion layers of the second conductivity type, the semiconductor substrate, and the gate A contact hole provided in the vicinity; an interlayer insulating film having the contact hole provided on the gate and the semiconductor substrate; and a contact hole surface provided in the interlayer insulating film other than the contact hole bottom. A semiconductor device, comprising: an insulating film; and a conductive layer formed in a contact hole in contact with the insulating film. 2. A semiconductor substrate; a first conductivity type well provided in the semiconductor substrate; a plurality of second conductivity type impurity diffusion layers formed in the first conductivity type well; A gate oxide film provided on the second conductivity type impurity diffusion layer; a gate provided on the gate oxide film between the second conductivity type impurity diffusion layers; and a gate oxide film provided on both sides of the gate. A gate sidewall insulating film; a contact hole provided on the semiconductor substrate and in the vicinity of the gate; an interlayer insulating film having a contact hole provided on the gate and on the semiconductor substrate; An insulating film provided on the surface of the contact hole other than the bottom of the contact hole, and a conductive layer formed in the contact hole in contact with the insulating film. Conductor device. 3. A semiconductor substrate having a memory region and a logic region, a first first conductivity type well provided in the memory region in the semiconductor substrate, and a semiconductor substrate formed in the first first conductivity type well. A plurality of first second conductivity type impurity diffusion layers, and a first gate oxide provided on the first first conductivity type well and on the first second conductivity type impurity diffusion layer. A film, a first gate provided on the first gate oxide film, a first contact hole provided on the semiconductor substrate and near the first gate, and on the first gate A first interlayer insulating film having the first contact hole provided on the semiconductor substrate, and a first contact hole bottom provided in the first interlayer insulating film, Insulation provided on the contact hole surface An edge film; a conductive layer formed in a first contact hole in contact with the insulating film; a second first conductivity type well provided in the logic region in the semiconductor substrate; A plurality of second second-conductivity-type impurity diffusion layers provided on the first-conductivity-type well; and on the second first-conductivity-type well and on the second second-conductivity-type impurity diffusion layer. A second gate oxide film provided on the second gate oxide film, a second gate provided on the second gate oxide film, a second gate sidewall insulating film provided on both sides of the second gate, A semiconductor device comprising: a second interlayer insulating film including a second contact hole provided on the semiconductor substrate on the second gate; and a conductive layer formed in the second contact hole. 4. A semiconductor substrate having a memory region and a logic region, a first first conductivity type well provided in the memory region in the semiconductor substrate, and a semiconductor substrate formed in the first first conductivity type well. A plurality of first second conductivity type impurity diffusion layers, and a first gate oxide provided on the first first conductivity type well and on the first second conductivity type impurity diffusion layer. A film, a first gate provided on a first gate oxide film between the first second conductivity type impurity diffusion layers, and a first gate sidewall insulating film provided on both sides of the first gate A film, a first contact hole provided on the semiconductor substrate and near the first gate, and a first contact hole provided on the first gate and the semiconductor substrate A first interlayer insulating film, and the first layer An insulating film provided on the surface of the first contact hole other than the bottom of the first contact hole in the insulating film; a conductive layer formed in the first contact hole in contact with the insulating film; A second first conductivity type well provided in the logic region therein; a plurality of second second conductivity type impurity diffusion layers provided on the second first conductivity type well; A second gate oxide film provided on the second first conductivity type well and on the second second conductivity type impurity diffusion layer; and a second gate oxide film between the second second conductivity type impurity diffusion layer. A second gate provided on the gate oxide film; a second gate sidewall insulating film provided on both sides of the second gate; and a second gate provided on the semiconductor substrate on the second gate. A second interlayer insulating film including a second contact hole; The semiconductor device having a conductive layer formed in tact hole. 5. A step of forming a first conductivity type region in a semiconductor substrate region; a step of forming a second conductivity type impurity diffusion region in a part of the first conductivity type region; Forming a gate oxide film on the mold region and on the impurity diffusion layer of the second conductivity type; forming a gate on the gate oxide film between the impurity diffusion layers of the second conductivity type; Forming an interlayer insulating film on the gate, on the impurity diffusion region of the second conductivity type, and on the gate sidewall insulating film; and on the gate, the impurity diffusion region of the second conductivity type. Removing the upper interlayer insulating film, exposing the impurity diffusion region of the second conductivity type,
Forming an opening region; forming an insulating film on the surface of the opening region and the surface of the interlayer insulating film; removing the insulating film leaving a side surface of the opening region; Forming a wiring on the semiconductor device. 6. A step of forming a semiconductor substrate region having a memory formation planned region and a logic formation planned region, and forming a first first conductivity type region in the semiconductor substrate region to be the memory formation planned region, Forming a second first conductivity type region in a semiconductor substrate region to be the logic formation planned region; and a first element isolation region separating a plurality of semiconductor device formation planned regions in the memory formation planned region. Forming a second element isolation region for isolating a plurality of semiconductor device formation regions in the logic formation region, a third element isolation region for isolating the memory formation region and the logic formation region Forming a gate oxide film on the first first conductivity type region and the second first conductivity type region; and forming a plurality of semiconductors in the memory formation planned region. Forming a plurality of first gates in a body device formation planned region, and forming a plurality of second gates in a plurality of semiconductor device formation planned regions in the logic formation planned region; Forming a first second conductivity type impurity diffusion region on a part of the mold region; and forming a second second conductivity type impurity diffusion region on a part of the second first conductivity type region. Forming a first gate sidewall insulating film on the first gate sidewall and forming a second gate sidewall insulating film on the second gate sidewall; and forming the second gate sidewall insulating film on the second gate sidewall. Forming an interlayer insulating film on a gate, on the first second conductivity type impurity diffusion region, and on the second second conductivity type impurity diffusion region; and Part of the interlayer insulating film provided on the impurity diffusion region and the first gate sidewall insulating film Forming a first contact hole electrically connected to the impurity diffusion region of the first second conductivity type, and forming the first contact hole simultaneously with the step of forming the second contact hole. The interlayer insulating film provided on the two-conductivity-type impurity diffusion region is removed, and the second insulation film is electrically connected to the second second-conductivity-type impurity diffusion region, and is substantially equal to the contact diameter of the first contact hole. Forming a second contact hole; forming an insulating film on the first contact hole surface, the second contact hole surface, and the interlayer insulating film surface; and forming the insulating film on the first contact hole. A method of manufacturing a semiconductor device, comprising: a step of removing a side surface portion; and a step of forming a wiring in the first contact hole and the second contact hole.