JP2009094439A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that prevents a defect from being caused even if over-etching thereof is made great, and to provide its manufacturing method. <P>SOLUTION: Semiconductor device includes a field effect transistor having a gate electrode comprised of side wall insulating films on a plurality of active regions, and a wiring formed on an element isolation region by using the same material as the gate electrode where the side wall insulating films are selectively removed and then a silicide layer thicker than that of the gate electrode is formed. A tensile stress insulating film is formed by covering a n-channel field effect transistor, and a compressive stress insulating film being formed by covering a p-channel field effect transistor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device having a silicide layer and a method for manufacturing the semiconductor device.

  In the manufacturing process of a semiconductor device, a normally insulated gate (MOS) field effect transistor (FET) structure is formed, and a silicide layer is formed on the gate wiring and source / drain regions by a salicide process and covered with an interlayer insulating film. Thereafter, a contact hole is formed through the interlayer insulating film to expose the gate wiring of the MOS transistor and the contact surface of the source / drain region. The silicide layer is effective in reducing contact resistance and wiring resistance.

  In order to form contact holes with different depths with good controllability, an etching stopper film is formed to cover the gate wiring and source / drain regions, and a main interlayer insulating film of silicon oxide is formed thereon. By stopping the etching of the main interlayer insulating film at the etching stopper layer, holes with different depths are formed with high reliability, and then the etching stopper film is etched to complete the contact holes. As the etching stopper film, a nitride film mainly showing tensile stress is used (for example, Patent Document 1, Japanese Patent Laid-Open No. 9-191056).

  There is a limit to improving the performance by miniaturization of MOS transistors. In addition to miniaturization, mobility enhancement due to stress has been widely adopted as a technique for improving the performance of MOS transistors.

  Patent Document 2 and Japanese Patent Application Laid-Open No. 2003-86708 propose using a stress control film in which stress is controlled, covering an n-channel MOSFET with a film having a tensile stress, and covering a p-channel MOSFET with a film having a compressive stress. ing.

  FIG. 5 schematically shows a CMOS structure proposed in Patent Document 2. For example, an active region isolation trench is formed from the surface of the p-type silicon substrate 111, and an insulating film such as an oxide film is embedded to form a shallow trench isolation (STI) region 112. By performing desired ion implantation in the active region defined in the STI (isolation) region, a p-type well region 113 for forming an n-channel MOSFET and an n-type well region 114 for forming a p-channel MOSFET are formed.

  A gate insulating film 115 is formed by thermally oxidizing the surface of the active region. After forming the gate insulating film, a polycrystalline silicon layer is deposited to form a gate electrode layer. By patterning the gate electrode layer and the gate insulating layer using the resist pattern, the n-channel MOSFET gate electrode Gn, the underlying gate insulating film 115, the p-channel MOSFET gate electrode Gp, and the underlying gate insulating film 115 are formed. Patterned. By performing desired ion implantation for each of the n-channel MOSFET region and the p-channel MOSFET region, an n-type extension region 121n is formed in the n-channel MOSFET region, and a p-type extension region 121p is formed in the p-channel MOSFET region. The

  Thereafter, an insulating film such as a silicon oxide film is deposited and anisotropic etching is performed to form a sidewall spacer SW on the sidewall of the gate electrode. After forming the sidewall spacers, ions of a desired conductivity type are ion-implanted again into the n-channel MOSFET region and the p-channel MOSFET region, so that the n-type source / drain diffusion layer 122n in the n-channel MOSFET region and the p-channel MOSFET region A p-type source / drain diffusion layer 122p is formed.

  Thereafter, a metal layer capable of silicidation such as cobalt is deposited, a silicidation reaction is caused, an unnecessary metal layer is removed, and then the silicidation reaction is completed, whereby the gate electrode G and the source / drain region 122 are formed. Then, the silicide layer SL is formed. The n-channel MOSFET region is covered with an etching stopper layer 125n which is a nitride film having tensile stress, and the p-channel MOSFET region is covered with an etching stopper layer 125p which is a nitride film having compressive stress.

  An insulating film of, for example, silicon oxide is formed on the etching stopper layers 125n and 125p, and the surface is planarized by chemical mechanical polishing (CMP). A resist pattern having contact hole-shaped openings is formed on the planarized surface, and the insulating film is etched. This etching stops at the etching stopper layers 125n and 125p of silicon nitride. Contact holes having different depths such as contact holes for the gate wiring layer and contact holes for the source / drain regions of the substrate can be formed with high accuracy. Thereafter, the etching stopper layer is etched to complete the contact hole. A conductive film that fills the contact hole is formed by forming a Ti film and a TiN film in the contact hole by sputtering or the like and forming a W layer by CVD.

  With such a configuration, it is possible to apply tensile stress to the n-channel MOSFET region and compressive stress to the p-channel MOSFET region using the etching stopper layer. These stresses improve the characteristics of the MOSFET.

  Japanese Patent Application Laid-Open No. 2004-170037 (incorporated here by reference) discloses an insulating stress film in which a recess is formed by digging a source / drain region formed below both sides of a sidewall spacer, and the recess is embedded. Propose to form.

  The Si—Ge mixed crystal has a larger lattice constant than Si, and when the Si—Ge mixed crystal is epitaxially grown on the Si source / drain region, a compressive stress can be applied to the Si region in the channel region sandwiched therebetween. The Si—C mixed crystal has a lattice constant smaller than that of Si, and when the Si—C mixed crystal is epitaxially grown on the Si source / drain region, tensile stress can be applied to the Si region of the channel region. It is possible to improve the carrier mobility by digging the source / drain regions of the MOS transistor and growing epitaxial crystals having different lattice constants (for example, Patent Document 4, Japanese Patent Application No. 2006-290773, US patent application Ser. No. 11 / 797,253, incorporated herein by reference.

  There has also been proposed full silicidation for siliciding the entire polycrystalline silicon wiring including the gate electrode (for example, P. Ranade et al: IEDM 2005, p227-230). Silicidation of the surface of the source / drain region of the active region is performed in a separate process. This is an effective technique for obtaining a low-resistance gate wiring. However, since the polycrystalline silicon layer disappears, a new technique is required for threshold control of the transistor.

JP-A-9-191056 JP 2003-86708 A JP 2004-170037 A Japanese Patent Application No. 2006-290773, US Patent Application No. 11 / 797,253 P. Ranade et al: IEDM2005, p227-230 Two gate electrodes may be formed in close proximity on the same active region, forming source / drain contacts on the intermediate substrate surface. For high integration, the gate electrode spacing should be as small as possible. However, if the contact etching stopper layer is formed to cover the gate electrode, the contact etching stopper layer from both sides will come into contact with the gate electrode to fill the narrow space. A thick layer may be formed.

  In a CMOS semiconductor device, a tensile stress silicon nitride film may be formed on an NMOS transistor, and a compressive stress film may be formed on a PMOS transistor, and these two kinds of stress films may be overlapped at the boundary. In some cases, the gate electrode of the NMOS transistor and the gate electrode of the PMOS transistor are formed by one continuous polysilicon wiring, and the lead wiring is connected in the middle. When the connection portion of the lead wiring overlaps with the overlapping portion of the stress silicon nitride film, the thickness distribution of the contact etch stopper film to be etched becomes large.

  In such a case, contact failure may occur if etching is insufficient. In order to ensure contact reliability, it is necessary to increase the etching margin (overetching amount) of the contact etching stopper layer. However, if the etching time is lengthened, excessive etching is performed in a region where etching has been appropriately performed. If the silicide region below the contact hole disappears due to excessive etching, contact resistance increases and contact failure occurs.

  An object of the present invention is to provide a highly reliable and high performance semiconductor device having a gate wiring with a silicide layer and a method for manufacturing the same.

  Another object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress the occurrence of problems even when the amount of overetching is increased.

  Another object of the present invention is to provide a semiconductor device capable of forming a highly reliable contact and capable of improving mobility by using stress, and a manufacturing method thereof.

According to one aspect of the present invention,
A semiconductor substrate having an active region and an element isolation region;
A conductive layer formed on the active region and the element isolation region;
A first silicide layer formed on the conductive layer located on the active region;
A second silicide layer formed on the conductive layer located on the element isolation region and thicker than the first silicide layer;
A sidewall insulating film covering a sidewall of the conductive layer located on the active region and exposing at least a part of the sidewall of the conductive layer located on the blocking isolation region;
A semiconductor device is provided.

According to another aspect of the invention,
Forming an element isolation region in a semiconductor substrate;
Forming a pattern including silicon on the element isolation region and an active region defined by the element isolation region;
Forming a sidewall insulating film on the sidewall of the pattern;
Removing the sidewall insulating film formed on the sidewall of the pattern on the element isolation region using a mask covering the pattern on the active region;
Forming a silicide layer on the pattern by forming a metal layer covering the pattern and reacting the pattern with the metal layer;
A method of manufacturing a semiconductor device having the above is provided.

  By increasing the thickness of the silicide layer, the wiring resistance is lowered, and the possibility that the silicide layer disappears due to overetching is reduced.

  By securing a polycide structure for the gate electrode, threshold control can be performed with high reliability.

  FIG. 4 shows a circuit diagram of an exclusive NOR circuit. On the right side, two configurations in which two NMOS transistors are connected in parallel and one common connection point 401 is connected in series to one PMOS transistor are shown side by side. On the left side, a configuration is shown in which two PMOS transistors are connected in parallel, and one common connection point 402 is connected in series to one NMOS transistor. Such a parallel-connected transistor can be realized on a semiconductor wafer by two gate electrodes, an intermediate portion thereof, and source / drain regions formed on both sides thereof.

  If an attempt is made to reduce the area occupied by two parallel transistors of the same conductivity type, the distance between the two transistors (two gate electrodes) also decreases. In a CMOS circuit, it is necessary to connect a reverse conductivity type transistor. Although not limited, such a CMOS circuit will be described as an example. Embodiments of the present invention will be described below with reference to the drawings.

  1A to 1P are cross-sectional views of a semiconductor substrate showing main steps of a method of manufacturing a CMOS semiconductor device.

As shown in FIG. 1A, a buffer oxide film 12 is formed by thermally oxidizing the surface of a p-type silicon substrate (wafer) 11, for example, and CVD is performed thereon using, for example, a silane-based material and ammonia as a source gas. A silicon nitride film 13 is deposited. The silicon nitride film 13 serves as a hard mask when the trench (groove) is etched in the silicon substrate 11, and functions as a stopper in the chemical mechanical polishing (CMP) process after the trench is backfilled with the silicon oxide film. On the silicon nitride film 13, a resist pattern PR1 having an opening in the shape of an element isolation region is formed. Using the resist pattern PR1 as an etching mask, the silicon nitride film 13 is etched with a gas containing CHF ₃ , Ar, and O ₂ . Subsequently, the buffer oxide film 12 and the silicon substrate 11 are etched with a gas containing Cl ₂ , O ₂ , and N ₂ to form a trench (groove) T having an element isolation region shape. The resist pattern PR1 may disappear after the etching of the silicon nitride film 13, or may be removed. After the etching process is finished, it should not remain.

As shown in FIG. 1B, after the inner surface of the trench is thermally oxidized as necessary, silane (SiH ₄ ) and oxygen (O ₂ ) are used as source gases by high density plasma (HDP) CVD using inductive coupling. Then, a silicon oxide film 14 is deposited so as to fill the trench T back. Instead of HDP-CVD, CVD using electron cyclotron resonance plasma may be used. A silicon oxide film can also be formed by thermal CVD using tetraethoxysilane (TEOS) and ozone (O ₃ ) as a source gas. HDP-CVD is preferred from the standpoint of the resistance of a dilute hydrofluoric acid cleaning step performed later.

  The silicon oxide film above the silicon nitride film 13 is polished and removed by chemical mechanical polishing (CMP). In CMP, the silicon nitride film 13 functions as a stopper. A flat surface is once formed by polishing.

  The silicon nitride film 13 is removed by wet etching with phosphoric acid boil (hot phosphoric acid). The buffer oxide film 12 is also removed by wet etching with dilute hydrofluoric acid. The exposed silicon surface of the active region is thermally oxidized to form a sacrificial oxide film for ion implantation.

  An NMOS region and a PMOS region are separated by a resist mask, and ion implantation such as well formation, channel stop formation, channel (threshold adjustment layer) formation, etc. is performed in the silicon substrate through a sacrificial oxide film, and n-type well NW, p-type Well PW is formed. Thereafter, the sacrificial oxide film is removed with dilute hydrofluoric acid.

  As shown in FIG. 1C, the surface of the active region is thermally oxidized to form a silicon oxide film having a thickness of 3 nm or less, and nitrogen is introduced using high temperature, plasma, etc., to form a silicon nitride oxide gate insulating film 16. To do. A polycrystalline silicon film 17 having a thickness of about 80 nm to 150 nm, for example, a thickness of 100 nm is deposited on the gate insulating film 16 at 600 ° C. by thermal CVD using silane or the like as a source gas.

A resist pattern PR2 having a gate wiring (including gate electrode) shape is formed on the polycrystalline silicon film 17, and the polycrystalline silicon film 17 is formed with a gas containing Cl ₂ , HBr, and CF ₄ using the resist pattern PR2 as an etching mask. Anisotropic ion etching is performed by reactive ion etching (RIE). After the gate electrode and the gate wiring are etched, the resist pattern PR2 is removed.

  When the minimum line width of the wiring on the wafer is 40 nm, the gate wiring width is, for example, the minimum line width of 40 nm. In the subsequent silicidation process, the silicidation reaction proceeds from both sides, and it is easy to perform full silicidation by merging at the center and siliciding the entire width.

  As shown in FIG. 1D, a gate electrode is formed on the active region, and a gate wiring is formed on the element isolation region. The reason why the gate wiring on the right side is widely shown is that the cross-sectional direction is bent as described below with reference to FIG.

  FIG. 2 shows a top view of a silicon substrate on which a transistor structure is formed. The element isolation region STI formed of the silicon oxide film 14 defines two p-type wells PW on the left side and one n-type well NW on the right side. In the figure, polysilicon gate lines G, which are five conductive layers, are arranged in the vertical direction. The third (center) gate wiring from the left forms the gate of the NMOS transistor across the p-type well PW on the upper side and the gate of the PMOS transistor across the n-type well NW on the lower side. Sidewall insulating films SW to be formed in a later process are formed on both sides of the gate wiring. On the element isolation region STI, the sidewall insulating film is selectively removed in a region including a position where a contact hole is to be formed.

  A broken line II corresponds to the cross-sectional direction of FIGS. Although it is generally in a direction intersecting with the gate wiring, in order to show a connection portion between the NMOS transistor and the PMOS transistor, a part of the cross section is taken along the gate wiring at the center.

  Returning to FIG. 1D, ion implantation of the pocket (or halo) region Pk and the extension region Ex is selectively performed on the p-type well PW and the n-type well NW using a resist mask. The ion implantation of the pocket region is performed from four directions inclined with respect to the substrate normal by p-type impurities such as In to B for the p-type well PW and n-type impurities such as As to P for the n-type well NW. Ion implantation. The extension region is ion-implanted with low acceleration energy so as to form a shallow junction, n-type impurities such as As to P for the p-type well PW, and p-type impurities such as In to P for the n-type well NW. B is ion-implanted from the substrate normal direction. The n-type extension region Exn of the NMOS transistor and the p-type extension region Exp of the PMOS transistor are formed so as to be surrounded by the pocket region Pk having the same conductivity type as the well.

As shown in FIG. 1E, a sidewall insulating film SW is formed. In order to suppress thermal diffusion of impurities in the extension region, it is desirable to form the sidewalls at as low a temperature as possible. For example, by using CVD with a temperature of 530 ° C. and a pressure of 20 Pa at a flow of 60 sccm of binary butylaminosilane (SiH ₂ (NH—C ₄ H ₉ ) ₂ , BTBAS) as the Si source gas and 240 sccm of oxygen as the O source gas, the thickness is about A 30 nm silicon oxide film is deposited. This silicon oxide film is anisotropically etched by reactive ion etching (RIE) using a gas containing C ₄ F ₈ and Ar to remove it from the surface of the flat portion, and on the side wall of the gate electrode (including gate wiring) Is left as a sidewall insulating film SW only.

Note that the sidewall insulating film is not limited to the above. For example, a silicon nitride film may be used instead of the silicon oxide film. For example, a silicon nitride film can be deposited by CVD at a temperature of about 400 ° C. to 700 ° C. using Si ₂ H ₂ Cl ₂ , SiH ₄ , Si ₂ H _6, etc. as the Si source gas, NH ₃ as the N source gas. BTBAS and NH ₃ may be used as source gases.

  After the sidewall insulating film SW is formed, ion implantation of the high concentration and deep source / drain regions SD is selectively performed on the p-type well PW and the n-type well NW using a resist mask. Impurities obtained by ion-implanting n-type impurities and P for p-type well NMOS transistors, and p-type impurities and B for n-type well PMOS transistors, and ion-implanted by RTA (rapid thermal anneal) heat treatment Is activated to form an n-type source / drain region SDn and a p-type source / drain region SDp.

As shown in FIG. 1F, a resist mask PR3 that opens a region from which the sidewall insulating film is removed is formed. For example, the sidewall insulating film is removed from a region where a contact hole may be formed. The removal of the silicon oxide sidewall insulating film can be performed by, for example, wet etching with dilute hydrofluoric acid. When the element isolation region is an HDP oxide film and the sidewall insulating film is a silicon oxide film formed using BTBAS, the etch rate of the wet etching of dilute hydrofluoric acid aqueous solution of HF: H ₂ O = 1: 200 is The sidewall insulating film is preferentially etched by 2 to 3 times higher than the wall insulating film. Instead of wet etching, chemical dry etching using a mixed gas of CF ₄ and O ₂ may be performed.

  The sidewall insulating film removal region is referred to as an increased silicide region. The sidewall insulating film mainly has a function of 1) separating the ion implantation region from the gate electrode, and 2) insulating and protecting the side surface of the gate electrode and improving the coverage with respect to the step of the gate electrode. Since ion implantation is not performed in the element isolation region, the function 1) is not originally provided, and even if the sidewall insulating film is removed from the polysilicon wiring, only the function 2) is changed. Thereafter, when a stress insulating film such as a silicon nitride film is deposited, the function of insulating protection is provided by the stress insulating film. If there is no problem in coverage, the sidewall insulating film may be removed.

  When the sidewall insulating film is removed and the side surface of the polysilicon wiring is exposed, in the subsequent silicidation process, silicidation from the side surface becomes possible as well as silicidation from the upper surface. A thicker silicide layer can be formed as compared with a gate electrode in which silicidation occurs only from the upper surface, wiring resistance can be reduced, and resistance to overetching from the upper surface can be improved.

  FIG. 1G shows a state in which the sidewall insulating film is removed in the increased silicide region and then the resist pattern PR3 is removed. FIG. 2 is a top view of this state. In this state, a silicidation process is performed.

  As shown in FIG. 1H, a nickel layer 20 is deposited on the substrate by sputtering from a plurality of oblique directions inclined from the substrate normal, so that the thickness on the side surface of the polycrystalline silicon wiring layer becomes 20 nm to 40 nm. To.

As shown in FIG. 1I, in an inert gas atmosphere such as Ar, under a pressure of 0.3 Pa to 10 Pa, a temperature of 220 ° C. to 270 ° C. for 120 seconds to 300 seconds, preferably a temperature of 240 ° C. for 120 seconds. When heat treatment is performed for ˜200 seconds, a nickel silicide layer mainly composed of dinickel silicide (Ni ₂ Si) is formed on the exposed silicon surface. Subsequently, it is washed out with SPM (sulfuric acid / hydrogen peroxide mixture) to remove unreacted nickel. Further, if necessary, heat treatment is performed in an inert atmosphere at a temperature of 200 ° C. to 400 ° C. for 30 seconds to 600 seconds to reduce silicide resistance. In this step, it is converted to nickel monosilicide.

  When a silicide reaction having a thickness of 20 nm or more is caused from each interface of the nickel layer / silicon layer, the entire width of the silicon wiring having a wiring width of 40 nm from which the sidewall insulating film has been removed is silicided to form the silicide wiring 23. Also in the height direction, since a nickel layer of 20 nm or more is formed on all side surfaces of the silicon wiring, the entire height of the silicon wiring can be silicided (full silicidation). In the silicon wiring (including the gate electrode) from which the sidewall insulating film has not been removed, the silicide layer 21 having a thickness of about 20 nm or more is formed from the upper surface, but the polycrystalline silicon layer 17 remains below the polysilicon layer 17 and the polycide gate. An electrode is formed. A silicide layer 22 is also formed on the exposed surface of the source / drain region. However, siliciding the total thickness of the silicon wiring is not essential. By forming a silicide layer thicker than the silicide layer of the gate electrode on the active region on the silicon wiring in the increased silicide region, the wiring resistance (at least increase thereof) can be suppressed. In addition, contact holes can be stably formed in the wiring.

As shown in FIG. 1J, a silicon nitride film 26 having tensile stress is deposited on the entire surface of the substrate by CVD. For example, using a parallel plate plasma CVD apparatus, a silane-based gas such as SiH ₄ , SiH ₂ Cl ₂ , Si ₂ H ₄ , Si ₂ H _6, etc. is 5 sccm to 50 sccm, NH ₃ gas is 500 sccm to 10,000 sccm, nitrogen, argon, A silicon nitride film 26 is deposited to a thickness of about 60 nm at a pressure of 0.1 Torr to 400 Torr and a temperature of 200 ° C. to 450 ° C. by supplying helium or the like as a carrier gas at 500 sccm to 10,000 sccm. A silicon oxide film 27 that functions as an etch stopper is formed on the silicon nitride film 26. For example, a silicon oxide film having a thickness of 5 nm to 10 nm is deposited by plasma CVD at 400 ° C. using SiH ₄ gas and O ₂ gas.

As shown in FIG. 1K, the NMOS transistor region is covered with a resist mask PR4, and reactive ion etching (RIE) using a gas such as C ₄ F ₈ , Ar, or O ₂ is used to form a silicon oxide film 27 on the PMOS transistor region. Then, the tensile stress silicon nitride film 26 is removed.

As shown in FIG. 1L, after removing the resist mask PR4, a silicon nitride film 29 having compressive stress is deposited on the entire surface of the substrate by CVD. For example, methylsilane-based gas (CH ₃ ) ₄ Si or (CH ₃ ) ₃ SiH is supplied at 100 sccm to 1000 sccm, NH ₃ gas is supplied at 500 sccm to 10,000 sccm, nitrogen, argon, helium, etc. are supplied as carrier gases at 500 sccm to 10,000 sccm, and pressure is 2 Torr to A silicon nitride film 29 is formed to a thickness of 60 nm at 10 Torr, a temperature of 400 ° C. to 700 ° C., and an RF power of 100 W to 1000 W.

As shown in FIG. 1M, the PMOS transistor region is covered with a resist mask PR5, and the compressive stress silicon nitride film 29 on the NMOS transistor region is formed by reactive ion etching using a gas such as C ₄ F ₈ , Ar, or O _2. Remove. In this etching, the silicon oxide film 27 functions as an etching stopper and protects the underlying silicon nitride film 26. Thereafter, the resist mask PR5 is removed.

  As shown in FIG. 1N, a silicon oxide film 30 is deposited on the entire surface of the substrate by a thickness of about 600 nm by plasma CVD using tetraethoxysilane (TEOS) as a source gas, and the surface is planarized by CMP.

As shown in FIG. 1O, a resist pattern PR6 having a contact hole-shaped opening is formed on the silicon oxide film 30. Using the resist pattern PR6 as an etching mask, first, reactive ion etching of the silicon oxide film 30 is performed using an etching gas mainly composed of CF ₄ and H ₂ . Subsequently, the silicon oxide film 27 is etched using an etching gas mainly composed of C ₄ F ₈ , Ar, and O ₂ .

The resist pattern PR6 is removed, and the silicon nitride films 26 and 29 are etched using an etching gas mainly composed of CHF ₃ to expose the silicon surface. At this time, the etching over amount in the etching of the silicon nitride film is set to 150% to 200%, for example.

  In this way, the contact hole CH1 for the single source / drain region of the NMOS transistor, the contact hole CH2 for the gate wiring covered with the single stress insulating film on the element isolation region, and the dual stress insulating film on the element isolation region are covered. A contact hole CH3 for the broken gate wiring and a contact hole CH4 for the interconnection point of the parallel PMOS transistors are formed.

  Although the contact hole CH1 is deep, the etching stopper layer does not become abnormally thick. The contact hole CH2 is shallow and the etching stopper layer does not become abnormally thick. Although the contact hole CH3 is shallow, if the etching stopper layer overlaps, the total thickness of the etching stopper layer becomes remarkably thick. The contact hole CH4 may be deep and the etching stopper layer may be abnormally thick. The etching stopper layer is often formed of a material having a low etching rate, and is not not etched at all. When etching a deep contact hole, the shallow contact hole is not deeper than the etching stopper layer, but the etching stopper layer may be thinner. When overetching is increased by etching the etching stopper layer, the base of the etching stopper layer is excessively etched. Such excessive etching on the underlayer is most likely to occur in the contact hole CH2, and is likely to occur next in the contact hole CH1.

  When the contact holes CH2 and CH4 are compared, CH2 is shallow and there is no cause for hindering etching of the etching stopper. When a thick etching stopper is formed in CH4, a large over-etching amount is required for CH4. During this over-etching, CH2 is excessively etched. By making the silicide layer thick, disappearance of the silicide layer can be prevented. The same situation occurs not only in CMOS.

  Comparing contact holes CH2 and CH3, CH2 is covered with a single stress insulating film, but CH3 is covered with a dual stress insulating film. A large over-etching amount is required for CH3. During this over-etching, CH2 is excessively etched. By making the silicide layer thick, disappearance of the silicide layer can be prevented. The dual stress insulating film is a component of CMOS.

  As shown in FIG. 1P, Ti and TiN are sputtered and a W film is grown by CVD to form a conductive plug 32 in the contact hole. The unnecessary metal layer on the surface is removed by CMP. If necessary, insulating layer formation and wiring embedding are repeated to form multilayer damascene wiring. In this way, a semiconductor device is completed.

  In the process of FIG. 1H, silicide metal is deposited from a plurality of oblique directions to form a metal layer having a uniform thickness on the side surface of the silicon wiring. However, a simplified method can be used.

  FIG. 1Q shows a case where silicide metal is deposited along the normal direction from above the substrate. Side surfaces of the silicon wiring from which the sidewall insulating film has been removed are exposed. The sputtered metal flies with a certain spread and deposits from the upper surface to the upper part of the side surface. By performing silicidation using this side surface portion, a silicide thicker than the silicide layer of the gate electrode provided with the sidewall insulating film can be formed.

  Even in the case where the formation of the contact hole is not easy, the contact hole is surely formed by increasing the over-etching amount. By forming a thick silicide layer on the wiring that can be exposed to excessive over-etching, stable contact characteristics can be secured.

  3A and 3B show two typical criteria for setting the augmented silicide region.

  As shown in FIG. 3A, the element isolation region STI defines active regions AR1 and AR2, and a gate wiring GW1 is disposed across the active regions AR1 and AR2. In the middle of the two active regions, the gate line GW1 is connected to the upper layer line. An increased silicide region IS is set in a region including the connection position.

  In FIG. 3B, all regions separated from the active region by a predetermined distance or more are set as increased silicide regions. A connection position of the gate wiring is selected in the increased silicide region. The gate wirings GW2 and GW3 do not have connection points, but do not include a sidewall insulating film, and therefore have a small occupied area and are arranged with high density.

  If the main portion of the polycrystalline silicon wiring on the element isolation region is fully silicidized, the wiring resistance can be greatly reduced. Also in this case, since the gate electrode maintains a polycide structure, threshold control can be performed with high reliability and high accuracy.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, the silicide metal is not limited to nickel. The silicide metal can be selected from nickel, titanium, cobalt, platinum, and alloys of these metals. The main conductor of the conductive plug is not limited to W. Cu or the like can also be used. The element isolation region may be formed by LOCOS (local oxidation of silicon) instead of STI. It will be apparent to those skilled in the art that other various modifications, improvements, substitutions, combinations, and the like are possible.

  The features of the present invention will be described below.

(Appendix 1)
A semiconductor substrate having an active region and an element isolation region;
A conductive layer formed on the active region and the element isolation region;
A first silicide layer formed on the conductive layer located on the active region;
A second silicide layer formed on the conductive layer located on the element isolation region and thicker than the first silicide layer;
A sidewall insulating film covering a sidewall of the conductive layer located on the active region and exposing at least a part of the sidewall of the conductive layer located on the blocking isolation region;
A semiconductor device.

(Appendix 2)
The semiconductor device according to claim 1, wherein the conductive layer is a gate electrode formed on the semiconductor substrate through a gate insulating film in the active region.

(Appendix 3)
The semiconductor device according to appendix 1 or 2, further comprising a stress insulating film formed on the semiconductor substrate and covering the conductive layer.

(Appendix 4)
An interlayer insulating film formed on the stress insulating film;
A contact hole formed in the interlayer insulating film and the stress insulating film and reaching the second silicide layer;
The semiconductor device according to any one of appendices 1 to 3, further comprising:

(Appendix 5)
A silicon substrate having an element isolation region defining a plurality of active regions;
A plurality of field effect transistors formed in the plurality of active regions, respectively;
A gate electrode structure including a polysilicon layer, a sidewall insulating film formed on the sidewall thereof, and a silicide layer formed by silicidizing an upper portion of the polysilicon layer;
A source / drain region formed in active regions on both sides of the gate electrode structure and having a silicide layer;
A plurality of field effect transistors having:
An increased silicide region is formed on the element isolation region using the same material as the gate electrode structure, the sidewall insulating film is selectively removed, and a silicide layer thicker than the silicide layer of the gate electrode structure is formed. Having wiring;
Covering the plurality of field effect transistors, a stress insulating film formed on a silicon substrate;
An interlayer insulating film formed above the stress insulating film;
A plurality of conductive plugs penetrating the interlayer insulating film and the stress insulating film and connected to the source / drain regions and the wiring;
A semiconductor device.

(Appendix 6)
The semiconductor device according to claim 5, wherein the sidewall insulating film is removed over the entire height of the side wall of the polysilicon layer in the increased silicide region.

(Appendix 7)
The semiconductor device according to appendix 6, wherein the silicide layer is formed over the entire thickness and width of the wiring in the increased silicide region.

(Appendix 8)
The plurality of field effect transistors include an n-channel field effect transistor and a p-channel field effect transistor;
The stress insulating film includes a tensile stress insulating film covering the n-channel field effect transistor and a compressive stress insulating film covering the p-channel field effect transistor;
The semiconductor device according to any one of appendices 5 to 7.

(Appendix 9)
The semiconductor device according to claim 8, wherein the tensile stress insulating film and the compressive stress insulating film are silicon nitride films, and the interlayer insulating film is a silicon oxide film.

(Appendix 10)
The semiconductor device according to appendix 8 or 9, wherein the tensile stress insulating film and the compressive stress insulating film are formed so as to overlap each other on the wiring.

(Appendix 11)
Forming an element isolation region in a semiconductor substrate;
Forming a pattern including silicon on the element isolation region and an active region defined by the element isolation region;
Forming a sidewall insulating film on the sidewall of the pattern;
Removing the sidewall insulating film formed on the sidewall of the pattern on the element isolation region using a mask covering the pattern on the active region;
Forming a silicide layer on the pattern by forming a metal layer covering the pattern and reacting the pattern with the metal layer;
A method for manufacturing a semiconductor device comprising:

(Appendix 12)
12. The method of manufacturing a semiconductor device according to claim 11, wherein the pattern is a gate electrode formed on the semiconductor substrate via a gate insulating film in the active region.

(Appendix 13)
Forming a stress insulating film on the silicide layer;
Fixing to form an interlayer insulating film on the stress insulating film;
Forming a contact hole reaching the pattern located in the element isolation region in the interlayer insulating film and the stress insulating film;
The method for manufacturing a semiconductor device according to appendix 11 or 12, further comprising:

(Appendix 14)
14. The method of manufacturing a semiconductor device according to any one of appendices 11 to 13, wherein the stress insulating film includes a first stress insulating film having a tensile stress and a second stress insulating film having a compressive stress.

(Appendix 15)
(A) forming an element isolation region for defining a plurality of active regions on a silicon substrate;
(B) Forming a gate insulating film on the surface of the plurality of active regions, depositing a polysilicon layer on the entire surface of the substrate, and patterning, thereby wiring the gate electrode of the field effect transistor above the active region and wiring above the element isolation region Forming a step;
(C) forming a sidewall insulating film on the gate electrode and the sidewall of the wiring;
(D) forming a source / drain region of a field effect transistor by ion-implanting impurities into the active region via the gate electrode and the sidewall insulating film;
(E) using a mask having an opening on a selected region of the element isolation region, removing the sidewall insulating film in the opening and exposing a side surface of the wiring;
(F) forming a metal layer covering the gate electrode and the wiring on the silicon substrate, and performing a heat treatment;
(G) forming a stress insulating film covering the field effect transistor;
(H) forming an interlayer insulating film above the stress insulating film;
(I) forming a contact hole that reaches the wiring through the interlayer insulating film and the stress insulating film;
(J) burying a conductive plug in the contact hole;
A method of manufacturing a semiconductor device including:

(Appendix 16)
The semiconductor device manufacturing method according to claim 15, wherein the step (a) includes a step of forming a groove in the silicon substrate and a step of depositing a silicon oxide film in the groove.

(Appendix 17)
The step (c) includes a step of depositing the silicon oxide film using Vista butylaminosilane, and a step of anisotropically etching the silicon oxide film to process it into the sidewall insulating film. e) A method for manufacturing a semiconductor device according to appendix 15 or 16, comprising a step of removing the sidewall insulating film of the silicon oxide film using a dilute hydrofluoric acid aqueous solution.

(Appendix 18)
Any one of Supplementary Notes 15 to 17, wherein the step (g) includes a step of depositing a tensile stress silicon nitride film using a silane-based gas and a step of depositing a compressive stress silicon nitride film using a methylsilane-based gas. A method for manufacturing a semiconductor device according to claim 1.

(Appendix 19)
The step (a) selectively forms a p-type well for forming an n-channel field effect transistor and an n-type well for forming a p-channel field effect transistor,
In the step (d), a p-type impurity is ion-implanted into the n-type well, and an n-type impurity is ion-implanted into the p-type well.
The step (g) forms a tensile stress insulating film on the n-channel field effect transistor and a compressive stress insulating film on the p-channel field effect transistor;
The method for manufacturing a semiconductor device according to any one of appendices 15 to 18.

(Appendix 20)
In the step (g), an overlapping silicon nitride film is formed on the element isolation region, and in the step (e), a side surface of the wiring is exposed under the overlap, and the steps (i), ( (20) A method for manufacturing a semiconductor device according to appendix 19, wherein j) forms a conductive plug that penetrates the overlapping silicon nitride film.

/ / / 1A to 1P are cross-sectional views of a silicon substrate showing a method of manufacturing a semiconductor device according to an embodiment, and FIG. 1Q is a cross-sectional view of a silicon substrate showing a modification. It is a top view of the semiconductor device by an example. 3A and 3B are plan views showing the arrangement of the element isolation region and the increased silicide region, showing two typical criteria for setting the increased silicide region. It is a circuit diagram of an exclusive NOR circuit. It is sectional drawing of the CMOS semiconductor device which has a silicide layer, a tensile stress film | membrane, and a compressive stress film | membrane by a prior art.

Explanation of symbols

11 silicon substrate, 12 buffer oxide film, 13 silicon nitride film, 14 HDP silicon oxide film, 16 gate insulating film, 17 polysilicon film, 20 nickel layer, 21 (gate electrode) silicide layer, 22 (on source / drain region) ) Silicide layer, 23 (gate wiring) silicide layer, 26 tensile stress silicon nitride film, 27 silicon oxide film, 29 compressive stress silicon nitride film, 30 silicon oxide film (main interlayer insulating film), 32 conductive plug, PR Resist (pattern), T trench, Pk pocket, Ex extension, SD source / drain region, G gate electrode, SW sidewall insulating film.

Claims (10)

A semiconductor substrate having an active region and an element isolation region;
A conductive layer formed on the active region and the element isolation region;
A first silicide layer formed on the conductive layer located on the active region;
A second silicide layer formed on the conductive layer located on the element isolation region and thicker than the first silicide layer;
A sidewall insulating film covering a sidewall of the conductive layer located on the active region and exposing at least a part of the sidewall of the conductive layer located on the blocking isolation region;
A semiconductor device.   The semiconductor device according to claim 1, further comprising a stress insulating film formed on the semiconductor substrate and covering the conductive layer. An interlayer insulating film formed on the stress insulating film;
A contact hole formed in the interlayer insulating film and the stress insulating film and reaching the second silicide layer;
The semiconductor device according to claim 1, further comprising: A silicon substrate having an element isolation region defining a plurality of active regions;
A plurality of field effect transistors formed in the plurality of active regions, respectively;
A gate electrode structure including a polysilicon layer, a sidewall insulating film formed on the sidewall thereof, and a silicide layer formed by silicidizing an upper portion of the polysilicon layer;
A source / drain region formed in active regions on both sides of the gate electrode structure and having a silicide layer;
A plurality of field effect transistors having:
An increased silicide region is formed on the element isolation region using the same material as the gate electrode structure, the sidewall insulating film is selectively removed, and a silicide layer thicker than the silicide layer of the gate electrode structure is formed. Having wiring;
Covering the plurality of field effect transistors, a stress insulating film formed on a silicon substrate;
An interlayer insulating film formed above the stress insulating film;
A plurality of conductive plugs penetrating the interlayer insulating film and the stress insulating film and connected to the source / drain regions and the wiring;
A semiconductor device. The plurality of field effect transistors include an n-channel field effect transistor and a p-channel field effect transistor;
The stress insulating film includes a tensile stress insulating film covering the n-channel field effect transistor and a compressive stress insulating film covering the p-channel field effect transistor;
The semiconductor device according to claim 4. Forming an element isolation region in a semiconductor substrate;
Forming a pattern including silicon on the element isolation region and an active region defined by the element isolation region;
Forming a sidewall insulating film on the sidewall of the pattern;
Removing the sidewall insulating film formed on the sidewall of the pattern on the element isolation region using a mask covering the pattern on the active region;
Forming a silicide layer on the pattern by forming a metal layer covering the pattern and reacting the pattern with the metal layer;
A method for manufacturing a semiconductor device comprising: Forming a stress insulating film on the silicide layer;
Fixing to form an interlayer insulating film on the stress insulating film;
Forming a contact hole reaching the pattern located in the element isolation region in the interlayer insulating film and the stress insulating film;
The method of manufacturing a semiconductor device according to claim 6, further comprising:   8. The method of manufacturing a semiconductor device according to claim 6, wherein the stress insulating film includes a first stress insulating film having a tensile stress and a second stress insulating film having a compressive stress. (A) forming an element isolation region for defining a plurality of active regions on a silicon substrate;
(B) Forming a gate insulating film on the surface of the plurality of active regions, depositing a polysilicon layer on the entire surface of the substrate, and patterning, thereby wiring the gate electrode of the field effect transistor above the active region and wiring above the element isolation region Forming a step;
(C) forming a sidewall insulating film on the gate electrode and the sidewall of the wiring;
(D) forming a source / drain region of a field effect transistor by ion-implanting impurities into the active region via the gate electrode and the sidewall insulating film;
(E) using a mask having an opening on a selected region of the element isolation region, removing the sidewall insulating film in the opening and exposing a side surface of the wiring;
(F) forming a metal layer covering the gate electrode and the wiring on the silicon substrate, and performing a heat treatment;
(G) forming a stress insulating film covering the field effect transistor;
(H) forming an interlayer insulating film above the stress insulating film;
(I) forming a contact hole that reaches the wiring through the interlayer insulating film and the stress insulating film;
(J) burying a conductive plug in the contact hole;
A method of manufacturing a semiconductor device including: The step (a) selectively forms a p-type well for forming an n-channel field effect transistor and an n-type well for forming a p-channel field effect transistor,
In the step (d), a p-type impurity is ion-implanted into the n-type well, and an n-type impurity is ion-implanted into the p-type well.
The step (g) forms a tensile stress insulating film on the n-channel field effect transistor and a compressive stress insulating film on the p-channel field effect transistor;
A method for manufacturing a semiconductor device according to claim 9.

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