JP2000243835A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the capacity between wirings on a substrate, to contrive the speedup of a semiconductor device and to make it possible to eliminate a breaking-off or the like of the wirings to the utmost by a method wherein a cavity with the inner wall covered with insulating films is formed between the wirings and a part of the inner wall of the cavity is formed of a metal silicide layer. SOLUTION: A silicon oxide film 12 is formed on a silicon substrate 11 and thereafter, an amorphous silicon film 13 and a silicon oxide film 14 are formed on the film 12. After three holes are bored in the film 14, a WSi2 layer 15 and a Ti layer 16 are formed on the film 14 and are patterned. This substrate 11 is annealed for five minutes at 700 deg.C in a nitrogen atmosphere, silicon in the film 13 is sucked out in the layer 16 via the layer 15 and the layer 16 is converted into a TiSix film 18. As this result, a cavity 17 is formed in the part formed with the film 13. Thereby, the capacity between wirings on the substrate 11 can be reduced and the high-speed operation, which sharply reduces the delay of a signal, of a semiconductor device can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same which reduce the capacitance between wirings of an LSI.

[0002]

2. Description of the Related Art Basically, the performance of LSIs can be improved by increasing the degree of integration of elements, that is, by miniaturizing elements. However, when the degree of integration of the element becomes extremely high, 1) the wiring has a high resistance due to the reduction in the wiring size (wiring width and film thickness), and 2) the capacitance between the wirings has increased due to the compact wiring space. Therefore, the operating speed of the LSI is limited by the RC delay. Regarding resistance, the use of copper having a resistivity 30% lower than that of aluminum alloys has been studied. Regarding capacitance, research has been conducted on SiOF or an organic material, which is a low dielectric constant material, as a material between wirings, and further on the structure. For example, Japanese Patent Application Laid-Open No. Hei 5-21617 proposes a method for realizing a further lower dielectric constant between wirings by making a space between wirings juxtaposed in the horizontal direction.

According to this method, first, the silicon substrate 5
After the silicon oxide film 52 is formed on the substrate 0, an Al wiring pattern 53 is formed. Subsequently, a silicon oxide film 54 and an SOG film 55 are formed on the Al wiring pattern 53 (FIG. 5).
(A)). Next, after etching back until the silicon oxide film 54 is exposed (FIG. 5B), a silicon oxide film 56 is formed on the obtained silicon substrate 50, and the SOG film 5 is formed.
An opening 56a is formed on the silicon oxide film 56 and on the silicon oxide film 56 (FIG. 5C). Further, the silicon oxide film 56
A spacer 57 is formed on the side wall of the opening 56a of the silicon oxide film 56 by forming a CVD silicon oxide film thereon and performing etch back (FIG. 5D). Subsequently, the SOG film 55 below the opening 56a is selectively etched back by a wet etching method using hydrofluoric acid to form a cavity 58 (FIG. 5E).
A silicon oxide film 59 is formed to close the opening 56a (FIG. 5F). The SOG film 5 is formed on the silicon oxide film 59 again.
1 is applied and its surface is flattened (FIG. 5 (g)).

In Japanese Patent Application Laid-Open No. 7-45701,
A technique has been proposed in which an ice film previously filled between wirings is evaporated to form a cavity between wirings at the same level. According to this method, first, a desired element such as a transistor is formed on a silicon substrate, a silicon oxide film 61 is formed by a CVD method, and a wiring pattern 62 is formed on the silicon oxide film 61 (FIG. 6 ( a)). Subsequently, the atmosphere was set to 0 ° C. or lower, and water was dropped, and the silicon oxide film 61 was formed.
An ice film 63 is formed on the surface (FIG. 6B), and the ice film 63 is polished by chemical mechanical polishing until the wiring pattern 62 is exposed (FIG. 6C). Next, a porous silicon oxide film 6 is formed on the flattened ice film 63 at a temperature of 0 ° C. or less.
5 is formed. Thereafter, by performing a heat treatment at a temperature of 100 ° C. or more, the water 64 constituting the ice film 63 evaporates through the fine holes of the silicon oxide film 65, and a cavity 66 is formed (FIG. 6D). ).

Further, in Japanese Patent Application Laid-Open No. 9-237831, a carbon layer is formed at a portion where a cavity is formed, and the carbon layer is ashed by thermal oxidation or oxygen plasma treatment.
There has been proposed a technique for forming a cavity between horizontal and vertical wirings. According to this method, first, the silicon substrate 71
After forming a desired element such as a transistor, CVD
A silicon oxide film 72 by a sputtering method, a carbon layer 73 and a mask material 74 are sequentially formed by a sputtering method, and the carbon layer 73 is patterned using the mask material 74 (FIG. 7A). Subsequently, a wiring pattern 75 is embedded between the carbon layers 73 (FIG. 7B), the mask material 74 is removed, and an insulating layer 76 is formed on the carbon layer 73 and the wiring pattern 75 (FIG. 7C). )). Next, the carbon layer 73 is ashed by heat treatment in an oxygen atmosphere or oxygen plasma treatment to form a cavity 77 between the wiring patterns 75 (FIG. 7D).

[0006]

However, Japanese Patent Laid-Open Publication No.
The use of a wet etching method in the method of JP 1617 or the use of an ice film in JP-A-7-45701 makes it difficult to completely remove water in a later step, and lowers the reliability of the finally obtained semiconductor device. There is fear. Further, evaporation of an ice film disclosed in JP-A-7-45701 and JP-A-9-23
In the incineration of the carbon layer of JP 7831, cavities may burst during the process due to its structure and its vapor pressure. Further, as described in Japanese Patent Application Laid-Open No. 9-237873, when a silicon oxide film is formed on a carbon layer, carbon in the carbon layer is oxidized and gasified, so that a silicon oxide film is formed on the carbon layer. The method is limited. In addition, etching and resist ashing in which carbon contacts oxygen plasma are also limited.

The present invention has been made in view of the above problems, and provides a semiconductor device capable of realizing a higher speed by providing a cavity for reducing the capacitance between wirings, and also provides a semiconductor device which is formed in a process of forming the semiconductor device. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of minimizing factors such as a reduction in device reliability and rupture of wiring.

[0008]

According to the present invention, a cavity having an inner wall covered with an insulating film is provided between the wirings on a substrate having the wiring, and a part of the inner wall of the cavity is formed of a metal silicide. Semiconductor device formed of layers A semiconductor device is provided. Further, according to the present invention, a step of forming a first insulating layer and a silicon layer on a substrate, a step of removing the silicon layer existing between regions where wiring is to be formed, and a step of covering the remaining silicon layer Forming an insulating film, forming one or more openings in the second insulating film on the surface of the silicon layer, and forming a metal layer so as to cover at least one opening of the second insulating film Heat treating the resulting substrate to convert the metal layer to a metal silicide layer, between the regions where the wiring is to be formed, and where the silicon layer covered by the second insulating film was present And a method of manufacturing a semiconductor device including a step of forming a cavity in the semiconductor device.

Further, according to the present invention, a step of forming a first insulating layer on a substrate, forming a groove in the first insulating film between regions where wiring is to be formed, and filling the groove with a silicon layer Covering at least the silicon layer with a second insulating film, forming at least one opening in the second insulating film on the surface of the silicon layer, forming at least one opening in the second insulating film. Forming a metal layer so as to cover the substrate, and heat-treating the obtained substrate to convert the metal layer into a metal silicide layer.
A method of manufacturing a semiconductor device including a step of forming a cavity in a groove of an insulating film is provided.

Further, according to the present invention, a step of forming a first insulating layer, a silicon layer / metal layer or a metal layer / silicon layer on a substrate, and patterning the silicon layer and the metal layer into desired shapes. Forming a second insulating film covering the obtained silicon layer and the metal layer, and heat-treating the obtained substrate to convert the metal layer into a metal silicide layer, thereby forming a cavity in a portion where the silicon layer was present. A method for manufacturing a semiconductor device including a forming step is provided.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention has a cavity in which an inner wall is covered with an insulating film between the wirings on a substrate having the wiring, and a part of the inner wall of the cavity is a metal silicide layer. Be formed.

The substrate on which the semiconductor device of the present invention is formed comprises:
The semiconductor substrate is not particularly limited as long as it is a semiconductor substrate on which a semiconductor device is usually manufactured. For example, various substrates such as a semiconductor substrate such as silicon and germanium, and a compound semiconductor such as SiC, GaAs, and InGaAs are exemplified. Above all,
A silicon substrate is preferred. Also, the SOI substrate, that is,
Usually, a bonded SOI (BES) in which a buried insulating film is formed on a supporting substrate and a surface semiconductor layer is further formed thereon.
OI), SIMOX (Separation by Implantation of
Oxygen) type substrates may be used. Note that, as the supporting substrate, for example, a semiconductor substrate such as silicon or germanium, a compound semiconductor such as GaAs or InGaAs, an insulating substrate such as sapphire, quartz, glass, plastic, or the like;
As the buried insulating film, for example, a film thickness of 50 to 500 nm
Examples of the surface semiconductor layer such as a SiO ₂ film or a SiN film having a thickness of about 150 to 200 nm include a thin film made of a semiconductor such as silicon or germanium and a compound semiconductor such as GaAs or InGaAs. By using the SOI substrate, it is possible to obtain a device with higher speed than a device using a normal semiconductor substrate, which is effective as a measure against RC delay. In addition,
Elements such as PMOS, NMOS and CMOS transistors, bipolar transistors, dual-gate transistors, capacitors and resistors, desired circuits such as memory and / or logic circuits, insulating layers, wiring layers, and the like are formed on the substrate. Is also good.

The wiring provided on the substrate is formed by a conductive layer for obtaining electrical connection between elements such as transistors and capacitors, between circuits, and with the outside. There is no particular limitation.

The cavity of the semiconductor device of the present invention is substantially covered with an insulating film formed between the wirings, usually for electrically separating the wirings or protecting the wirings. The space formed, that is,
This means a space in which the inner wall is substantially covered with an insulating film, but a part of the inner wall of the cavity is formed by a metal silicide layer. Touching. The cavity in the present invention also includes a cavity in which another part of the inner wall of the cavity is formed of wiring or another conductive layer, and a cavity having one or more holes in the inner wall of the cavity. Here, the hole is
Means that the cavity is formed so as to be in contact with the outside air.If the cavity is in contact with the outside air, a part of the inner wall of the cavity or the entire inner wall other than the portion where the metal silicide layer is formed is formed of the passivation film. Are included in the cavity of the present invention. When the cavity is in contact with the outer wall and the inner wall is covered with the passivation film, the reliability of the finally obtained semiconductor device can be improved, and a further cooling effect can be obtained. The term "between wirings" includes any of between wirings existing in a horizontal direction with respect to the substrate surface, between wirings existing in a vertical direction like a multilayer wiring structure, and between wirings existing in an oblique direction in a multilayer wiring structure. . Further, one cavity may be formed between one set of wirings, or two or more cavities may be formed. The size of the cavity is not particularly limited, and can be appropriately adjusted depending on the wiring pattern of the obtained semiconductor device.

As an insulating film for covering the inner wall of the cavity,
The insulating film is preferably an insulating film that does not easily react with a metal constituting a metal silicide layer described later. For example, a silicon oxide film by a CVD method, a plasma TEOS by a CVD method
(Tetra-Ethoxy Silane) film, LTO (Low Temperature)
Oxide) film, HTO (High Temperature Oxide) film, N
An SG (None-Doped Silicon Glass) film, an SOG (Spin On Glass) film formed by a spin coating method, a silicon nitride film, and the like can be given. Above all, a silicon oxide film formed by a CVD method is more preferable.

The material of the metal silicide layer covering a part of the inner wall of the cavity is not particularly limited as long as it is a silicide layer made of a metal in which Si can be a diffusion species by an appropriate heat treatment. For example, Ti, Hf, V, Ta, Mo, W and F
e, a silicide layer of one or more metals or alloys selected from the group consisting of e. Specifically, TiS
_{i 2, HfSi 2, VSi 2} , TaSi 2, MoSi 2, W
Si ₂ , FeSi _{2 and the} like can be mentioned. The size of a part of the inner wall of the cavity covered by the metal silicide layer can be appropriately adjusted depending on the size of the cavity, the type of the metal silicide layer, the temperature at which the metal silicide layer is formed, and the like. Note that this metal silicide layer may not only cover a part of the inner wall of the cavity but also function as the wiring itself or a part of the wiring.
The wiring and the conductive layer which may partially cover the inner wall of the cavity are made of, for example, TiSi ₂ , HfSi ₂ , VSi ₂ ,
It can be formed of aSi ₂ , MoSi ₂ , WSi ₂ , FeSi ₂ or the like. Further, the passivation film which may cover a part of the inner wall of the cavity can be formed of, for example, a silicon nitride film, a PSG (phosphorus-doped silicon oxide film) or the like.

In the method of manufacturing a semiconductor device according to the present invention, a cavity is formed between wirings by utilizing a phenomenon in a reaction between a silicon layer and a metal layer. As a first phenomenon, for example, a case where a part of a silicon layer is brought into contact with a metal layer and another part of the silicon layer is covered with an insulating film using a metal layer such as titanium in which a diffusion species is silicon. By performing the heat treatment, a silicon layer is sucked up in the metal layer, and a cavity is formed in a portion where silicon is present. Also, as a second phenomenon, for example, when a volume of silicon 2.3 reacts with metal 1 such as titanium, the volume of metal + silicon finally becomes about 2.10 with respect to the initial volume. 4 / 3.3. For this reason, when the metal layer and the silicon layer are covered with an insulating film having low reactivity, the volume of the portion covered with the insulating film is reduced due to the reaction between the metal layer and the silicon layer, and a cavity is formed.

In the method of manufacturing a semiconductor device according to the present invention, first, a first insulating layer and a silicon layer are formed on a substrate, and the silicon layer existing in a region where a wiring is to be formed is removed. Is formed to cover the second insulating film. Here, the material of the first and second insulating films is not particularly limited, and examples thereof include the same materials as the above-described insulating films. Among them, a material that does not easily react with a metal layer described later is preferable, and for example, a silicon oxide film formed by a CVD method is preferable. Note that the first insulating film is
It may be formed as an interlayer insulating film covering elements and circuits formed on the substrate, or may be subjected to planarization after forming the first insulating film. First
The thickness of the insulating film is, for example, about 5000 to 20000 °.

The silicon layer formed on the first insulating film is
The layer may be made of any of amorphous silicon, single crystal silicon, and polycrystalline silicon, but is preferably a layer made of amorphous silicon. The silicon layer can be formed, for example, with a thickness of about 1000-15000 °. This silicon layer defines a region where a cavity is formed in a later step, and is usually formed so as to exist between wirings formed in the later step. Specifically, after the silicon layer is formed on the entire surface of the first insulating film, the silicon layer existing in the region where the wiring is to be formed is formed by a known method, for example, a photolithography and etching process. Formed by etching.

The second insulating film that completely covers the silicon layer is preferably formed to a thickness that can prevent a reaction between the metal layer formed in a later step and the silicon layer.
Specifically, about 100-1000 degrees are mentioned. Next, an opening is formed in the second insulating film on the surface of the silicon layer. The number of openings formed here may be one or two or more.
It may be formed on an insulating film. The size of the hole is not particularly limited, but in one case, a silicidation reaction between the silicon layer and a metal layer described later is performed through the hole, so that the silicidation reaction is not sufficiently performed. It must be large enough to be performed. That is, the size of the hole can be determined according to the thickness, width, length, and the like of the silicon layer.
In the case of a polysilicon layer having a thickness of about 1 μm, holes having a diameter of about 1 μm can be given. In the case of two or more holes, it is preferable that at least one hole is a hole for the finally formed cavity to be in contact with the outside air. For example, heat generated by wiring adjacent to the cavity is efficiently used. It is preferable that the size is such that it can be released to the surface.

Subsequently, a metal layer is formed on the second insulating film.
You. The metal layer is silicided with the silicon layer to form a metal silicide.
A layer consisting of metal atoms that can form a side
If it is not particularly limited, for example, Ti, H
selected from the group consisting of f, V, Ta, Mo, W and Fe
Single or multiple layers of one or more metals or alloys
There are several layers. The shape is not particularly limited
However, if the second insulating film has one hole,
And plug one opening to make contact with the silicon layer
It is necessary to form such a shape. In addition, opening 2
If more than one, at least one of the openings will not be blocked
It is preferable to have such a shape. The thickness of the metal layer
The silicon layer formed and the silicon layer
Secure metal atoms necessary for complete silicidation reaction
The thickness must be large enough to
Adjust appropriately according to the thickness, size, etc. of the silicon layer formed
Can be adjusted. For example, about 430-7000
The film thickness is mentioned. Note that the metal layer is formed of the above-described metal or
In addition to a single layer or multiple layers of an alloy,
Layer of silicide made of metal or alloy
Good. Silicide is placed under the metal to form the metal layer
In this case, place more over the holes formed in the second insulating film.
This is advantageous because the metal layer can be formed flat.
is there. As the laminated layer, for example, Ti / TiSi_Two, T
i / TaSi_Two, Ti / MoSi_Two, Ti / WSi_Two, T
i / FeSi_Two, Ta / TiSi_Two, Ta / TaSi_Two,
Ti / WSi _Two, W / TiSi_Two, W / TaSi_Two, W /
MoSi_Two, W / WSi_Two, W / FeSi_TwoEtc.
You.

Next, the obtained substrate is heat-treated. The heat treatment here needs to be performed at a temperature higher than the temperature at which the silicon layer and the metal layer undergo a silicidation reaction.
Heat treatment in a temperature range of about to 900 ° C. is exemplified. Thereby, the metal layer can be converted into the metal silicide layer, and at the same time, the silicon layer is sucked up to diffuse into the metal layer through the hole formed in the second insulating film, and the first layer is sucked.
A cavity can be formed between the insulating film and the second insulating film, that is, in the space where the silicon layer existed. Other conditions of the heat treatment here are not particularly limited as long as the conditions can surely perform the silicidation reaction.
For example, under an atmosphere of nitrogen, air, argon, helium, or the like, for a period of several seconds to about 60 minutes.

In the method of manufacturing a semiconductor device according to the present invention, after the above-described steps, a through hole is further formed in the first insulating film and / or the second insulating film existing in the region where the wiring is to be formed. By forming a barrier metal and a wiring layer on a substrate including a region where a through hole and a wiring are to be formed, and patterning the barrier metal and the wiring layer, a wiring can be formed in a desired region.

Here, the through holes formed in the first and second insulating films penetrate these insulating films, and are connected to elements such as a substrate, a wiring or a transistor existing under the first insulating film and the first insulating film or It is formed to connect a wiring or an element such as a transistor formed on the second insulating film. The material, film thickness, forming method, and the like constituting the barrier metal and the wiring layer can be appropriately selected and used according to a known technique. The barrier metal and the wiring layer can be patterned into a desired shape by a known method, for example, a photolithography and etching process, a chemical mechanical polishing method, and the like. It is preferable that the barrier metal and the wiring layer are buried in the region where the metal is to be formed, and the surfaces of the barrier metal and the wiring layer are planarized with the surface of the second insulating film. In addition, the barrier metal and / or the wiring
The metal silicide layer may be formed so as to be directly connected to the metal silicide layer formed by forming the cavity, and the metal silicide layer may be used as the wiring itself or a part of the wiring.

In the present invention, a device having a multilayer wiring structure can be formed by repeating the above-described step of forming the first insulating film to the step of patterning the barrier metal and the wiring layer a plurality of times. Further, when the above process is repeated a plurality of times to form a multilayer wiring structure,
By design, the cavities in each layer of the multi-layer wiring may be arranged so as to overlap when viewed from above, and finally a through hole may be formed to penetrate these cavities, so that the cavities come into contact with the outside air. In this case, it is preferable that a passivation film is formed in the through hole so that the cavity is covered with the passivation film.

Further, according to another method for manufacturing a semiconductor device of the present invention, first, a first insulating layer is formed on a substrate, and a groove is formed in the first insulating film between regions where wiring is to be formed. The trench is filled with a silicon layer, and a second insulating film is formed so as to cover at least the silicon layer. As the first insulating film and the second insulating film, the same one as described above can be used. The groove formed in the first insulating film defines a region where a cavity is formed in a later step, and is usually formed so as to exist between wirings formed in a later step. Specifically, the first insulating film existing between the regions where the wiring is to be formed is removed by a known method, for example, a photolithography and etching process. At this time, the depth and shape of the groove can be appropriately adjusted according to the size and shape of the cavity to be formed. Thereafter, a silicon layer is formed on the first insulating film, preferably in a thickness greater than the depth of the groove, and the groove is filled with the silicon layer by etch-back or chemical mechanical polishing.

Thereafter, the step of forming an opening in the second insulating film on the surface of the silicon layer, the step of forming a metal layer on the second insulating film, and the step of heat-treating the obtained substrate are substantially as described above. It can be performed in the same manner as the method. Further, following the above method, further, a metal silicide layer and a third insulating film having a substantially flat surface are formed on the substrate including the metal silicide layer, and a first insulating film existing in a region where a wiring is to be formed. Forming a through hole in the second insulating film and the third insulating film, forming a groove in the third insulating film and the metal silicide layer in a region where a wiring is to be formed, and forming a barrier metal and a substrate on the substrate including the through hole and the groove. By forming a wiring layer and patterning these barrier metal and wiring layer,
Wiring can be formed in a desired region. These steps can be performed in substantially the same manner as described above. Since the barrier metal and the wiring layer formed here are in direct contact with a part of the metal silicide layer formed when the cavity is formed, the metal silicide layer functions as the wiring itself or a part of the wiring. Can be done.

According to still another method of manufacturing a semiconductor device in the present invention, first, a first insulating layer is formed on a substrate,
Forming a silicon layer / metal layer or a metal layer / silicon layer on the first insulating layer, patterning the silicon layer and the metal layer into desired shapes, and covering the obtained silicon layer and the metal layer with a second insulating film To form Subsequent steps can form cavities in substantially the same manner as described above. Here, the layers on the first insulating layer and covered with the second insulating film include a silicon layer / metal layer, a silicon layer / metal silicide layer / metal layer, a metal layer / silicon layer, and a metal layer / metal A laminated structure such as a silicide layer / silicon layer may be used. These layers can be formed substantially in the same manner as described above. Note that the thickness of these layers can be appropriately adjusted in consideration of the size of the cavity formed by reducing the volume by the silicidation reaction between the metal layer and the silicon layer. Also in this method, an opening may be formed on the upper surface or side surface of the second insulating film. Note that the metal silicon layer located immediately below the cavity formed here can be used as a wiring or a part of a wiring. In addition, by repeating the steps from the step of forming the first insulating film to the step of forming the cavity a plurality of times, a device having a multilayer wiring structure can be formed.

Hereinafter, a semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the drawings.

First Embodiment First, as shown in FIG. 1A, a silicon oxide film 12 is formed on a silicon substrate 11 by a CVD method at a thickness of 10000. Subsequently, as shown in FIG. 1B, an amorphous silicon film 13 is formed on the entire surface of the silicon oxide film 12 by CV.
A 2300 [deg.] Film is formed by the method D, and is patterned into a desired shape by a normal photolithography and etching process so as to remove the amorphous silicon film 13 in the region 30b where the wiring is to be formed. Then, CVD
A silicon oxide film 14 is further formed at 500.degree.

Next, as shown in FIG. 1C, one or more holes, for example, three holes are formed in the silicon oxide film 14 on the amorphous silicon film 13 by ordinary photolithography and etching steps. Subsequently, a WSi ₂ layer 15 formed by CVD is formed on the entire surface of the obtained silicon substrate 11 at a thickness of 300 ° C., and Ti is formed thereon by sputtering.
The film 16 is 2000Å formed by conventional photolithography and etching process to pattern the Ti layer 16 and WSi ₂ layer 15. Here, at least one hole is formed for each contact between the WSi ₂ film 15 and the amorphous silicon film 13 and at least one hole is formed for the amorphous silicon film 13 to contact the outside air.

Subsequently, as shown in FIG. 1D, the obtained silicon substrate 11 was placed in a nitrogen atmosphere at 700 ° C.
By annealing for 5 minutes, the silicon in the amorphous silicon film 13 is sucked out into the Ti layer 16 via the WSi ₂ film 15, and the Ti layer 16 is converted into TiSix (x ≦ 2).
It is converted into a film 18. As a result, a cavity 17 is formed in the portion where the amorphous silicon film 13 was formed.

Embodiment 2 First, as shown in FIG. 2A, a silicon oxide film 12 is formed by a CVD method on a silicon substrate 11 on which a desired element (not shown) such as a transistor is formed at 15000.degree. Then, the surface of the silicon oxide film 12 is removed by 5000 ° by chemical mechanical polishing. Subsequently, an amorphous silicon film 23 is formed at 2300 ° by a sputtering method, and the amorphous silicon film 23 in a region where a wiring is to be formed in a later process is formed by a usual photolithography and etching process.
Is removed, and a silicon oxide film 24 is formed on the obtained silicon substrate 11 by a CVD method at 500 °.

Next, as shown in FIG. 2B, holes are formed in the silicon oxide film 24 on the amorphous silicon film 23 by ordinary photolithography and etching steps. On the obtained silicon substrate 11, a WSi ₂ film 2
5 is formed by CVD at a thickness of 300.degree.
An i-film 26 is formed at 1000 °. Subsequently, as shown in FIG. 2C, the Ti film 26 and the WSi ₂ film 25 existing in a region where a wiring is to be formed in a later step are patterned by ordinary photolithography and etching steps. At this time, the Ti film 26 and the WSi ₂ film 25 remain on the side walls of the amorphous silicon film 23 in a sidewall shape.

Next, as shown in FIG. 2D, the obtained silicon substrate 11 was placed in a nitrogen atmosphere at 700 ° C.
By annealing for 5 minutes, silicon in the amorphous silicon layer 23 is sucked out into the Ti film 26, and Ti
The film 26 is converted into TiSix (x ≦ 2) 27 and a cavity 28 is formed. Subsequently, as shown in FIG. 2E, to make contact with the silicon substrate 11,
Contact holes 20 are formed in silicon oxide film 24 and silicon oxide film 12 by ordinary photolithography and etching processes. Thereafter, a TiN / Ti layer 29 is formed as a barrier metal at a thickness of 500 °.

Next, as shown in FIG.
A Cu film 21 is formed on the N / Ti layer 29 by the CVD method.
Then, chemical mechanical polishing is performed until the surface of the silicon oxide film 24 is exposed, the surface is flattened, and wiring is formed. In the case of obtaining a plurality of wiring layers, a plurality of
2 (g) through the steps of (a) to FIG. 2 (f).
Can be obtained. Finally, a PSG film 22 is formed on the entire surface of the obtained flat wiring structure, a bonding pad portion is opened in a usual photolithography and dry etching process, and bonding is performed (not shown). ).

Third Embodiment First, as shown in FIG. 3A, a silicon oxide film 12 is formed by a CVD method on a silicon substrate 11 on which a desired element (not shown) such as a transistor is formed at 15000.degree. Then, the surface of the silicon oxide film 12 is removed by 5000 ° by chemical mechanical polishing. Subsequently, a groove is formed by removing the silicon oxide film 12 at a depth of 4600 ° in a region where a wiring is to be formed in a later process by a usual photolithography and etching process. An amorphous silicon film 23 is formed on the entire surface of the obtained silicon substrate 11 by 5000 .ANG. By a CVD method, and is polished by chemical mechanical polishing until the surface of the silicon oxide film 12 is exposed to flatten the surface. A silicon oxide film 2 formed on the obtained silicon substrate 11 by CVD.
4 is formed at 500 °.

Subsequently, as shown in FIG. 3B, a hole is formed in the silicon oxide film 24 on the amorphous silicon film 23 by ordinary photolithography and etching steps. Next, the WSi ₂ layer 35 is formed by CVD to 30
0 °, a 2000 ° Ti film 36 is formed, and a mask which is the reverse of the mask used when forming the groove (or a negative resist using the same mask if the groove is a positive resist) is used. By photolithography and etching steps, patterning is performed so that the Ti layer 36 and the WSi ₂ layer 35 are left on the regions where the cavities will be formed in a later step.

Further, as shown in FIG. 3C, annealing is performed at 700 ° C. for 5 minutes in a nitrogen atmosphere to suck out the silicon in the amorphous silicon film 23 into the Ti layer 36. At this time, the Ti layer 36 is converted into a titanium silicide layer 37 of about 4800 ° and a cavity 38 is formed. Subsequently, a 6000 ° silicon oxide film 39 is formed on the obtained silicon substrate 11 by a plasma CVD method, and is polished by chemical mechanical polishing until the surface of the titanium silicide layer 37 is exposed. At this time, since the titanium silicide layer 37 has a concave shape above the hole of the silicon oxide film 24 formed on the amorphous silicon film 23, the silicon oxide film 39 remains. Therefore, the silicon oxide film 39 is further selectively etched by 500 °, and the silicon oxide film 39 on the titanium silicide layer 37 is completely removed.

Subsequently, as shown in FIG. 3D, through holes 30a are formed in the silicon oxide film 39, the silicon oxide film 24, and the silicon oxide film 12 by ordinary photolithography and etching steps. In a region including the through hole 30a, a groove 3 having a depth of 5000 mm is formed.
0b is formed.

Further, as shown in FIG. 3E, the titanium silicide layer 37 is selectively etched back by 4000 ° to form a groove for forming a wiring in a later step together with the previously formed groove 30b. . After that, as shown in FIG. 3F, the TiN / Ti film 31 is sequentially
に よ り is formed by a sputtering method so that
A film 32 is formed at 6000 ° by a CVD method. continue,
The Cu film 32 and the TiN / Ti film 31 are polished by chemical mechanical polishing until the surface of the silicon oxide film 39 is exposed, and the surfaces are flattened to form wiring.

When a plurality of wiring layers are to be obtained, a multilayer wiring structure as shown in FIG. 3 (g) is obtained by performing the steps of FIGS. 3 (a) to 3 (f) a plurality of times. Can be. Finally, the uppermost wiring layer is used as a bonding pad 34, a passivation film 33 is formed on the entire surface of the obtained flat wiring structure, and a window for a bonding pad portion is formed by ordinary photolithography and dry etching techniques. , Carrying out the homing (not shown).

Embodiment 4 First, as shown in FIG. 4A, a silicon oxide film 42 is formed on a silicon substrate 41 by 4000 ° CVD.
The Ti film 43 is 2000４３, the WSi ₂ film 44 is 300Å, and the amorphous silicon layer 45 by the CVD method is 460.
0 ° are sequentially formed. Subsequently, the amorphous silicon layer 45, the WSi ₂ film 44, and the Ti film 43 are patterned into a desired shape as a wiring by ordinary photolithography and etching processes.

Subsequently, as shown in FIG. 4B, a 2000 ° silicon oxide film 46 is formed on the obtained silicon substrate 41. Thereafter, as shown in FIG. 4C, annealing is performed at 700 ° C. for 5 minutes in a nitrogen atmosphere to cause a silicidation reaction. As a result, the silicon in the amorphous silicon layer 45 is sucked into the Ti film 43 via the WSi ₂ film 44, and the Ti film 43 is converted into the titanium silicide layer 47, and the Ti film 43 is deposited on the WSi ₂ film 44.
An 800 ° cavity 48 is formed.

[0045]

According to the semiconductor device of the present invention, a cavity whose inner wall is covered with an insulating film is provided between the wirings on the substrate having the wiring, and a part of the inner wall of the cavity is a metal silicide layer. Therefore, the capacitance between the wirings can be reduced. In addition, a completely hollow cavity in which no moisture or the like remains can be arranged between the wirings, high-speed operation with greatly reduced signal delay can be realized, and a highly reliable semiconductor device can be obtained. .

Further, when the metal silicide layer becomes a wiring or a part of the wiring, it is advantageous because the layer used for forming the cavity can be used as the wiring as it is. Furthermore, when the cavity has one or more holes that come into contact with the outside air, the heat dissipation effect of the obtained semiconductor device due to self-heating can be further enhanced, and the speed of the semiconductor device can be further increased. . Further, when the cavity is covered with a passivation film, the obtained semiconductor device or wiring can be protected, which is advantageous.

Further, when the substrate is an SOI substrate, the parasitic capacitance can be prevented and the speed can be further increased, which is advantageous as a measure against RC delay. Also,
According to the method of manufacturing a semiconductor device of the present invention, since a cavity is formed by a silicidation reaction between a silicon layer and a metal layer, a residue such as a corrosive material such as moisture is generated in the cavity during the manufacturing process. Can be prevented, and the material of the insulating film and the like formed on the cavity and the like, the forming method, and the like are not limited. Moreover, since there is no step of evaporating the material existing in the cavity forming region to form the cavity, the cavity is not destroyed by the influence of incineration or vapor pressure during the manufacturing process, and the wiring is simply and reliably provided between the wirings. A cavity can be formed.

The metal layer is made of Ti, Hf, V, Ta, M
o, a single layer or a plurality of layers made of one or more alloys selected from the group consisting of W and Fe, or a laminated layer of these metals and a silicide made of these metals, if it is a laminated layer The cavity can be easily formed by a simple method of optimizing the size, and the size can be controlled.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional process drawing of a main part for describing an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a schematic cross-sectional process drawing of a main part for describing another embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a schematic cross-sectional process diagram of a main part for describing still another embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 4 is a schematic cross-sectional process diagram of a main part for describing still another embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 5 is a schematic cross-sectional process drawing of a main part for describing a conventional method of manufacturing a semiconductor device.

FIG. 6 is a schematic cross-sectional process drawing of a main part for describing another conventional method for manufacturing a semiconductor device.

FIG. 7 is a schematic cross-sectional process drawing of a main part for describing another conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

11, 41 Silicon substrate (substrate) 12, 42 CVD silicon oxide film (first insulating film) 13, 23, 45 CVD amorphous silicon film (silicon layer) 14, 24, 46 CVD silicon oxide film (second insulating film) 15 , 25, 35, 44 Tungsten silicide film (metal silicide layer) 16, 26, 36, 43 Titanium film (metal layer) 17, 28, 38, 48 Cavity 18, 27, 37, 47 Titanium silicide film (metal silicide layer) Reference Signs List 20 contact hole 21 Cu film (wiring) 22 PSG film 29 barrier metal 30a through hole 30b region where wiring is to be formed 33 passivation film 34 bonding pad 39 CVD silicon oxide film (third insulating film)

Continued on the front page F term (reference) 4M104 AA01 AA02 AA03 AA04 AA05 AA09 BB04 BB14 BB19 BB24 BB25 BB26 BB27 BB28 DD78 DD84 EE20 FF13 FF22 5F033 GG01 GG02 GG03 GG04 HH11 HHH HHH HHH JJ33 MM02 MM05 MM08 MM10 MM12 MM13 NN06 NN07 PP06 QQ08 QQ09 QQ31 QQ37 QQ48 QQ70 QQ73 RR04 RR14 RR29 RR30 SS04 SS11 SS15 XX01 XX24

Claims (15)

[Claims] 1. A semiconductor device having a cavity whose inner wall is covered with an insulating film between wirings on a substrate having wirings, and a part of the inner wall of the cavity is formed of a metal silicide layer. 2. The semiconductor device according to claim 1, wherein the metal silicide layer is a wiring or a part of a wiring. 3. The semiconductor device according to claim 1, wherein the cavity has one or more holes in contact with the outside air. 4. The semiconductor device according to claim 1, wherein a part of the inner wall of the cavity or the entire inner wall other than a part formed of the metal silicide layer is covered with a passivation film. . 5. The method according to claim 1, wherein the metal silicide layer comprises Ti, Hf, V,
The semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is a single layer or a plurality of silicide layers of one or more metals or alloys selected from the group consisting of Ta, Mo, W, and Fe. . 6. The substrate according to claim 1, wherein the substrate is an SOI substrate.
The semiconductor device according to any one of the above. 7. A step of forming a first insulating layer and a silicon layer on a substrate, removing the silicon layer existing between regions where wiring is to be formed, and forming a second insulating film covering the remaining silicon layer. Forming; forming at least one opening in the second insulating film on the surface of the silicon layer; forming a metal layer so as to cover at least one opening of the second insulating film. A heat treatment is performed on the substrate to convert the metal layer into a metal silicide layer, so that a cavity is formed between the regions where the wirings are to be formed and in the portion where the silicon layer covered with the second insulating film was present. A method for manufacturing a semiconductor device including a step of forming. 8. The method according to claim 7, wherein two or more openings are formed in the second insulating film on the surface of the silicon layer, and the metal layer is formed so that at least one opening is not closed by the metal layer. the method of. 9. A step of forming a through hole in a first insulating film and / or a second insulating film existing in a region where a wiring is to be formed, the method including the through hole and a region where the wiring is to be formed. 8. The method according to claim 7, further comprising forming a barrier metal and a conductive film on the substrate, and patterning the barrier metal and the conductive film to form a wiring. 10. A step of forming a first insulating layer on a substrate, forming a groove in the first insulating film between regions where wiring is to be formed, filling the groove with a silicon layer, and forming at least the silicon layer. Covering with a second insulating film, forming one or more openings in the second insulating film on the silicon layer surface, forming a metal layer so as to cover at least one opening in the second insulating film. A heat treatment of the obtained substrate to convert the metal layer to a metal silicide layer, thereby forming a cavity in a groove of the first insulating film in which the silicon layer is embedded. . 11. The method according to claim 11, further comprising the step of forming a substantially flat surface on the substrate including the metal silicide layer with respect to the surface of the metal silicide layer.
(3) a step of forming an insulating film; a first insulating film and a second
Forming a through hole in the insulating film and the third insulating film, and forming a groove in the third insulating film and the metal silicide layer in a region where a wiring is to be formed; and forming a barrier metal on the substrate including the through hole and the groove. And forming a conductive film and patterning the barrier metal and the conductive film to form a wiring.
The described method. 12. A step of forming a first insulating layer, a silicon layer / metal layer or a metal layer / silicon layer on a substrate, patterning the silicon layer and the metal layer into a desired shape, and obtaining the obtained silicon layer and metal. Forming a second insulating film covering the layer; heat-treating the obtained substrate to convert the metal layer to a metal silicide layer, thereby forming a cavity in a portion where the silicon layer was present; Device manufacturing method. 13. The method according to claim 1, wherein the metal layer is Ti, Hf, V, Ta, M
13. A single layer or plural layers composed of one or more metals or alloys selected from the group consisting of o, W and Fe, or a laminated layer of these metals and silicide composed of these metals. The method described in. 14. The metal silicide layer is made of TiSi ₂ , H
_{fSi 2, VSi 2, TaSi 2} , MoSi 2, The method of claim 7 to 13 is WSi ₂ or FeSi _2. 15. The substrate according to claim 7, wherein the substrate is an SOI substrate.
15. The method according to 14.