JP4489823B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The invention disclosed in this specification relates to a semiconductor device using a single crystal semiconductor thin film formed over a substrate having an insulating surface. In particular, crystallized glass (also called ceramic glass) that is inexpensive and has high heat resistance is used as the substrate.

  Note that in this specification, a thin film transistor (hereinafter referred to as TFT), a semiconductor circuit, an electro-optical device, and an electronic device are all included in the category of “semiconductor device”. That is, all devices that can function using semiconductor characteristics are called semiconductor devices.

  Therefore, the semiconductor device described in the claims includes not only a single element such as a TFT but also a semiconductor circuit or an electro-optical device in which the semiconductor device is integrated, and an electronic device in which they are mounted as components.

  In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several tens to several hundreds nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are particularly urgently developed as switching elements for image display devices (for example, liquid crystal display devices: LCDs).

  In a liquid crystal display device, a pixel matrix circuit that individually controls pixels arranged in a matrix, a driver circuit that controls the pixel matrix circuit, and a logic circuit (arithmetic circuit, memory circuit, Attempts have been made to build a clock generator on the same substrate.

  In order to realize such a monolithic LCD, a TFT circuit having a higher operating speed is required, and for this purpose, a semiconductor layer having an extremely high carrier mobility is required.

  In such a trend, SOI technology has attracted attention. In particular, a technique called a smart cut method has attracted attention as a technique for forming a single crystal silicon thin film on a substrate such as synthetic quartz.

  The smart cut method (announced by SOIITEC in France in 1996) is one of the bonded SOI technologies and actively uses hydrogen embrittlement. Here, a simple procedure of the smart cut method will be described with reference to FIG.

First, a thermal oxide film 202 is formed by thermally oxidizing the bond wafer 201, and then hydrogen ions (H ⁺ ) are added by an ion implantation method. Through the hydrogen ion addition process, a micro cavity 203 terminated with hydrogen is formed in the bond wafer 201. In this specification, the minute cavity 203 is referred to as a hydrogen implantation layer. (Fig. 2 (A))

  Next, the bond wafer 201 that has been subjected to the above treatment and a base wafer 204 that will later become a thin film support substrate are bonded together at room temperature, and a heat treatment at about 500 ° C. is performed. By this heat treatment, hydrogen embrittlement occurs in the hydrogen implantation layer described above, and a fracture layer 205 is formed due to hydrogen embrittlement. (Fig. 2 (B))

  When the fracture layer 205 is formed by hydrogen embrittlement in this way, the bond wafer 201 is easily peeled leaving only the single crystal silicon thin film 206. (Fig. 2 (C))

  Therefore, a thermal oxide film 202 and a single crystal silicon thin film 206 are formed on the base wafer 204. The film thickness of the single crystal silicon thin film 206 at this time is determined by the film thickness of the thermal oxide film 202 and the implantation depth of hydrogen ion implantation in FIG.

  When the state of FIG. 2C is obtained in this way, shallow polishing (touch polishing) of the order of 10 nm is performed, and further, heat treatment is performed at a temperature of about 1000 to 1100 ° C. for about 2 hours, and the single crystal silicon having strong bonding strength A thin film 207 is obtained. (Fig. 2 (D))

  As described above, the smart cut method has an advantage that a single crystal silicon thin film can be obtained by a very simple means. Further, since the film thickness of the single crystal silicon layer is not affected by the polishing accuracy as compared with the past bonded SOI substrates, the film thickness is very uniform.

  Recently, an attempt has been made to form a single crystal silicon thin film on synthetic quartz using this smart cut method. (Takao Abe: 24th Amorphous Material Properties and Application Seminar Text, p.25-32, 1997)

  However, according to this report, when synthetic quartz and a silicon wafer (bond wafer) are bonded together, the difference in thermal expansion coefficient is large, so that destruction occurs when heated to about 300 ° C. Therefore, in the same report, after bonding the bond wafer at around 200 ° C., planar polishing (or etching) to 50 μm, and then performing heat treatment at 500 ° C. to complete the bonding.

  As described above, forming a single crystal silicon layer on a synthetic quartz by using the smart cut method has a problem that a bonding process becomes complicated due to a problem of a difference in thermal expansion coefficient.

  Further, considering the purpose of forming a TFT using a single crystal silicon layer to realize a monolithic LCD, it is not preferable to use an expensive quartz substrate because it increases the overall cost.

  The present invention has been made in view of the above problems, and an object thereof is to provide a technique for realizing a semiconductor device using a single crystal silicon thin film obtained by a smart cut method at a low manufacturing cost. .

The configuration of the invention disclosed in this specification is as follows.
A glass substrate having a strain point of 750 ° C. or higher;
An insulating silicon film formed on at least the front and back surfaces of the glass substrate;
A TFT having a single crystal silicon thin film formed on the insulating silicon film as a channel formation region;
Is included in the configuration.

In addition, the configuration of other inventions is as follows:
A glass substrate having a strain point of 750 ° C. or higher;
An insulating silicon film formed to cover the outer periphery of the glass substrate;
A TFT having a single crystal silicon thin film formed on the insulating silicon film as a channel formation region;
Is included in the configuration.

In addition, the configuration of other inventions is as follows:
Forming an amorphous semiconductor thin film on the entire surface of the glass substrate having a strain point of 750 ° C. or higher;
Oxidizing the amorphous semiconductor thin film by a first heat treatment to completely transform it into a thermal oxide film;
Forming a single crystal silicon thin film on the main surface side of the glass substrate by a smart cut method;
It is characterized by including.

In addition, the configuration of other inventions is as follows:
A step of forming an insulating silicon film on the entire surface of a glass substrate having a strain point of 750 ° C. or higher by a low pressure thermal CVD method;
Forming a single crystal silicon thin film on the main surface side of the glass substrate by a smart cut method;
It is characterized by including.

As important constituent requirements of the present invention,
(1) A glass substrate having heat resistance that can withstand a temperature of 750 ° C. or higher (a glass substrate having a strain point of 750 ° C. or higher) is used as the substrate.
(2) The outer peripheral surface (at least the front surface and the back surface, preferably the entire surface) of the high heat-resistant glass substrate is protected with an insulating silicon film.
(3) A single crystal silicon thin film is formed on the high heat resistant glass substrate wrapped with the insulating silicon film by using a smart cut method.
There are three points.

  A single crystal silicon thin film bonded onto a substrate by the smart cut method can be completely bonded by heat treatment at 800 to 1200 ° C. (preferably 900 to 1100 ° C.). Therefore, it is necessary to use a substrate having a strain point of at least 750 ° C. or more as the base substrate.

As such a substrate, a quartz substrate can be considered first, but the quartz substrate is expensive as described above, which increases the overall cost. In addition, the thermal expansion coefficient of quartz is 0.48 × 10 ⁻⁶ ° C.− ^1, which is as small as 1/10 of the thermal expansion coefficient of silicon (about 4.15 × 10 ⁻⁶ ° C. ⁻¹ ). That is, stress is easily generated between the silicon and silicon, and silicon peeling (film peeling) is likely to occur during the heat treatment.

  Therefore, in the present invention, crystallized glass with high heat resistance having a strain point of 750 ° C. or higher (typically 800 to 1200 ° C., preferably 900 to 1100 ° C.) is used as the substrate. Since crystallized glass can be made thinner than quartz, LCD manufacturing costs can be reduced. In addition, since it is a glass substrate, it can be enlarged and cost reduction can be achieved by multi-cavity.

  Furthermore, since the thermal expansion coefficient can be easily changed by making the component composition constituting the crystallized glass appropriate, a coefficient close to the thermal expansion coefficient of the single crystal silicon thin film can be selected. That is, since the difference in thermal expansion coefficient can be made extremely small, there is no film peeling as in the prior art, and there is no need to perform a complicated process as described in the conventional example.

  However, since crystallized glass has various component compositions, there is a concern that component substances may flow out during the manufacturing process of the semiconductor device. Therefore, it is important to protect the crystallized glass with an insulating film (an insulating silicon film is preferable in consideration of compatibility with a single crystal silicon thin film). For this purpose, it is necessary to protect at least the front surface (side on which the element is formed) and the back surface of the crystallized glass with an insulating film in the entire process.

  In addition, since the side surface of crystallized glass is a very small area when seen from the whole, even if it is exposed, it does not matter much. However, it goes without saying that it is most preferable to completely wrap the front surface, side surface, and back surface with an insulating film and to completely prevent the outflow of component substances.

  However, a portion where the film is not formed can be formed in the portion of the substrate support portion (such as a pusher pin) when forming the insulating film. However, it is not a problem because it is a very small area compared to the entire area.

  In consideration of the above points, the present inventors provide a single crystal silicon thin film formed by a smart cut method on a high heat resistant glass substrate whose outer peripheral surface (preferably the entire surface) is protected with an insulating silicon film. It came to the structure of this invention of this application.

  In the present invention, crystallized glass that is inexpensive and can be enlarged is used, and at least the front and back surfaces (preferably the entire outer periphery) of the glass are used in order to use the crystallized glass safely (without worrying about contamination). A configuration is adopted in which protection is performed with an insulating silicon film.

  On top of that, TFTs are fabricated using a single crystal silicon thin film formed using the smart cut method to realize a system-on-panel, and a high-performance electro-optic device, semiconductor circuit, and more The mounted electronic device can be provided at a low price.

  The embodiment of the present invention will be described in detail with the following examples.

  In this embodiment, steps up to forming a single crystal silicon thin film on crystallized glass using the smart cut method will be described with reference to FIG.

  First, a crystallized glass substrate 101 having a thickness of 0.5 to 1.1 mm (typically 0.7 mm) is prepared as a substrate. Crystallized glass is also called glass ceramics and is defined as a glass substrate obtained by uniformly growing fine crystals at the stage of glass production. Such crystallized glass is characterized by high heat resistance and low thermal expansion coefficient.

  The glass substrate used in the present invention is required to have high heat resistance having a strain point temperature of 750 ° C. or higher, preferably 900 to 1100. At present, the only glass material that realizes such heat resistance is crystallized glass. However, even if the glass substrate does not fall within the definition of crystallized glass (for example, an amorphous heat-resistant glass substrate), the above heat resistance Any substrate having the properties can be used in the present invention.

  For details on crystallized glass, refer to “Glass Handbook; Sakuo Sachio et al., Pp.197-217, Asakura Shoten, 1975”.

There are various types of crystallized glass, but basically, aluminosilicate glass and borosilicate glass (including B ₂ O ₃ ) centered on quartz (SiO ₂ ), alumina (Al ₂ O ₃ ) Etc. can be said to be practical. However, considering that it is used as a substrate for a semiconductor device, it is desirable to use an alkali-free glass. In this sense, MgO—Al ₂ O ₃ —SiO ₂ system, PbO—ZnO—B ₂ O ₃ system, Al ₂ O ₃ —B ₂ O ₃ —SiO ₂ system, ZnO—B ₂ O ₃ —SiO ₂ system, and the like are preferable.

MgO-Al ₂ O ₃ -SiO ₂ high-insulation crystallized glass contains TiO ₂ , SnO ₂ , ZrO _2, etc. as nucleating agents, mainly cordierite (2MgO · 2Al ₂ O ₃ · 5SiO ₂ ) It is crystallized glass as a crystal phase. This type of crystallized glass is characterized by high heat resistance and excellent electrical insulation even in a high frequency range. Table 1 shows composition examples and thermal expansion coefficients of cordierite-based crystallized glass.

The smaller the coefficient of thermal expansion, the smaller the influence of heat shrinkage (shrinkage due to heat), so that it is preferable as a semiconductor substrate for fine pattern processing. However, if the difference from the thermal expansion coefficient of the semiconductor thin film is large, film peeling or the like is likely to occur. Therefore, it is desirable to use a semiconductor thin film having a thermal expansion coefficient as close as possible. Considering such a fact, SiO ₂ is 45-57% Al ₂ O ₃ is 20 to 27% MgO is 11 to 18%, and TiO ₂ is preferably 9-12% of cordierite based crystallized glass I can say that.

Further, for example, when a transmissive LCD is manufactured, the crystallized glass is required to have translucency. In such a case, an alkali-free transparent crystallized glass may be used. For example, there is a crystallized glass as shown in Table 2 as a crystallized glass having a crystalline phase filled β-quartz solid solution and a thermal expansion coefficient of 1.1 to 3.0 × 10 ⁻⁶ ° C.

The first of the constituent requirements of the present invention is to use crystallized glass as described above as a substrate. Of course, if appropriate measures are taken (such as complete protection with an insulating film as in the present invention), alkali-based crystallized glass (Na ₂ O—Al ₂ O ₃ —SiO ₂ system, Li ₂ O—Al ₂ O ₃₎ -SiO ₂ system or the like) can also be used. In addition, even for crystallized glass with a very small coefficient of thermal expansion (or close to zero), a glass having a coefficient of thermal expansion of 2.0 to 3.0 x 10 ^-6 ° C is coated to reduce the difference in coefficient of thermal expansion from the semiconductor thin film. It can also be mitigated.

When the crystallized glass 101 having the above structure is prepared, an amorphous silicon film 102 is formed on the crystallized glass 101. Film formation is performed by a low pressure CVD method, and silane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used as a film formation gas. Note that the film thickness may be 50 to 250 nm (typically 100 to 150 nm). (Fig. 1 (A))

  When the film is formed by the low pressure thermal CVD method, the amorphous silicon film 102 can be formed on the front surface, the back surface, and the side surface so as to wrap the substrate 101. Strictly speaking, the amorphous silicon film 102 is not formed in a portion where a pusher pin for holding the substrate is in contact. However, it is insignificant when viewed from the overall area.

  Next, heat treatment is performed, and the thermal oxidation film 103 is formed by completely thermally oxidizing the amorphous silicon film 102. In this case, since the amorphous silicon film 102 is completely thermally oxidized and changed to the thermal oxide film 103, the thickness of the thermal oxide film 103 is 100 to 500 nm (typically 200 to 300 nm).

The heat treatment conditions may be any of known dry O ₂ oxidation, wet O ₂ oxidation, steam oxidation, pyrogenic oxidation, oxygen partial pressure oxidation, and hydrochloric acid (HCl) oxidation. Appropriate conditions may be set for the processing temperature and processing time in consideration of the process.

  In addition, it is preferable to perform the heat treatment at a temperature not lower than the strain point of the crystallized glass and not higher than the slow cooling point, and holding at that temperature, followed by slow cooling. By performing such treatment, it is possible to take measures against glass shrinkage simultaneously with the formation of the thermal oxide film. That is, by sufficiently shrinking the substrate in advance by the above-described processing, the amount of substrate shrinkage due to the subsequent heat treatment can be reduced. A technique related to this is described in JP-A-8-250744.

As described above, the thermal oxide film (silicon oxide film) 103 is formed. Since the amorphous silicon film 102 is formed so as to wrap around the substrate 101 as described above, the thermal oxide film 03 is also formed. It is formed so as to enclose the substrate 101. That is, since the crystallized glass substrate 101 is completely wrapped with an insulating silicon film, it is possible to prevent the outflow of the component substances.

  Here, the silicon oxide film represented by SixOy is used as the insulating silicon film, but other insulating silicon films such as a silicon nitride film represented by SixNy and a silicon oxynitride film represented by SiOxNy are also used. It is also possible to use.

  In this way, two of the important configurations of the present invention, the point of using crystallized glass and the point of wrapping the crystallized glass with the insulating silicon film, are achieved.

Next, a bond wafer 104 is prepared. The surface of the bond wafer 104 is covered with a thermal oxide film 105, and a hydrogen implanted layer 106 is formed by implanting hydrogen ions (H ⁺ ions) by an ion implantation method.

The thermal oxide film 105 has a thickness of 200 to 700 nm (typically 400 to 500 nm) and a hydrogen ion dose of 5 × 10 ¹⁵ to 1 × 10 ¹⁷ ions / cm ² (preferably 1 × 10 ¹⁶ to 5 × 10 ¹⁶ ions / cm ² ). If the dose is less than this, it is difficult to form a rupture layer, and if the dose is higher than this, there is a risk of rupture at the same time as ion implantation.

  Then, the bond wafer 104 is bonded to the main surface side (TFT forming side) of the crystallized glass 101 described above at room temperature, and then heat treatment is performed at a temperature of 400 to 600 ° C. (typically 500 ° C.). Apply. At this time, since there is not much difference between the thermal expansion coefficients of the crystallized glass 101 and the bond wafer 104, problems such as peeling (film peeling) due to thermal stress can be prevented.

  Thus, when the heat treatment process is completed, the bond wafer 104 is separated, and the thermal oxide film 105 and the single crystal silicon thin film 107 which are part of the bond wafer 104 are left on the crystallized glass 101. (Fig. 2 (D))

  This thermal oxide film 105 is integrated with the thermal oxide film 103 formed in the step of FIG. 2B and functions as a base film.

  Thereafter, a touch polishing process of about 10 nm is performed, and a heat treatment at 900 to 1200 ° C. (typically 950 to 1050 ° C.) is performed to increase the bonding strength of the single crystal silicon thin film 107. Thus, the single crystal silicon thin film 107 can be formed on the crystallized glass 101 whose outer periphery is completely protected by the thermal oxide film 103.

  The crystallized glass substrate shown in FIG. 1 (D) manufactured according to the present embodiment is much cheaper to manufacture than using a quartz substrate as in the prior art. In addition, since the outer periphery of the substrate is completely protected by the silicon oxide film, contamination due to the glass component does not occur in the subsequent process.

  In this embodiment, a manufacturing process of a semiconductor device having the structure of the present invention will be described with reference to FIGS. Specifically, a drive circuit and a logic circuit composed of a CMOS circuit in which NTFT (N-channel TFT) and PTFT (P-channel TFT) are complementarily combined are identical to a pixel matrix circuit composed of NTFT. An example in which the substrate is integrally formed on the substrate is shown.

  Note that a logic circuit is a signal processing circuit having a function different from that of a drive circuit typified by a shift register or the like, such as a D / A converter circuit, a memory circuit, a γ correction circuit, and an arithmetic processing circuit. This is a general term for circuits that perform signal processing as performed by an external IC.

  First, according to the manufacturing process described with reference to FIG. Then, the obtained single crystal silicon thin film is patterned to form active layers 303 to 305. Reference numeral 303 is an active layer of the PTFT of the CMOS circuit, 304 is an active layer of the NTFT of the CMOS circuit, and 305 is an active layer of the pixel matrix circuit, and the thickness of each is adjusted to 30 nm.

In this embodiment, crystallized glass having a composition of SiO ₂ : 65%, Al ₂ O ₃ : 25%, MgO: 10%, ZrO ₂ : 10% is used as the substrate 301. The substrate 301 is characterized in that it is transparent. Reference numeral 302 denotes a silicon oxide film obtained by thermally oxidizing an amorphous silicon film, and the film thickness is 400 nm.

  In this way, the state of FIG. Next, a gate insulating film 306 made of a silicon oxide film is formed to a thickness of 120 nm. Alternatively, a silicon oxynitride film or a silicon nitride film can be used. Further, these insulating silicon films may be freely combined to form a laminated structure.

  After the gate insulating film 306 is formed, a thermal oxidation process is performed in the temperature range of 800 to 1100 ° C. (preferably 1000 to 1150 ° C.). At this time, since the thermal oxidation reaction proceeds at the interface between the active layer and the gate insulating film, the active layer is thinned and the thickness of the gate insulating film is increased. This configuration is effective in suppressing the dielectric breakdown of the gate insulating film due to the edge thinning phenomenon (a phenomenon in which the thermal oxide film becomes extremely thin at the end portion of the active layer).

At this time, the atmosphere of the heat treatment may be an inert atmosphere or an oxidizing atmosphere, but a dry O ₂ atmosphere is preferable for obtaining the most stable interface characteristics. Further, the film quality of the gate insulating film itself is improved by performing the heat treatment at a high temperature.

  Next, gate electrodes 307 to 309 made of a crystalline silicon film exhibiting N-type conductivity are formed on the gate insulating film 306. The film thickness of the gate electrodes 307 to 309 may be selected in the range of 200 to 300 nm. (Fig. 3 (B))

After the gate electrodes 307 to 309 are formed, the gate insulating film 306 is etched by a dry etching method using the gate electrodes 307 to 309 as a mask. In this embodiment, CHF ₃ gas is used to etch the silicon oxide film.

  By this step, the gate insulating film remains only directly under the gate electrode (and the gate wiring). Of course, the portion remaining under the gate electrode is the portion that actually functions as the gate insulating film.

Next, a region to be a PTFT is hidden with a resist mask 310, and an impurity imparting N-type (phosphorus in this embodiment) is added by an ion implantation method or a plasma doping method. Since some of the low-concentration impurity regions 311 and 312 formed later become LDD (Lightly Doped Drain) regions, phosphorus is added at a concentration of 1 × 10 ¹⁷ to 5 × 10 ¹⁸ atoms / cm ^3. . (Figure 3 (C))

  Next, after removing the resist mask 310, a region to be an NTFT is hidden by the resist mask 313, and an impurity imparting P-type (boron in this embodiment) is added by an ion implantation method or a plasma doping method. At this time, the low concentration impurity region 314 is formed as in the case of phosphorus. (Fig. 3 (D))

  When the state of FIG. 3D is thus obtained, the resist mask 313 is removed, and then the sidewalls 315 to 317 are formed using an etch back method. In this embodiment, the sidewalls 315 to 317 are formed using a silicon nitride film.

  Note that in the case where a silicon oxide film is used as a material for the sidewall, the etch-back process may not be performed if the silicon oxide film 302 that protects the side surface of the crystallized glass 301 is thin. Since the glass side surface is sufficiently smaller than the entire area, the outflow of the glass component does not matter so much, but the thickness of the silicon oxide film 302 may be increased in advance so that it remains after the etch-back process.

  After the side walls 315 to 317 are formed in this way, the region to be the PTFT is again hidden by the resist mask 318 and phosphorus is added. At this time, the dose is set higher than in the previous addition step.

  By this phosphorus addition step, a source region 319, a drain region 320, a low concentration impurity region (LDD region) 321 and a channel formation region 322 of the NTFT constituting the CMOS circuit are defined. Further, a source region 323, a drain region 324, a low-concentration impurity region (LDD region) 325, and a channel formation region 326 of the NTFT constituting the pixel matrix circuit are defined. (Fig. 4 (A))

  Next, after the resist mask 315 is removed, the resist mask 327 hides a region to be NTFT, and boron is added at a higher dose than before. By this boron addition process, a source region 328, a drain region 329, a low concentration impurity region (LDD region) 330, and a channel formation region 331 of the PTFT constituting the CMOS circuit are defined. (Fig. 4 (B))

  As described above, after the process of adding impurities to the active layer is completed, heat treatment is performed by furnace annealing, laser annealing, or lamp annealing to activate the added impurities. Further, at this time, the damage to the active layer when the impurity is added is also recovered.

Note that the channel formation regions 322, 326, and 331 are intrinsic or substantially intrinsic regions to which no impurity element is added. Here, substantially intrinsic means that the impurity concentration imparting N-type or P-type is lower than the spin density of the channel formation region, or the impurity concentration is 1 × 10 ¹⁴ to 1 × 10 ¹⁷ atoms / cm It means that it is within the range of ³ .

  Next, a first interlayer insulating film 332 made of a laminated film of a 25 nm thick silicon nitride film and a 900 nm thick silicon oxide film is formed. Then, source electrodes 333 to 335 and drain electrodes 336 and 337 formed of a laminated film made of Ti / Al / Ti (film thicknesses are sequentially 100/500/100 nm) are formed.

  Next, a second interlayer insulating film having a laminated structure of a 50 nm thick silicon nitride film 338, a 20 nm thick silicon oxide film (not shown), and a 1 μm thick polyimide film 339 is formed. In addition to polyimide, other organic resin films such as acrylic and polyamide can be used. In this case, the 20 nm-thick silicon oxide film functions as an etching stopper when the polyimide film 339 is dry-etched.

  After the second interlayer insulating film is formed, the polyimide film 339 is etched to provide an opening in a region where an auxiliary capacitance is formed later. At this time, only the silicon nitride film 338 is left at the bottom of the opening, or the silicon nitride film 338 and the silicon oxide film (not shown) are left.

  Then, a titanium film having a thickness of 300 nm is formed, and a black mask 340 is formed by patterning. The black mask 340 is disposed on the pixel matrix circuit in a portion requiring light shielding, such as a TFT or a wiring portion.

  At this time, the drain electrode 337 of the pixel matrix circuit and the black mask 340 are close to each other with the silicon nitride film 338 (or a laminated film of a silicon nitride film and a silicon oxide film) interposed therebetween in the opening. In this embodiment, an auxiliary capacitor 341 is configured in which the black mask 340 is held at a fixed potential, the drain electrode 337 is a lower electrode, and the black mask 340 is an upper electrode. In this case, since the dielectric is very thin and the relative dielectric constant is high, a large capacity can be secured.

  After forming the black mask 340 and the auxiliary capacitor 341 in this way, a polyimide film having a thickness of 1 μm is formed to form a third interlayer insulating film 342. Then, a contact hole is formed, and a pixel electrode 343 made of a transparent conductive film (typically ITO) is formed to a thickness of 120 nm.

  Finally, heat treatment is performed at 350 ° C. for about 2 hours in a hydrogen atmosphere to hydrogenate the entire device. Thus, an active matrix substrate as shown in FIG. 4C is completed. Since the TFT formed in this embodiment uses a single crystal silicon thin film as an active layer, it has very high performance.

For example, the sub-threshold coefficient (S value) is 60 to 80 mV / decade for both NTFT and PTFT, the field effect mobility (mobility) of NTFT is 300 to 700 cm ² / Vs, and the mobility of PTFT is 200 to 400 cm ² / Vs. Realize.

  Moreover, since the single crystal silicon thin film is formed by the smart cut method, the uniformity of the thickness of the active layer on the substrate can be improved. In particular, the present invention is very effective in suppressing variations in characteristics of pixel TFTs (TFTs constituting a pixel matrix circuit) that require high uniformity.

  When the active matrix substrate is completed, an active matrix liquid crystal display device (transmission type) can be completed by sandwiching a liquid crystal layer between the counter substrate and the opposite substrate by a known cell assembly process.

  Note that the structure of the active matrix substrate is not limited to this embodiment, and can be any structure. That is, the practitioner can freely design the TFT structure, circuit arrangement, and the like as long as the configuration requirements of the present invention can be satisfied.

  For example, although a transparent conductive film is used as the pixel electrode in this embodiment, a reflective active matrix liquid crystal display device can be easily realized by changing this to a highly reflective material such as an aluminum alloy film. In this case, the crystallized glass serving as the base of the active matrix substrate does not need to be transparent, and a light-shielding substrate may be used.

  In this embodiment, crystallized glass is used as the active matrix substrate, so that compatibility is good when a glass substrate is used as the counter substrate. If quartz is used as the active matrix substrate, warpage may occur between the active matrix substrate and the counter substrate due to the difference in thermal expansion coefficient between quartz and glass.

  In this embodiment, an example in which an insulating silicon film for protecting crystallized glass in the configuration of Embodiments 1 and 2 is formed by a low pressure thermal CVD method will be described.

First, crystallized glass containing SiO ₂ : 52.5, Al ₂ O ₃ : 26.5, MgO: 11.9, TiO ₂ : 11.4 as a composition component is prepared as a substrate. This is an alkali-free cordierite crystallized glass using TiO ₂ as a nucleating agent.

Next, a silicon oxynitride film is formed on the front surface, back surface, and side surfaces of the crystallized glass. In this embodiment, a silicon oxynitride film is formed by a low pressure thermal CVD method using silane (SiH ₄ ) and nitrous oxide (N ₂ O) as a film forming gas.

In this case, the film formation temperature is 800 to 850 ° C. (850 ° C. in this embodiment), and the flow rates of the respective film formation gases are SiH ₄ : 10 to 30 sccm and N ₂ O: 300 to 900 sccm. The reaction pressure may be 0.5 to 1.0 torr.

Further, when silane and nitrogen dioxide (N ₂ O) or nitrogen monoxide (NO) are used as a film forming gas, a silicon oxynitride film can be formed at a temperature of 600 to 650 ° C. In this case, the reaction pressure may be 0.1 to 1.0 torr, and the gas flow rates may be SiH ₄ : 10 to 30 sccm, NO ₂ or NO: 300 to 900 sccm.

  In this embodiment, since the silicon oxynitride film is formed by the low pressure thermal CVD method, the entire surface of the crystallized glass is covered with an insulating film. In addition, by using different deposition gases, a silicon nitride film can be formed as a protective film for crystallized glass.

In this case, 40-50 sccm of dichlorosilane (SiH ₂ Cl ₂ ) and 200-250 sccm of ammonia (NH ₃ ) are used as the deposition gas, the deposition temperature is 750-800 ° C, and the reaction pressure is 0.1-0.5 torr. What should I do?

  A silicon nitride film is an optimal insulating film for preventing the outflow of glass components, but it is not suitable as a base film for TFT because of its strong stress. However, in the present invention, since the silicon nitride film is formed on at least the front surface and the back surface of the crystallized glass, the stress of the silicon nitride film is offset between the front and back surfaces of the substrate, and the warp of the substrate does not occur.

  In this embodiment, an example in which an insulating silicon film formed by a low pressure thermal CVD method is used as the gate insulating film in Embodiments 1 and 2 will be described. FIG. 5 is used for the description. The state shown in FIG. 5 is a state immediately after etching the gate insulating film after forming the gate electrode.

  In FIG. 5, reference numeral 501 denotes crystallized glass, and reference numeral 502 denotes a silicon oxynitride film serving as a protective film (underlying film) for preventing outflow of component substances from the crystallized glass. Active layers 503 to 505 are formed on the surface side of the crystallized glass 501, and after forming a gate insulating film, gate electrodes 506 to 508 are formed.

  By performing dry etching using the gate electrodes 506 to 508 as a mask, gate insulating films 509 to 511 remain immediately below the gate electrode.

  The most important configuration of this embodiment is that an insulating silicon film (silicon oxynitride film in this embodiment) formed by a low pressure thermal CVD method is used as the gate insulating film. That is, the gate insulating film is also characterized in that it is formed on all surfaces of the crystallized glass 501 on the front surface, back surface, and side surfaces.

  Therefore, at the time when the etching process of the gate insulating film (silicon oxynitride film) is completed (the state shown in FIG. 5), the surface side of the substrate is completely removed except for the portion masked by the gate electrode. The silicon oxynitride film 512 remains as it is. Note that although the silicon oxynitride film formed on the side surface is removed depending on conditions, there is no problem even if the side surface is removed.

  In the structure of this embodiment, the silicon oxynitride film 502 formed directly on the crystallized glass 501 even when the back surface and the side surface are exposed to an etchant or etching gas capable of etching the silicon oxynitride film in a later step. Can leave. That is, it is possible to thoroughly prevent the component substances from flowing out of the glass substrate.

  In Example 2, a crystalline silicon film exhibiting N-type conductivity is used as the gate electrode, but any material having conductivity can be used. In particular, when a liquid crystal display device for direct viewing is manufactured, it is preferable to use a material having a low wiring resistance because the area of the pixel matrix circuit becomes large.

  In such a case, it is desirable to use aluminum or a material mainly composed of aluminum for the gate electrode. In this embodiment, an aluminum film containing 2 wt% scandium is used as the gate electrode.

  In the case where a material mainly composed of aluminum is used as the gate electrode, it is preferable to use the technique described in Japanese Patent Application Laid-Open No. 7-13518 by the present inventors. In this publication, an anodic oxide film obtained by anodizing a gate electrode is used instead of the side wall used in the first embodiment.

  By using aluminum or a material mainly composed of aluminum as the gate electrode as in this embodiment, it is possible to form a gate wiring with a low wiring resistance, and an active matrix substrate with a high response speed can be manufactured.

  In addition, a present Example can be combined with the structure of Examples 1-4.

  In Example 2, it is effective to add an impurity element for controlling the threshold voltage (Vth) of the TFT to the active layer. Since this impurity element only needs to be added at least to the channel formation region, it may be added at any time before the gate electrode is formed.

  In the case of adding other than during film formation, means such as addition by ion implantation method or plasma doping method, addition by diffusion from the gas phase, addition by diffusion from the solid phase can be used. These means are effective because they can be selectively added, for example, different impurities are added between NTFT and PTFT.

  As the impurity element to be added, a group 13 element (boron, gallium, or indium) is used if Vth is moved to the plus side, and 15 elements (phosphorus, arsenic, or antimony) are used if it is moved to the minus side. Use.

  In addition, a present Example can be combined with the structure of Examples 1-5.

  In this embodiment, an example in which a DLC (Diamond Like Corbon) film is used as a heat sink on the third interlayer insulating film 342 (see FIG. 4C) in the active matrix substrate described in the first embodiment. explain.

  The structure shown in FIG. 6 is basically the same as the structure shown in FIG. 4C except that a DLC film 601 is provided over the third interlayer insulating film 342.

DLC is carbon having a physical property such as diamond or a material having high hardness mainly composed of carbon. Also called i-carbon, it is composed mainly of sp ³ bonds.

  Diamond is a material having the highest thermal conductivity at room temperature (about 10 to 20 W / cm · k at room temperature), and a DLC film having the same physical properties also shows a high thermal conductivity. In this embodiment, the high heat conductivity is used to function as a heat sink.

  In addition, since the DLC film is excellent in adhesion with the organic resin film, it is a very effective material when an organic resin film is used as an interlayer insulating film and a heat sink is provided thereon.

  As a DLC film forming means, a gas phase film forming method such as a plasma CVD method, an ECR plasma CVD method, a sputtering method, an ion beam sputtering method, or an ionized vapor deposition method can be used.

  Further, hydrocarbon is used as a source gas for forming the DLC film. Examples of the hydrocarbon include saturated hydrocarbons such as methane, ethane, and propane, and unsaturated hydrocarbons such as ethylene and acetylene. Alternatively, a halogenated hydrocarbon in which one or a plurality of hydrogen atoms in a hydrocarbon molecule is substituted with a halogen element may be used.

  In addition to hydrocarbons, it is effective to add hydrogen. When hydrogen is added, hydrogen radicals in the plasma increase, and the effect of improving the film quality by extracting excess hydrogen in the film can be expected. At this time, the ratio of the hydrogen gas flow rate to the total gas flow rate is 30 to 90%, preferably 50 to 70%. If this ratio is too large, the film formation rate decreases, and if it is too small, the effect of extracting excess hydrogen is lost.

  Furthermore, helium can be added as a carrier gas for diluting the source gas, and argon can be added as a sputtering gas in the case of sputtering. It is also effective to add a group 13-15 element as described in JP-A-6-208721.

The reaction pressure is 5 to 1000 mTorr, preferably 10 to 100 mTorr. High frequency power is normally 13.56MHz. At this time, RF power to be applied 0.01~1W / cm ^2, preferably between 0.05 to 0.5 / cm ^2. In addition, it is also effective to use an electron spin resonance by adding an excitation effect of 2.45 GHz microwaves to form a 875 gauss magnetic field in the excitation space to promote decomposition of the source gas.

  In this embodiment, 50 sccm of methane gas and 50 sccm of hydrogen gas are introduced into the reaction space of the plasma CVD apparatus, the deposition pressure is 10 mTorr, the RF power is 100 W, and the temperature of the reaction space is room temperature. Further, a DC bias of 200 V is applied as a substrate bias, and an electric field is formed so that particles (ions) in the plasma are incident on the surface to be formed, thereby improving the film quality and improving the hardness.

  The DLC film has very high wear resistance even when the film thickness is about 10 nm. Therefore, in the structure shown in FIG. 7, the effect of protecting the third interlayer insulating film 342 from mechanical shock can be obtained. This is very effective for a friction process such as a rubbing process.

  The friction coefficient depends on the DLC film thickness, and becomes smaller as the DLC film thickness increases. Accordingly, it is sufficient that the thickness of the DLC film is 10 nm or more, but if it is too thick, the electric field applied to the liquid crystal is weakened, so about 10 to 50 nm is preferable.

  For further details of the DLC film forming method, film forming apparatus, and the like, it is preferable to refer to Japanese Patent Publication Nos. 3-72711, 4-27690, and 4-27191 by the present inventors. .

  In the structure of FIG. 7 obtained with the above configuration, the heat generated in the TFT is released with high efficiency, so that malfunction due to heat storage can be prevented. In particular, it is better to use such a heat-resistant structure for a liquid crystal display device used in a projection type electronic device.

  An example in which a liquid crystal display device is configured using the active matrix substrate having the configuration shown in Examples 1 to 7 is shown in FIG. FIG. 7 shows a portion corresponding to the main body of the liquid crystal display device, which is also called a liquid crystal module.

  In FIG. 7, reference numeral 701 denotes crystallized glass, and reference numeral 702 denotes an insulating silicon film formed so as to enclose the entire surface of the crystallized glass. In the case where a plurality of active matrix substrates are cut out from a large-sized substrate by multi-chamfering, the insulating silicon film does not exist on the side surface that becomes the cut surface, but the insulating silicon film remains on the other side surface. It is a feature of the invention. Of course, since it has been completed as an active matrix substrate, there is no fear that component materials will flow out even if it is not protected by an insulating silicon film.

  A plurality of TFTs are formed with a single crystal silicon thin film on the substrate having such a configuration. These TFTs constitute a pixel matrix circuit 703, a gate side driving circuit 704, a source side driving circuit 705, and a logic circuit 706 on the substrate. Then, a counter substrate 707 is attached to such an active matrix substrate. A liquid crystal layer (not shown) is sandwiched between the active matrix substrate and the counter substrate 707.

  In the configuration shown in FIG. 7, it is desirable that the side surfaces of the active matrix substrate and the side surface of the counter substrate are all aligned except for one side. By doing so, the number of multiple chamfers from the large substrate can be increased efficiently. On the one side, a part of the counter substrate is removed to expose a part of the active matrix substrate, and an FPC (flexible printed circuit) 708 is attached thereto. Here, an IC chip (semiconductor circuit composed of MOSFETs formed on single crystal silicon) may be mounted as necessary.

  Since the TFT constituting the circuit of this embodiment has an extremely high operation speed, a signal processing circuit driven at a high frequency of several hundred MHz to several GHz is integrally formed on the same substrate as the pixel matrix circuit. Is possible. That is, the liquid crystal module shown in FIG. 7 embodies a system-on-panel.

  Although the present embodiment describes the case where the present invention is applied to a liquid crystal display device, an active matrix EL (electroluminescence) display device or the like can also be configured. Further, an image sensor or the like provided with a photoelectric conversion layer can be formed over the same substrate.

  Note that a device having a function of converting an optical signal into an electric signal or converting an electric signal into an optical signal, such as the above-described liquid crystal display device, EL display device, and image sensor, is defined as an electro-optical device. The present invention can be applied to all electro-optical devices that can be formed using a semiconductor thin film on a substrate having an insulating surface.

  The present invention can constitute not only an electro-optical device as shown in the eighth embodiment but also a thin film integrated circuit (or semiconductor circuit) in which functional circuits are integrated. For example, an arithmetic circuit such as a microprocessor or a high-frequency circuit (MMIC: microwave module module IC) for portable devices can be configured.

  Furthermore, it is possible to construct a three-dimensional semiconductor circuit by taking advantage of the TFT using a thin film, and to construct a VLSI circuit integrated at an ultra-high density. As described above, it is possible to constitute a semiconductor circuit having a very high functionality by using the TFT of the present invention. Note that in this specification, a semiconductor circuit is defined as an electric circuit that controls and converts an electric signal using semiconductor characteristics.

  In this embodiment, an example of an electronic device (applied product) on which the electro-optical device or the semiconductor circuit shown in Embodiment 8 or Embodiment 9 is mounted is shown in FIG. An electronic device is defined as a product on which a semiconductor circuit and / or an electro-optical device is mounted.

  Electronic devices to which the present invention can be applied include video cameras, electronic still cameras, projectors, head mounted displays, car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones, PHS, etc.) and the like.

  FIG. 8A illustrates a mobile phone, which includes a main body 2001, an audio output unit 2002, an audio input unit 2003, a display device 2004, operation switches 2005, and an antenna 2006. The present invention can be applied to the audio output unit 2002, the audio output unit 2003, the display device 2004, and the like.

  FIG. 8B shows a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102, the audio input unit 2103, the image receiving unit 2106, and the like.

  FIG. 8C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the camera unit 2202, the image receiving unit 2203, the display device 2205, and the like.

  FIG. 8D illustrates a head mounted display, which includes a main body 2301, a display device 2302, and a band portion 2303. The present invention can be applied to the display device 2302.

  FIG. 8E illustrates a rear projector, which includes a main body 2401, a light source 2402, a display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be applied to the display device 2403.

  FIG. 8F illustrates a front projector, which includes a main body 2501, a light source 2502, a display device 2503, an optical system 2504, and a screen 2505. The present invention can be applied to the display device 2503.

  As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Further, the present invention can be applied to any product that requires an electro-optical device or a semiconductor circuit.

10A and 10B illustrate a manufacturing process of a single crystal silicon thin film. The figure which shows the process of the smart cut method. 10A and 10B illustrate a manufacturing process of a thin film transistor. 10A and 10B illustrate a manufacturing process of a thin film transistor. FIG. 9 illustrates a structure of a thin film transistor. FIG. 9 illustrates a structure of a thin film transistor. The figure which shows the structure of a liquid crystal module. FIG. 11 illustrates a structure of an electronic device.

Claims (6)

An amorphous silicon film is formed on a glass substrate having a strain point of 750 ° C. or higher,
Forming an insulating silicon film by thermally oxidizing the amorphous silicon film;
Wherein the bond wafer made of monocrystalline silicon having a glass substrate and a hydrogen implanted layer, so as to sandwich the oxide film formed on one and the bond wafer surface and the insulating silicon film formed on the back surface of the glass substrate , Pasting at room temperature,
After the bonding, a first heat treatment is performed,
After the first heat treatment, a part of the bond wafer is peeled off at a portion of the hydrogen implantation layer of the bond wafer to form a single crystal silicon thin film on the glass substrate,
A second heat treatment is performed on the glass substrate and the single crystal silicon thin film,
After the second heat treatment, an active layer is formed by patterning the single crystal silicon thin film,
Forming a gate insulating film on the active layer;
A method of manufacturing a semiconductor device, wherein a gate electrode is formed on the gate insulating film. An amorphous silicon film is formed on a glass substrate having a strain point of 750 ° C. or higher,
Forming an insulating silicon film by thermally oxidizing the amorphous silicon film;
Wherein the bond wafer made of monocrystalline silicon having a glass substrate and a hydrogen implanted layer, so as to sandwich the oxide film formed on the insulative silicon film bond wafer formed on the outer peripheral surface of the glass substrate, at room temperature Pasting,
After the bonding, a first heat treatment is performed,
After the first heat treatment, a part of the bond wafer is peeled off at a portion of the hydrogen implantation layer of the bond wafer to form a single crystal silicon thin film on the glass substrate,
A second heat treatment is performed on the glass substrate and the single crystal silicon thin film,
After the second heat treatment, an active layer is formed by patterning the single crystal silicon thin film,
Forming a gate insulating film on the active layer;
A method of manufacturing a semiconductor device, wherein a gate electrode is formed on the gate insulating film. An amorphous silicon film is formed on a glass substrate having a strain point of 750 ° C. or higher,
Forming an insulating silicon film by thermally oxidizing the amorphous silicon film;
Wherein the bond wafer made of monocrystalline silicon having a glass substrate and a hydrogen implanted layer, so as to sandwich the oxide film formed on the insulative silicon film bond wafer formed on the entire outer peripheral surface of the glass substrate, at room temperature Pasted together,
After the bonding, a first heat treatment is performed,
After the first heat treatment, a part of the bond wafer is peeled off at a portion of the hydrogen implantation layer of the bond wafer to form a single crystal silicon thin film on the glass substrate,
A second heat treatment is performed on the glass substrate and the single crystal silicon thin film,
After the second heat treatment, an active layer is formed by patterning the single crystal silicon thin film,
Forming a gate insulating film on the active layer;
A method of manufacturing a semiconductor device, wherein a gate electrode is formed on the gate insulating film.   4. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide film has a thickness of 200 to 700 nm. In any one of claims 1 to 4, wherein the hydrogen implanted layer is characterized by being formed by implanting hydrogen ions a dose of ^{5 × 10 15 ~1 × 10 17} ions / cm 2 semiconductor Device fabrication method. In any one of claims 1 to 5, wherein after forming the gate insulating film, by thermal oxidation process, a method for manufacturing a semiconductor device characterized by increasing the thickness of the gate insulating film.

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