JP4480678B2 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
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- JP4480678B2 JP4480678B2 JP2006004479A JP2006004479A JP4480678B2 JP 4480678 B2 JP4480678 B2 JP 4480678B2 JP 2006004479 A JP2006004479 A JP 2006004479A JP 2006004479 A JP2006004479 A JP 2006004479A JP 4480678 B2 JP4480678 B2 JP 4480678B2
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- integrated circuit
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Description
2.3 CPU
4 端子接続制御部
5 割り込み検出部
6 接続決定部
7 機能選択レジスタ(データ格納部)
CPORT0〜CPORT23 I/O端子
IPORT0〜IPORT18 内部汎用入力ポート
OPORT0〜OPORT12 内部汎用出力ポート
GPI0〜GPI7 内部汎用入力ポート
GPO0〜GPO7 内部汎用出力ポート
Claims (5)
- 複数のCPU、および複数の外部I/O端子を有した半導体集積回路装置であって、
前記複数のCPUは、
個々の前記CPUが管理する複数の内部汎用入出力ポートをそれぞれ備え、
予め設定された少なくとも2つの前記内部汎用入出力ポートから、任意の前記内部汎用入出力ポートを選択し、選択した前記内部汎用入出力ポートを任意の前記外部I/O端子に割り付けるように接続する端子接続制御部を備えたことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記端子接続制御部は、
機能設定データに基づいて、予め設定された少なくとも2つの前記内部汎用入出力ポートから、任意の前記内部汎用入出力ポートを選択し、前記外部I/O端子の接続状態を切り替える接続決定部と、
前記接続決定部の接続状態を切り換える機能設定データを格納するデータ格納部とよりなることを特徴とする半導体集積回路装置。 - 請求項2記載の半導体集積回路装置において、
前記複数のCPUは、
前記データ格納部に共通にアクセス可能であり、前記CPUによって前記データ格納部の機能設定データを設定することを特徴とする半導体集積回路装置。 - 請求項1〜3のいずれか1項に記載の半導体集積回路装置において、
前記複数のCPUが管理する内部汎用入出力ポートは、
割り込み信号を受け付ける割り込み機能、または内部汎用入力機能の少なくともいずれか一方の機能を備えることを特徴とする半導体集積回路装置。 - 請求項1〜4のいずれか1項に記載の半導体集積回路装置において、
前記複数のCPUは、1つの半導体チップ上に形成されていることを特徴とする半導体集積回路装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2006004479A JP4480678B2 (ja) | 2006-01-12 | 2006-01-12 | 半導体集積回路装置 |
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JP2006004479A JP4480678B2 (ja) | 2006-01-12 | 2006-01-12 | 半導体集積回路装置 |
Publications (2)
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JP2007188200A JP2007188200A (ja) | 2007-07-26 |
JP4480678B2 true JP4480678B2 (ja) | 2010-06-16 |
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JP2006004479A Active JP4480678B2 (ja) | 2006-01-12 | 2006-01-12 | 半導体集積回路装置 |
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JP (1) | JP4480678B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP7139815B2 (ja) * | 2018-09-19 | 2022-09-21 | 富士フイルムビジネスイノベーション株式会社 | 情報処理装置 |
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JP2007188200A (ja) | 2007-07-26 |
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