JP4472106B2 - How to access main ATX output without monitoring all outputs - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power monitor circuit, and more particularly to a circuit for monitoring the power of a personal computer.
[0002]
[Prior art and problems to be solved by the invention]
Personal computers include circuitry that monitors and controls the power supplied to different parts of the computer. Some parts, such as memory, require a different voltage than other parts, such as a microprocessor. In order to conserve power and increase the life of the integrated circuit, it is economical to reduce the power available to the component when the computer is inactive. Most computers have a power saving feature that reduces power after a predetermined time. The operator can control the time. During the power down time, minimal power is supplied to the computer. In theory, all that is needed is to provide enough power to detect when the user wants to return to full power. Despite the speed of the integrated circuit, a finite amount of time remains for the power supply to reach an operational level. If the computer begins to operate before the power source reaches their operating level, the calculations and operations performed by the computer may be incorrect. Such premature operation can cause operational errors that can cause the computer to fail and shut off. At this time, the user will have to restart the computer or perhaps even repair it.
[0003]
The power management function contributes to overall efficiency, saves energy, and reduces the operating cost of the computer. As personal computers become more sophisticated, power-up and power-down monitoring circuits have become more sophisticated as well. Computers use so many voltages that they need more sophisticated circuits. The main voltages used in computers are 12 volts, 5 volts and 3.3 volts. These are supplied from the AC / DC converter to other devices and chips in the computer. The motherboard on the computer itself requires an additional voltage derived from the main voltage for operating the memory chip, graphic chip and clock chip. Nevertheless, all of these main voltage derived voltages are derived from the three main voltages 12 volts, 5 volts and 3.3 volts.
[0004]
It is important that the various devices be powered up and down in a manner defined by the computer manufacturer. Unless power-up and power-down operations are controlled and there is not enough power, valuable data may be lost or the system may conflict with itself and crash.
For proper operation, the three main voltages must be 90% or about 90% of their expected operating level. Microprocessor manufacturers such as Intel specify that the microprocessor and motherboard are fully operational after a predetermined time window. The time window is currently set at about 100 ms. In addition, to assist PC manufacturers, Intel states that 3.3 and 5.0 volt sources must reach 90% of their values in 40 ms. The problem faced by computer manufacturers is how to monitor and determine the main voltage when a voltage derived from the main voltage can be obtained.
[0005]
Some manufacturers have suggested using a total of three power monitor chips, one for each main voltage. This is an easy method, but increases the number of power supply monitors to match the three main voltages. Yet another proposal is to use a single chip to monitor the power supply and to include three main voltage monitoring circuits (one circuit for each of the three main voltages) on that single chip. It was done.
[0006]
[Means for Solving the Problems]
The present invention improves upon the known solution by providing a single power monitor integrated circuit with a single input main voltage pin. In accordance with the present invention, this desired result is obtained by using functions specific to the power supply. Ensure that the power supply meets strict specifications. According to these specifications, 5 volt and 3.3 volt supplies are connected to a 12 volt supply. This power supply causes the 3.3 volt source and the 5.0 volt source to reach 90% of their value within 40 ms after the 12 volt source reaches 90% of their value. A suitable delay circuit 25 delays switching the dual supply of 3.3 and 5 volts from the standby voltage supply to the active voltage supply until after the main 3.3 and 5 volts are operating.
[0007]
According to the present invention, input means for receiving a plurality of power outputs from a power source, means for controlling the input power output to generate a controlled voltage power output, means for comparing a signal representing the main power voltage with a reference signal, An integrated circuit for monitoring and controlling power from a power source that generates a plurality of different output voltages, each power output voltage being derived from a main power voltage, comprising:
Means for detecting when the main power output voltage reaches or exceeds a threshold reference level;
Means for delaying connection of the power output voltage to the computer by a selected delay time after the power supply reaches a reference threshold level;
There is provided an integrated circuit characterized by further comprising:
[0008]
The integrated circuit provided by the present invention monitors and controls power from a computer ATX power supply. A typical ATX power supply generates a plurality of different output voltages, each output voltage coming from a main power voltage, typically a 12 volt supply. The integrated circuit includes a number of input pins. These input pins serve as input means for receiving multiple power outputs from the ATX power supply. The integrated circuit also includes a conventional linear power controller circuit that controls each of the power outputs. The comparator circuit compares a signal indicating the main power voltage with a reference signal. The voltage divider supplies one input to the comparator and the other input is supplied by a threshold reference source. When the divided signal exceeds the threshold value, the comparator outputs a signal indicating the result. This signal means that the main power supply has reached at least 90% of the target value. The output of the comparator then triggers the timing circuit. The timing circuit delays the start of the computer by a set time corresponding to the timing specification of the ATX power supply. These specifications require that the voltage source and power source derived from the main source be at their respective voltage levels within a very carefully controlled time (typically 40 microseconds). The The timing circuit is set so that the delay time is equal to or exceeds the ATX specification. In a typical application, the delay is set to about 100 microseconds. When the delay time ends, the present invention generates a power-up signal.
[0009]
According to the present invention, there is also provided a computer system having monitored power, including a power source for generating a plurality of different DC voltages, a motherboard including a memory unit, and a central processing unit, A power monitoring integrated circuit that controls the supply of power from the power source to the motherboard is disposed between the power source and the motherboard, and the power monitoring circuit includes: Means for receiving a plurality of power outputs from the power source; means for controlling the input power output to generate a controlled voltage power output; and means for comparing a signal indicative of the main power output voltage with a reference signal A computer system comprising:
Means for detecting when the main power output voltage reaches or exceeds a threshold reference level;
Means for delaying connection of the power output voltage to the computer by a selected delay time after the power supply reaches a reference threshold level;
A computer system characterized by further comprising: is provided.
[0010]
Furthermore, according to the present invention, there is a method for monitoring and controlling power from a power source that generates a plurality of different output voltages, each power output voltage being derived from a main power voltage,
Receiving a plurality of power outputs from a power source;
Controlling the input power output to generate a controlled voltage power output;
Comparing a signal representing the main power voltage with a reference signal;
Detecting when the main power output voltage reaches or exceeds a threshold reference level;
Delaying the connection of the power output voltage to the computer after the power supply reaches a reference threshold level by a selected delay time;
Is provided.
[0011]
At that time, the computer can enter a desired operating state including its active state or its sleep state.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described with reference to the accompanying drawings.
[0013]
FIG. 1 is a schematic diagram of a high level circuit showing a portion of a personal computer. The ATX AC / DC power supply 10 includes a transformer and a DC-DC converter chip. The power supply 10 has its input connected to an AC source. The nine outputs of power supply 10 include a 5 volt standby output and three main voltage outputs 12 volt, 5 volt, and 3.3 volt. The outputs from the ATX power supply are tightly coupled to each other. In fact, they are all derived from the same AC source. If the main 12 volt power supply exceeds 90% of its nominal setting, the 5 volt and 3.3 volt sources will equal or exceed 90% of their nominal setting at the end of the 40 ms window. . In fact, a 12 volt main power voltage can be used as another main voltage proxy. Since the 5 volt source and the 3.3 volt source are related to the 12 volt source, there is no need to actually monitor 5 and 3.3 volts. Instead, the 12 volt supply is monitored for overall compliance. Once the 12 volt supply is in compliance, the 5 volt supply and the 3.3 volt supply are in compliance by the end of the 40 ms window.
[0014]
The comparator circuit 22 is introduced into the power monitor integrated circuit 20. The comparator circuit 22 is a resistor divider network including resistors R1 and R2 (see FIG. 2). A resistor of sufficient value is selected to divide the voltage to the comparator 24 into the 5 volt standby power supply range. The voltage V _REF input to the comparator 24 is derived from a 5 volt standby power supply. The maximum reference level is set to 90% of the nominal value, ie 90% of 12V = 10.8 volts. In the preferred embodiment, the reference voltage is about 1.2 volts and the voltage divider is a 9-1 divider. Therefore, when between the resistor R2 is 10.6 volts, the input to the comparator are equal, the output signal at the terminal 27 of the comparator is high, the voltage V ₁₂ is shown to be about 90% of its nominal value ing. The high signal at terminal 27 is transmitted via control line 32 to the circuit that generates the induced voltage. The high output of the comparator 24 is delayed by the delay circuit 25. The control signal indicates that the 5 volt power supply, the 3.3 volt power supply, and the 2.5 volt power supply are now at appropriate levels to be used to generate the induced voltage.
[0015]
FIG. 3 shows the present invention in more detail. A 12 volt main power signal from power supply 10 is supplied to the motherboard and monitored via line 301. This line provides the input to a voltage divider (not shown; see FIG. 2) included in the monitor integrated circuit 22. The power monitor integrated circuit 22 includes a timing circuit (not shown; see FIG. 2) that measures the time since the 12 volt source is equal to or exceeds 90% of its nominal value. This time is less than 100 ms window for the motherboard. When the timing circuit times out, control logic 304 controls the operation of transistors Q2, Q3, Q4 and Q5 to bring the 5-volt and 3.3-volt dual lines from their respective standby voltages to the line from power supply 10. Switch to voltage.
[0016]
Circuit 22 simplifies the implementation of ACPI compliant design in microprocessor and computer applications. The circuit 22 integrates not only two linear controllers and a low current pass transistor but also a monitoring function and a control function into a 16-pin SOIC package. One linear controller 305 generates a 3.3V dual voltage plane from the 5VSB output of the ATX power supply during sleep states S3, S4 / S5, and is external pass transistor as commanded by the status of the 3.3V dual enable pin To supply power to the PCI slot. An additional pass transistor is used to switch to the ATX 3.3V output for PCI operation during the S0 and S1 (active) operating states. The second linear controller 306 supplies the computer system's 2.5V / 3.3V memory power via an external pass transistor in the active state. During the S3 state, the integrated pass transistor provides 2.5V / 3.3V sleep state power. The third controller 307 powers up the 5V dual plane by switching the ATX5V output to the active state or ATX5VSB to the sleep state.
The operating mode of the circuit 22 (active state output or sleep state output) can be selected via two control pins 319 and 318. The logic 304 governing the activation of the different power modes is further controlled via two enable pins 319 and 320. In the active state, the 3.3V dual linear regulator 305 uses an external N-channel pass MOSFET 331 to connect the output 314 (VOUT1) directly to the 3.3V input supplied by the ATX (or equivalent) power supply with minimal loss. To do. In the sleep state, 3.3V dual output is supplied from the ATX5VSB 312 via the NPN transistor 330 which is also external to the controller. Active power delivery for 2.5 / 3.3 VMEM output 351 is performed via external NPN transistor 332 or 3.3V setting NMOS switch. In the sleep state, the conduction on this output is transferred to the internal pass transistor. Power is supplied to the 5V dual output 352 via two external MOS transistors. In the sleep state, the PMOS (or PNP) transistor 333 passes current from the ATX5VSB output, while in the active state, transfers current flow to the NMOS transistor 334 connected to the ATX5V output. As with the 3.3V dual output, the operation of the 5V dual output 352 is determined not only by the status of the 317 and 318 pins, but also by the status of the EN5VDL enable pin 319.
[0017]
The 5V5B power by the reset (POR) signal initiates the soft start sequence. An internal 10 μA current source charges the external capacitor to 5V. The error amplifier reference input is clamped to a level proportional to the soft start pin voltage. As the soft start pin voltage slews from approximately 1.25V to 2.5V, the input clamp allows a quick and controlled output voltage rise.
[0018]
FIG. 4 shows a typical application activation software activation sequence in the sleep state with all output voltages enabled. At time TO, 5VSB (bias) is applied to the circuit. At time T1, 5VSB exceeds the POR level and the internal fast charge circuit rapidly raises the SS capacitor voltage to about 1V. At this point, the 10 μA current source continues to charge the capacitor to T2, and once the voltage 1.25V (typically) is reached, the internal clamp limits further charging. Clamping of the soft start-up voltage (T2-T3 interval) should only be observed with capacitors smaller than 0.1 μF. A soft start capacitor of 0.1 μF or more provides a soft start lamp void for this plateau. At time T3 (3 ms (typically greater than 5VSBPOR (T1)), the 10 μA current source resumes charging the soft start capacitor. At this point, the reference input of the error amplifier begins their transition. The output voltage rises proportionally, the ramp continues until time T4 when all the voltages reach the set value, and the undervoltage monitoring circuit at time T5 when the soft start capacitor value reaches approximately 2.8V. Is activated and the soft start-up capacitor rapidly discharges and decreases to the value obtained at time T2 (about 1.25V).
[0019]
If both 317 and 318 are logic high when 5VSB is applied, then circuit 22 is considered active and approximately 50ms after ATX's 12V output (detected at 12V input 311). The controlled external transistor is not used until the set threshold (typically 10.8 V) is exceeded. This timeout function is necessary to ensure that the main ATX output is stabilized. Also, the timeout ensures a smooth transition from sleep to active when the sleep state is supported.
[0020]
During transition from sleep state to active state from state where output is initially 0V (eg, S4 / S5 to S0 transition with EN3VDL = 1 and EN5VDL = 0, or simple power-up sequence directly to active state) ) The 3V dual and 5V dual outputs are quasi-soft activated by being pulled high through the body diode of an N-channel MOSFET connected between these outputs and the 3.3V and 5VATX outputs, respectively. FIG. 5 shows this activation process.
[0021]
When the main ATX output is turned on at time T0, 5VSB already exists. Similarly, the soft start capacitor is already charged to 1.25V, the clamp is active and is waiting for the 12VPOR timer to expire. As a result of the 3.3VIN and 5VIN rise, the 3.3V dual and 5V dual output capacitors C1, C3 charge up via the body diodes of Q3 and Q5, respectively (see FIG. 3). At time T1, the 12VATX output exceeds the 12V undervoltage threshold of circuit 22, and an internal 50ms (typical) timer 25 (FIG. 2) is started. At T2, a soft start is started due to a timeout, the memory output increases, and the adjustment limit is reached at T3. At the same time as the memory voltage rises, the DLA output 321 is pulled high (up to 12V), turning on Q3 and Q5 and adjusting the 3.3V and 5V dual outputs at time T2. At time T4, when the soft start voltage reaches about 2.8V, the undervoltage monitoring circuit is enabled and the soft start capacitor is rapidly discharged to about 2.45V.
A request to enter the sleep state during the active state soft start up causes a new soft start sequence to the desired state after the chip is reset.
[0022]
With the power monitor circuit and method, the startup of the computer is delayed until the plurality of power lines reach a safe operating level. The integrated circuit monitors only the main power supply output voltage, and there is no need to provide a monitor circuit for each power supply. Ensure that the power supply meets strict specifications relating the 5 volt power supply and the 3.3 volt power supply to the main 12 volt power supply. The ATX power supply causes the 3.3 and 5.0 volt power supplies to reach 90% of their values within 40 ms after the 12 volt power supply reaches 90% of their values. The delay circuit 25 delays switching the dual supply of 3.3 volts and 5 volts from the standby voltage supply to the active voltage supply until the main 3.3 volts and 5 volts are at a safe operating level.
[Brief description of the drawings]
FIG. 1 is a high level schematic diagram of a power distribution system in a computer.
FIG. 2 is a schematic diagram of a comparator circuit of the present invention.
FIG. 3 is a schematic diagram of an integrated circuit using the power management circuit of the present invention.
FIG. 4 is a graph showing a soft start interval in a sleep state in which all outputs are enabled.
FIG. 5 is a graph showing a soft start interval in an active state.
[Explanation of symbols]
10 AC / DC power supply 20 Power monitor integrated circuit 22 Comparator circuit 24 Comparator 25 Delay circuit 27 Comparator terminal 30 Motherboard 32 Control line 301 Line 304 Control logic 305, 306, 307 Linear controller 311 Input 312 ATX5VSB
317, 318 Pin 319 EN5 VDL enable pin 321 DLA output 331 External N-channel pass MOSFET
332 External NPN transistor 333 PMOS (or PNP) transistor 334 NMOS transistor 351 2.5 / 3.3V VEM output 352 5V dual output

Claims (9)

An integrated circuit for monitoring and controlling a plurality of power outputs from a power source that generates a first main power voltage and one or more second main power voltages comprising:
Input means for receiving the first main power voltage and the second main power voltage and generating a controlled voltage power output;
Means for comparing a signal representative of the first main power voltage with a reference signal;
Or the first main power over voltage reaches the threshold reference voltage level, means for sensing when exceeded it,
After the first main power voltage reaches the threshold reference voltage level, a connection of the first main power voltage and the second main power voltage to the controlled voltage power output is selected. Means for delaying by the delay time;
Means for initiating a soft start after the selected delay time has passed;
An integrated circuit comprising: Means for generating a power-up signal indicating that the first main power voltage and the second main power voltage of the power supply are usable and at or above an effective voltage level ;
Said comparing means, and a voltage divider and a comparator, said comparator being coupled to a threshold reference voltage, said voltage divider being coupled to said comparator and said first main power voltage, more powerful the integrated circuit of claim 1, comprising a linear controller for controlling each of the output voltage of the power output voltage of the monitor circuit. The delay means comprises a timing circuit, and the output of the comparator delays the connection of the first main power voltage and the second main power voltage to the controlled output by the selected delay time. the integrated circuit according to 請 Motomeko 2 that is coupled to the timing circuit. A computer system having a monitored power, comprising a power source for generating a first main DC voltage and one or more second main DC voltages, a motherboard including a memory unit, and a central processing unit. Each unit requires an operating voltage different from other units, and a power monitoring integrated circuit for controlling power supply from the power source to the motherboard is disposed between the power source and the motherboard, comparing the power monitoring circuit receives the first main power voltage and second main power voltage, input means for generating a controlled voltage power output, the first reference signal a signal indicating the main power over voltage and And a computer system comprising:
Or the first main power over voltage reaches the threshold reference voltage level, means for sensing when exceeded it,
After the first main power voltage reaches a threshold reference voltage level, a selected connection to the controlled voltage power output of said first main power voltage and the second main power over voltage Means for delaying by the delay time;
A computer system further comprising: Means for generating a power-up signal indicating that the first main power voltage and the second main power voltage of the power source are usable and at an effective voltage level or exceeded ;
Said comparing means, and a voltage divider and a comparator, said comparator being coupled to a threshold reference voltage, said voltage divider being coupled to said comparator and said first main power voltage, the output The means for controlling a voltage comprises a plurality of linear controllers, each linear controller controlling one of the output voltages of the controlled power output voltage of the power monitor circuit. Computer system. The delay means comprises a timing circuit, and the output of the comparator delays the connection of the first main power voltage and the second main power voltage to the controlled power output by the selected delay time. The computer system of claim 5, wherein the computer system is coupled to a timing circuit. A method of monitoring and controlling power from a power source that generates a first main power voltage and one or more second main power voltages derived from the first main power voltage ,
Receiving the first main power voltage and the second main power voltage from a power source;
Controlling the received power voltage to generate a controlled voltage power output;
Comparing a signal representative of the first main power voltage with a reference signal;
Or the first main power over voltage reaches the threshold reference voltage level, the step of detecting when it exceeds it,
Delaying the connection of the controlled voltage power output to the computer after the first main power voltage has reached a threshold reference voltage level by a selected delay time. how to. Generating a power-up signal indicating that the first main power voltage and the second main power voltage of the power supply are usable and at an effective voltage level, or exceed the first main power voltage; Comparing a signal indicative of a reference signal with a signal indicative of the main power voltage comprises: voltage dividing the signal indicative of the main power voltage; and comparing the voltage divided signal with a threshold reference voltage; 8. The method of claim 7 , wherein each controlled power output voltage is linearly controlled. Determining a time interval at which the delaying step starts when the voltage division signal exceeds the threshold reference signal; and the controlled voltage power of the first main power voltage and the second main power voltage. The method of claim 8 , comprising delaying the connection to the output by a selected delay time.

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