JP2000339068A - Method for accessing main atx output without monitoring all outputs - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for providing a monitor circuit to all power supplies by delaying the starting of a computer until a plurality of power lines are set at stable operating levels and making an integrated circuit monitor only the output voltage of a main power supply. SOLUTION: A single power monitor integrated circuit having a single input main voltage pin monitors and controls the power which is supplied from a computer ATX power supply. The 3.3 and 5.0 V supply sources are connected to a 12 V supply source. A comparator circuit 22 compares a signal showing the main power voltage of 12 V with a reference signal. Then this power supply functions to set both 3.3 and 5.0 V supply sources at 90% of their value within 40 ms after the 12 V supply source reached 90% of its value. A proper delay circuit 25 delays an action to switch the dual supply of both 3.3 and 5.0 V from the standby voltage supply to the active voltage supply until the main 3.3 and 5.0 V operate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power monitor circuit, and more particularly to a circuit for monitoring the power of a personal computer.

[0002]

BACKGROUND OF THE INVENTION Personal computers include circuitry for monitoring and controlling the power supplied to different parts of the computer. Certain parts, such as memories, require different voltages than other parts, such as microprocessors. In order to conserve power and extend the life of an integrated circuit, it is economical to reduce the power available to components when the computer is inactive. Most computers have a power saving feature that reduces power after a predetermined time. The operator can control the time. During the power down time, a minimum power is provided to the computer. Theoretically, all that is needed is to provide enough power to detect when the user wants to return to full power. Despite the speed of the integrated circuit, a finite amount of time remains for the power supply to reach an operable level. If the computers start operating before the power supplies reach their operating levels, the calculations and operations performed by the computers may be incorrect. Such premature actions can result in operational errors,
The computer may fail and shut down. At this time, the user will have to restart the computer or possibly repair it.

[0003] Power management functions contribute to overall efficiency, conserve energy, and reduce computer operating costs. As personal computers have become more sophisticated, so have the power-up and power-down monitoring circuits. Computers use so many voltages that they need more sophisticated circuits. The main voltages used in the computer are 12 volts, 5 volts and 3.3 volts. These are A
It is supplied from the C / DC converter to other devices and chips in the computer. The motherboard itself on the computer itself needs additional voltage from the main voltage to operate the memory chips, graphics chips and clock chips. Nevertheless, all of these main voltage derived voltages are derived from the three main voltages 12 volts, 5 volts and 3.3 volts.

It is important that various devices be powered up and powered down in a manner specified by the computer manufacturer. Unless the power up and power down operations are controlled and there is not enough power, valuable data may be lost or the system may conflict with itself and crash. For proper operation, the three main voltages are 90% of their expected operating level.
Or about 90%. Microprocessor manufacturers such as Intel specify that the microprocessor and motherboard will be fully operational after a window of time. The time window is currently set at about 100 ms. Also, to assist PC manufacturers, Intel has stated that 3.3 volt and 5.0 volt sources have 90% of their values in 40 ms.
% Must be reached. The problem facing computer manufacturers is how to monitor the mains voltage to determine when a voltage derived from the mains voltage can be obtained.

Some manufacturers, one for each mains voltage,
It was proposed to use a total of three power supply monitoring chips.
This is an easy way, but increases the number of power monitors until three main voltages are balanced. Still another proposal is to use a single chip to monitor the power supply and include three main voltage monitoring circuits (one for each of the three main voltages) on that single chip. Was done.

[0006]

SUMMARY OF THE INVENTION The present invention improves upon known solutions by providing a single power monitor integrated circuit with a single input main voltage pin. According to the present invention, this desired result is obtained by using functions specific to the power supply. Ensure that the power supply meets strict specifications. According to these specifications, 5 volts and 3.
Connect a 3 volt source to a 12 volt source. This power supply causes the 3.3 volt supply and the 5.0 volt supply to reach 90% of their value within 40 ms after the 12 volt supply reaches 90% of its value.
Appropriate delay circuit 25 delays switching the 3.3 volt and 5 volt dual supplies from the standby voltage supply to the active voltage supply until after the main 3.3 volt and 5 volt operations.

According to the present invention, input means for receiving a plurality of power outputs from a power supply, means for controlling the input power output to generate a controlled voltage power output, and comparing a signal representing the main power voltage with a reference signal Means for monitoring and controlling power from a power supply that generates a plurality of different output voltages, wherein each power output voltage is derived from a main power voltage, wherein the main power output voltage is derived from a main power voltage. Means for detecting when the power supply reaches or exceeds a threshold reference level, and delaying the connection of the power output voltage to the computer for a selected delay time after the power supply reaches the reference threshold level. Means for providing an integrated circuit.

[0008] The integrated circuit provided by the present invention monitors and controls power from a computer ATX power supply. A typical ATX power supply generates a plurality of different output voltages, each output voltage being derived from a main power voltage, typically a 12 volt supply. This integrated circuit includes a number of input pins. These input pins serve as input means for receiving a plurality of power outputs from the ATX power supply. The integrated circuit also includes a conventional linear power controller circuit that controls each of the power outputs. The comparator circuit compares a signal indicating the main power voltage with a reference signal. The voltage divider provides one input to a comparator and the other input is provided by a threshold reference source. When the divided signal exceeds the threshold, the comparator
Outputs a signal indicating the result. This signal means that the main power supply has reached at least 90% of the target value. Next, the output of the comparator triggers the timing circuit. The timing circuit determines when the computer starts, ATX
Delay by the set time corresponding to the power supply timing specification. These specifications require that the voltage and power sources from the primary source be at their respective voltage levels within a very carefully controlled time (typically 40 microseconds). You. The timing circuit is set so that the delay time is equal to or exceeds the ATX specification. In a typical application, the delay is around 100
Set to microseconds. When the delay time ends, a power-up signal is generated in the present invention.

Further, according to the present invention, there is provided a computer system having monitored power, comprising: a power supply for generating a plurality of different DC voltages; a motherboard including a memory unit; and a central processing unit. Wherein each unit requires a different operating voltage than the other units, and a power monitoring integrated circuit that controls the supply of power from the power supply to the motherboard is disposed between the power supply and the motherboard; A monitoring circuit, input means for receiving a plurality of power outputs from the power supply, means for controlling the input power output to generate a controlled voltage power output, and a signal indicating the main power output voltage as a reference signal; A means for comparing the main power output voltage. Means for detecting when a threshold reference level is reached or exceeded, and means for delaying the connection of the power output voltage to the computer for a selected delay time after the power supply has reached a reference threshold level. And a computer system further comprising:

Further, according to the present invention, there is provided a method for monitoring and controlling power from a power supply generating a plurality of different output voltages, wherein each power output voltage is derived from a main power voltage, the method comprising: Receiving a power output of the input power output; generating a controlled voltage power output by controlling the input power output; comparing a signal representing the main power voltage with a reference signal; Detecting when a reference level is reached or exceeded, and delaying connection of a power output voltage to a computer by a selected delay time after the power supply reaches a reference threshold level; Is provided.

At that time, the computer can enter a desired operating state, including its active state or its sleep state.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a high-level circuit showing a part of a personal computer. ATX AC / D
C power supply 10 includes a transformer and a DC-DC converter chip. The power supply 10 has its input connected to an AC source. The nine outputs of the power supply 10 include a 5 volt standby output and three main voltage outputs of 12 volts, 5 volts and 3.
3 volts included. The outputs from the ATX power supply are tightly coupled to each other. In fact, they all come from the same AC source. If the main 12 volt power supply exceeds 90% of its nominal setting, the 5 volt and 3.3 volt supplies will equal or exceed 90% of their nominal setting at the end of the 40 ms window . In fact, a 12 volt main power voltage can be used as another main voltage proxy. Since the 5 volt and 3.3 volt sources are associated with the 12 volt source, there is no need to actually monitor 5 volts and 3.3 volts.
Instead, monitor a 12 volt source for overall compliance. Once the 12 volt supply is compliant, the 5 volt supply and the 3.3 volt supply will be in compliance by the end of the 40 ms window.

The comparator circuit 22 is connected to a power monitor
It is introduced into the integrated circuit 20. The comparator circuit 22 includes a resistor
With a resistor divider network including resistors R1 and R2
(See FIG. 2). Divide the voltage to comparator 24
Enough to be within the range of 5 volt standby power supply
A resistor with an appropriate value is selected. Input to the comparator 24
Voltage V_REFComes from a 5 volt standby power supply
You. The maximum reference level is 90% of the nominal value, ie, 1
Set 90% of 2V = 10.8 volts. Favorable fruit
In an embodiment, the reference voltage is about 1.2 volts and the voltage
The divider is a 9-1 divider. Therefore, the resistor R
If there is 10.6 volts between the two, the input to the comparator
Are equal and the output signal at terminal 27 of the comparator is high.
And voltage V ₁₂Indicates that it is about 90% of its nominal value
are doing. The high signal at terminal 27 is
It is transmitted via 32 to a circuit that produces an induced voltage. Ko
The high output of the comparator 24 is delayed by the delay circuit 25.
It is. The control signal is a 5 volt power supply and a 3.3 volt power supply.
Source and power supply for 2.5 volts now produces induced voltage
Indicates that it is at an appropriate level to use.

FIG. 3 illustrates the present invention in more detail. The 12 volt mains signal from power supply 10 is provided to the motherboard and monitored via line 301. This line provides an input to a voltage divider (not shown; see FIG. 2) contained within monitor integrated circuit 22. Power monitor integrated circuit 22 includes a timing circuit (not shown; see FIG. 2) that measures the time since the 12 volt source is equal to or greater than 90% of its nominal value. This time is less than 100 ms window for the motherboard. When the timing circuit times out, control logic 304 controls the operation of transistors Q2, Q3, Q4 and Q5,
Switch the 5 volt and 3.3 volt dual lines from their respective standby voltages to the line voltage from power supply 10.

Circuit 22 simplifies the implementation of ACPI compliant designs in microprocessor and computer applications. The circuit 22 integrates not only two linear controllers and low-current pass transistors, but also a monitoring function and a control function into a 16-pin SOIC package. One linear controller 305 generates a 3.3V dual voltage plane from the 5VSB output of the ATX power supply during sleep states S3, S4 / S5,
Power the PCI slot via an external pass transistor as dictated by the status of the 3.3V dual enable pin. Using an additional pass transistor, P0 during S0 and S1 (active) operating states
Switch to ATX 3.3V output for CI operation. The second linear controller 306 is used for the 2.5
V / 3.3V memory power is supplied via the external pass transistor in the active state. In S3 state,
An integrated pass transistor provides 2.5V / 3.3V sleep state power. The third controller 307
By switching the TX5V output to the active state or the ATX5VSB to the sleep state, the 5V dual plane is powered up. The mode of operation of the circuit 22 (active state output or sleep state output) can be selected via two control pins 319 and 318. The logic 304 governing the activation of the different power modes is further controlled via two enable pins 319 and 320. In the active state, the 3.3V dual linear regulator 305 has an external N-channel path MOSFET
2. Using T331, output 314 (VOUT1) is supplied by an ATX (or equivalent) power supply with minimal loss.
Connect directly to 3V input. 2. In the sleep state,
3V dual output from ATX5VSB 312 to NPN transistor 33 which is also external to the controller
Feed through 0. 2.5 / 3.3 VMEM output 35
The active power supply for 1 is performed via the external NPN transistor 332 or the 3.3 V setting NMOS switch. In the sleep state, conduction on this output is transmitted to the internal pass transistor. Power is supplied to the 5V dual output 352 through two external MOS transistors. In sleep mode, PMO
S (or PNP) transistor 333 is ATX5VS
Pass the current from the B output, while in the active state,
The current flow is transmitted to the NMOS transistor 334 connected to the ATX 5V output. Like the 3.3V dual output, the operation of the 5V dual output 352 is not only dependent on the status of the 317 and 318 pins, but also on the EN
It is also determined by the status of the 5VDL enable pin 319.

The 5V5B power from the reset (POR) signal initiates a soft start sequence. Internal 10μ
The A current source charges an external capacitor to 5V. The error amplifier reference input clamps to a level proportional to the soft start pin voltage. The soft start pin voltage is approximately 1.
As it slews from 25V to 2.5V, the input clamp allows for a fast and controlled output voltage rise.

FIG. 4 shows a typical software startup sequence for starting an application in a sleep state with all output voltages enabled. At time TO,
5 VSB (bias) is applied to the circuit. At time T1,
When 5VSB exceeds the POR level, an internal fast charge circuit rapidly raises the SS capacitor voltage to about 1V.
At this point, the 10 μA current source continues to charge the capacitor to T2, and once the voltage reaches 1.25V (typically), the internal clamp limits further charging. Clamping of soft start voltage (T2-T3 interval)
It must only be observed with capacitors smaller than 0.1 μF. A soft start capacitor of 0.1 μF or more provides a soft start ramp void for this plateau. Time T3 (3 ms (typically 5VSBPOR
At (beyond T1), the 10 μA current source resumes charging the soft-start capacitor. At this point, the reference input of the error amplifier is initiating those transitions,
The output voltage increases proportionally. The ramp continues until time T4 when all voltages reach the set value. At time T5 when the soft start capacitor value reaches about 2.8V, the undervoltage monitoring circuit is activated, and the soft start capacitor rapidly discharges and decreases to the value obtained at time T2 (about 1.25V). I do.

If both 317 and 318 are logic high when 5 VSB is applied, the circuit 22 is considered active and the ATX 12V output (12V
The controlled external transistor is not used until a set threshold (typically 10.8 V) is exceeded about 50 ms after the input 311 is detected). This timeout function is
It is necessary to ensure that the TX output is stabilized. In addition, the timeout ensures that a smooth transition from sleep to active occurs when the sleep state is supported.

During the transition from the state where the output is initially 0 V to the sleep state to the active state (for example, EN3
S4 / S5 to S5 with VDL = 1 and EN5VDL = 0
0 transition, or simple power-up sequence to the direct active state) The 3V dual and 5V dual outputs are via the body diode of an N-channel MOSFET connected between these outputs and the 3.3V and 5VATX outputs, respectively. The software is activated by being pulled high. FIG. 5 shows this activation process.

When the main ATX output is turned on at time T0, 5VSB is already present. Similarly, the soft-start capacitor is already charged to 1.25V, the clamp is active, and the 12V PO
Waiting for R timer to expire. 3.3 VIN and 5
As a result of the VIN rise, the 3.3V dual and 5V dual output capacitors C1, C3 charge up via the body diodes of Q3 and Q5, respectively (see FIG. 3). At time T1, the 12 VATX output is
Exceeds 2V undervoltage threshold, internal 50ms (typical)
The timer 25 (FIG. 2) is started. At T2, the soft start is started due to the timeout, the memory output increases, and the adjustment limit is reached at T3. Simultaneously with the memory voltage rise, DLA output 321 is pulled high (up to 12V), turning on Q3 and Q5, and 3.3 at time T2.
Adjust V dual output and 5V dual output. Time T
At 4, when the soft start voltage reaches about 2.8V, the undervoltage monitoring circuit is enabled and the soft start capacitor is rapidly discharged to about 2.45V. A request to enter the sleep state during the active state soft start up causes a new soft start sequence to the desired state after the chip is reset.

The power monitoring circuit and method delays computer startup until a plurality of power lines are at a safe operating level. The integrated circuit monitors only the main power supply output voltage, eliminating the need to provide a monitor circuit for each power supply. The power supply should meet the exact specifications relating the 5 volt power supply and the 3.3 volt power supply to the main 12 volt power supply. The ATX power supply will cause the 3.3 volt power supply and the 5.0 volt power supply to reach 90% of their value within 40 ms of the 12 volt power supply reaching 90% of its value. The delay circuit 25 switches between the 3.3 volt and the 5 volt dual supplies from the standby voltage supply to the active voltage supply, mainly at 3.3 volts and 5 volts.
Delay until the bolt is at a safe operating level.

[Brief description of the drawings]

FIG. 1 is a high-level schematic diagram of a power distribution system in a computer.

FIG. 2 is a schematic diagram of a comparator circuit of the present invention.

FIG. 3 is a schematic diagram of an integrated circuit using the power management circuit of the present invention.

FIG. 4 is a graph showing a soft start interval in a sleep state in which all outputs are enabled.

FIG. 5 is a graph showing a software activation interval in an active state.

[Explanation of symbols]

 Reference Signs List 10 AC / DC power supply 20 Power monitor integrated circuit 22 Comparator circuit 24 Comparator 25 Delay circuit 27 Comparator terminal 30 Motherboard 32 Control line 301 Line 304 Control logic 305,306,307 Linear controller 311 Input 312 ATX5VSB 317,318 Pin 319 EN5VDL enable Pin 321 DLA output 331 External N-channel pass MOSFET 332 External NPN transistor 333 PMOS (or PNP) transistor 334 NMOS transistor 351 2.5 / 3.3V VEM output 352 5V dual output

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[Procedure amendment]

[Submission date] June 5, 2000 (2006.5.5)

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG.

FIG. 2

FIG. 3

FIG. 4

FIG. 5

Claims (9)

[Claims] An input means for receiving a plurality of power outputs from a power supply, means for controlling the input power output to generate a controlled voltage power output, and means for comparing a signal representing the main power voltage with a reference signal. An integrated circuit for monitoring and controlling power from a power source generating a plurality of different output voltages, wherein each power output voltage is derived from a main power voltage, wherein the main power output voltage is a threshold value Means for detecting when a reference level is reached or exceeded; means for delaying connection of a power output voltage to a computer by a selected delay time after the power supply reaches a reference threshold level; An integrated circuit, further comprising: 2. The system of claim 1 further comprising means for generating a power-up signal indicating that all monitored output voltages of the monitored power supply are at or above a usable and valid voltage level, and wherein said comparing means includes a voltage-up signal. A divider and a comparator, wherein the comparator is coupled to a threshold reference voltage, the voltage divider is coupled to the main power voltage and the comparator, and further comprising a power output voltage of the power monitor circuit. 2. The integrated circuit according to claim 1, further comprising a linear controller for controlling an output voltage of each of the integrated circuits. 3. The method of claim 2, wherein said delay means comprises a timing circuit, and wherein the output of said comparator is coupled to a timing circuit for delaying connection of said power supply voltage to said computer by said selected delay time. The integrated circuit according to claim 2, characterized in that: 4. A computer system having monitored power, comprising: a power supply for generating a plurality of different DC voltages; a motherboard including a memory unit; and a central processing unit, wherein each unit includes another unit. A power monitoring integrated circuit that requires a different operating voltage from the unit and controls supply of power from the power supply to the motherboard is disposed between the power supply and the motherboard, and the power monitoring circuit includes:
Input means for receiving a plurality of power outputs from the power supply, means for controlling the input power output to generate a controlled voltage power output, and means for comparing a signal indicative of the main power output voltage with a reference signal; Means for detecting when the main power output voltage reaches or exceeds a threshold reference level; and a power output voltage after the power supply reaches the reference threshold level. Means for delaying the connection to the computer by a selected delay time. 5. The system of claim 1, further comprising means for generating a power-up signal indicating that all monitored output voltages of the monitored power supply are at or above a usable and valid voltage level, and wherein said comparing means comprises a voltage-up signal. A divider and a comparator, wherein the comparator is coupled to a threshold reference voltage, the voltage divider is coupled to the main power voltage and the comparator, and a plurality of means for controlling the output voltage. The computer system according to claim 4, wherein each of the linear controllers controls the output voltage of one of the power output voltages of the power monitor circuit. 6. The apparatus of claim 6, wherein said delay means comprises a timing circuit, and wherein the output of said comparator is coupled to a timing circuit for delaying connection of said power supply voltage to said computer by said selected delay time. The computer system according to claim 5, characterized in that: 7. A method for monitoring and controlling power from a power supply generating a plurality of different output voltages, wherein each power output voltage is derived from a main power voltage, the method comprising receiving a plurality of power outputs from the power supply. Controlling the input power output to generate a controlled voltage power output; comparing a signal representing the main power voltage with a reference signal; and determining whether the main power output voltage reaches a threshold reference level; Detecting when it has exceeded it, and delaying the connection of the power output voltage to the computer for a selected delay time after the power supply reaches a reference threshold level. Features method. 8. A power-up signal is generated to indicate that all monitored output voltages of the monitored power supply are at or above a usable and valid voltage level, and the comparing step indicates the main power voltage. Voltage dividing the signal, comprising comparing the voltage divided signal with a threshold reference voltage, linearly controlling each of the power output voltages of the power monitor circuit;
The method according to claim 9, characterized in that: 9. The method of claim 1, wherein the delaying step determines a time interval that begins when the voltage divided signal exceeds the threshold reference signal, and connects the power supply voltage to the computer for a selected delay time. The method of claim 7, comprising delaying.