TW484050B - Accessing main ATX outputs without monitoring all outputs - Google Patents

Accessing main ATX outputs without monitoring all outputs Download PDF

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Publication number
TW484050B
TW484050B TW089107585A TW89107585A TW484050B TW 484050 B TW484050 B TW 484050B TW 089107585 A TW089107585 A TW 089107585A TW 89107585 A TW89107585 A TW 89107585A TW 484050 B TW484050 B TW 484050B
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TW
Taiwan
Prior art keywords
power
voltage
output
supply
power supply
Prior art date
Application number
TW089107585A
Other languages
Chinese (zh)
Inventor
Bogdan Duduman
Original Assignee
Intersil Corp
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Publication date
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Publication of TW484050B publication Critical patent/TW484050B/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/28Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/36Means for starting or stopping converters

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Power Sources (AREA)
  • Direct Current Feeding And Distribution (AREA)

Abstract

A power monitor circuit method delays the start of a computer until multiple power lines are at a safe level of operation. The integrated circuit monitors only the voltage of a primary power supply output and eliminates the need for monitor on each supply. The power supply is made to exacting specifications that tie the 5 volt and 3.3 volt supplies to the primary 12 volt supply. The ATX power supply drives the 3.3 and 5.0 supplies to reach 90% of their values within 40 ms after the 12 volt supply reaches 90% of its value. A time delay circuit 25 delays switching the 3.3 and 5 volt dual supply from the standby voltage supply to the active voltage supply until after the primary 3.3 and 5 volt are at a safe operating level.

Description

A7 B7 五、發明說明( 上月係屬於—電力監視電路及特別 路,-電路用於監視一個人電腦之電力。 屬… 値人電腦且古 ^ 腦之不同:;Λ—Γ,該電路監視及控制電力供給至電 例如微處理器:要=邵::如記憶體,τ、同之其他部分 ^ &入而要不同心電壓。爲了節省電力,延長積體 U’L’t電腦不工作時減少送至元件可用之電力較 :了'彳七刀、電腦具有在-預定時間及減少電力之電力 :省功能。操作者可控制該-時間。在當電力停用時間σ 了取低電力送至電腦。理論上,當使用者感到在回恢至要 ί全邵電力僅在需要時才供充分之電力才合理。不理積體 “各之4度’ a尚有充分充裕之時間用於將電力供應至其 可運作之位準。如果電腦在供應至其位準前即行開始運 作,則由電腦執行之電腦工作及運作可能是錯誤的。此種 匕早之運作可㈣造成運作巾之誤差致使電腦失敗及停機, 然後使:者必需再起動電腦或可能需加以檢修。 处電力管理功能可提供電腦運作全面效率之程度,節省電 能至減低成本。在個人電腦已趨向精密化之時,t力加入 及:力V用之監視電路亦相同爲精密化。電腦因使用多種 包壓而需有較多(精細電。使用於電腦之起始電壓爲12伏 特,5伏特及3.3伏特。由一交流/直流轉換器供應至其他 設置及電腦内之晶片。如此,在電腦之母板在起始電壓外 仍需要進-步之驅動電壓用於運作之記憶晶片,緣圖晶片 及時脈晶片。不過,所有這些驅動電壓由12,5,3·3伏特 三個起始電壓來驅動。 4· 本纸張尺度適用中國國家標準(CNS)A4規格(21〇 χ 297公爱) ^tr---------· (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 A7 ^ _________B7_ 五、發明說明(2 ) 兩重點爲知由電腦製造者加以規範之方法來對許多設置做 :力加入或電力停止。除非電力加上及電力停用運作乃在 九足 < 電力下被控制,否則重要資料可能被遺失或者系統 可此與其本身抵觸及衝撞。 、對於適當之運作,三個起始之電壓必需爲或高於其預期 又運作位準炙百分之九十方可。微處器之賣主,例如英特 爾公司,對微處理器及母板之規範指出在一預先決定之時 間窗後將可全面運作。時間窗之設定近於1〇〇毫秒。爲了 協助個人電腦製造廠英特爾規範訂定3.3及5伏特供應必需 f 40毫秒達到其値之百分之九十。電腦製造廠所面對之g 題爲當自起始電壓驅動之電壓被建立時如何監視起始電壓 而做成決定。 一些製造廠提供使用三個電力供給之監視晶片,每一起 始電壓使用一個。此爲一直接了當的做法,僅爲配合三個 起始電壓而增加了電力供給監視之數量。一些其他者建議 一單一之晶片用於監視電力供給及在該一單一晶片包括即 二個起始電壓之每一個有一電路之三個起始電壓監視電 路。 ^ 發明藉提供具有一單一輸入電壓管腳之一單一監視之積 时電路來改善已知解決之道。發明藉使用電力供給一内在 之特徵來元成此一所需之結果。電壓供給可以確實達成規 範之要求。該規範連接5伏特及3.3伏特至12伏特供應上。 電壓供應將在1 2伏特達到其値之百分之九十後於4 〇毫秒 内驅動3.3及5.0供應達到其値之百分之九十。一適當之時 本紐尺度朝巾關家鮮(CNS)A4規格(21G X 297公爱) ' -------- . --------訂--------- (請先閱讀背面之注意事項再填寫本頁} A7A7 B7 V. Description of the invention (Last month belonged to-electric power monitoring circuit and special road,-the circuit is used to monitor the power of a personal computer. It belongs to the difference between a human computer and an ancient brain: Λ-Γ, the circuit monitors and Control the supply of electricity to electricity such as a microprocessor: To = Shao :: such as memory, τ, and other parts ^ & to be different voltage. To save power, extend the integrated U'L't computer does not work The power available to the component is reduced when compared to the following: the 'seven knives, the computer has an on-predetermined time and the reduced power: power saving function. The operator can control the -time. When the power is deactivated, σ takes a lower power Send to the computer. In theory, when the user feels that it is necessary to recover the full power only when it is needed, it is reasonable to provide sufficient power. Ignore the building "4 degrees each" a There is still sufficient time to use It is necessary to supply electricity to its operational level. If the computer starts to operate before it is supplied to its level, the computer work and operation performed by the computer may be wrong. Such early operation can lead to operational problems. The error caused the Failure and downtime, then: the need to restart the computer or may need to be repaired. The power management function can provide the computer with the full efficiency of the operation, saving electricity to reduce costs. When the personal computer has become more sophisticated, t And: The monitoring circuit for Force V is also precise. The computer needs more because of using a variety of package pressure (fine electricity. The initial voltage used in the computer is 12 volts, 5 volts and 3.3 volts. From an AC / The DC converter is supplied to other settings and chips in the computer. In this way, the motherboard of the computer still needs a step-by-step driving voltage for the operating memory chip, the edge map chip and the clock chip. However, all These driving voltages are driven by three starting voltages of 12, 5, 3, and 3 volts. 4. The paper size applies to the Chinese National Standard (CNS) A4 specification (21〇χ 297 public love) ^ tr ----- ---- · (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumers ’Cooperatives of the Ministry of Economics and Intellectual Property Bureau Printed A7 ^ _________B7_ V. Description of the Invention 2) The two main points are that the computer manufacturer regulates many settings to do many settings: power on or power off. Unless power plus and power off operation are controlled under the nine feet < power, important information may be It can be lost or the system can collide with itself. For proper operation, the three starting voltages must be 90% or higher than their expected and operating levels. The seller of microprocessors, For example, Intel Corporation, the specifications for microprocessors and motherboards indicate that they will be fully operational after a predetermined time window. The time window is set to approximately 100 milliseconds. In order to assist the personal computer manufacturer Intel specification 3.3 and A 5 volt supply must f 40 milliseconds to reach ninety percent of it. The g faced by computer manufacturers is to make a decision on how to monitor the starting voltage when a voltage driven from the starting voltage is established. Some manufacturers provide monitoring chips that use three power supplies, one for each starting voltage. This is a straightforward approach, increasing the number of power supply monitors only to match the three starting voltages. Some others have suggested that a single chip be used to monitor the power supply and three start voltage monitoring circuits having a circuit on each single chip including two start voltages. ^ The invention improves the known solution by providing a time-integrated circuit with a single monitor with a single input voltage pin. The invention achieved this desired result by using an inherent feature of electricity supply. The voltage supply can indeed meet the specifications. This specification connects 5 volts and 3.3 volts to a 12 volt supply. The voltage supply will drive 3.3 and 5.0 supplies to 90% of its voltage within 40 milliseconds after 12 volts reaches 90% of its voltage. When the time comes, the New Zealand-standard North Korean towels (CNS) A4 specifications (21G X 297 public love) '--------. -------- Order ------- -(Please read the notes on the back before filling out this page) A7

五、發明說明(4 ) 始電源驅動之電壓及電力咖 其各自之電壓位準,棹準小心控制之時間内爲在 電力加上信號。|&amp;時間’時間延遲終了後,發明產- ::月尚包括電腦系統’該電腦系統具有 生夕個不同直流電壓之—電力供給之電力。—母產 其 早凡及一中央處理單元,其中每一單元需要由Τ己 他單元來之一運作電饜· 早而要由不同之 力供給與母板之間用於控:來— 輸 壓 之 孩電力監視電路包含用於接收自電力供紙來:供給 :心輸入裝置’用於控制輸入電力輸出 二” 廷力輸出之裝置,用於包括將—代表起朴 一信號與一參考信號比較之裝 並 輸出廷壓 壓 於 出電壓達到或超過—門摇參考^馬當起始電力 供給達到門极參考位準^裝一裝1料感測及電 延遲將電力輸出電壓連接至ί腦/選擇〈延遲時間用 發明更進-步包括一方法,該方法用於 電力供给來之電力。該電力供給產生—多個2担制由 壓’其中每一電力輸出電壓由來自_起始之電:::: 動。其特點爲接收電力供給來之多個電:Ε坠來 電力輸出至產生控制之電壓電力輸出,將輸 壓〈-信號與-參考信號比較,當電 電力 二晴考位準時感測,及在電a:;:; “率及依_所選擇之延遲時間延遲將輸出電壓連接^ 本紙張尺度翻中各⑽ X 297公釐) A7V. Description of the invention (4) The voltage of the power source and the power supply have their respective voltage levels, and carefully control the time to add a signal to the power. | &amp; Time ’After the time delay expires, the invention- ::: Month still includes a computer system’ The computer system has electricity with different DC voltages—electric power supply. —The mother produces its early fan and a central processing unit, each of which needs to be operated by one of the other units. · Early but by a different power supply to the mother board for control: come — power transmission The children's power monitoring circuit includes a device for receiving power from a paper supply: supply: cardiac input device 'for controlling input power output 2' and a device for outputting power, including comparing-representing a signal from a simple signal with a reference signal Install and output voltage when the output voltage reaches or exceeds the gate swing reference ^ when the initial power supply reaches the gate reference level ^ install a package 1 material sensing and electrical delay to connect the power output voltage to the brain / Selecting <Increase the delay time with the invention-a step further includes a method for supplying power from the power supply. The power supply is generated-a plurality of 2 load voltages where each power output voltage is from :::。 It is characterized by receiving multiple electric power from the power supply: Ε falling electric power output to the control voltage power output, comparing the input voltage <-signal with-reference signal, when the electric power is cleared On time And electrically a:;:; "_ by the selected rate and delay time of the output voltage connection ^ scale turn each sheet of the present ⑽ X 297 mm) the A7

訂 齒 請 先 閱 讀 背 面 之 注 項 再癱 填 寫裝To read the teeth, please read the note on the back first.

本衣 頁IShirt Page I

I Λ7 B7 五、發明說明(6 -比一、:電路22引入至電力監視積體電路20,比較哭 馬:电阻除法接線包括電阻以㈣,見圖 毛阻有充份之値使得電壓至比較器22 _ 供給電壓之範圍内。妗λ $ u Α 在5伙特備用 ik # ^ ^ 軸入至比較器24之電壓VREF由來自5 =用電力供給驅動。所設定之最高參考電壓位準 九十。即12伏特之百分之九十等她伏 選之具體實施例中,參考電壓約爲⑽及電 控 106伏9比Κ除法器。如此,當跨接於電阻尺2爲 特時,輸入至比較器爲相等及在比較器之端子27之 輸^號馬高且指出電壓Vi2爲約標示値之百分之九十 在端子2 7之高信號經控制線3 2傳送至產生驅動電壓之 路:比較态24之高輸出由一計時延遲電路25被延遲。 制信號指出此用於5,3.3及2 · 5伏特之電力供給現在已爲 於使用產生驅動電壓之適用之位準。 來 除 、轉至圖3,指出發明之進—步之説明,由電力供給ι〇 '伏特起^电壓供給信號送至母板及經線3 0 1被監視 該線提供一輸入至-電壓除法器(未示出,見圖2)。該邱— 法器包括有内部監視積體電路22。電力監視積體電路Μ 包,一計時電路(未示出,見圖2)用來測定自當12伏特供 給等於或超過其標示値之百分之九十時之時間起。此一時 間較用於母板之100毫秒爲短。當計時電路時間到時,控 制邏輯304控制電晶體Q2,q3,(54及〇5動作自電力供給 1〇,5伏特3·3伏特二線自各自之備用電壓_換至線電壓。 電路22在微處理機及電腦應用中簡化爲Acpi順從敦計執 I · 9 - 本纸張尺度適用中國國豕標準(CNS)A4規格(210 X 297公爱) 經濟部智慧財產局員工消費合作社印製 484050 A7 B7 五、發明說明(7) 行。電路22集合二個線性控制器及一低電流通過電晶體, 一如一在一 16管腳SOIC組件内之監視及控制功能。一線性 控制器305產生由一 ATX電力供給之5VSB輸出來之3.3V DUAL電壓平面當在休止狀態S3,S4/S5時。如由3.3V DUAL允許管腳之狀態所指示,經一外部通過電晶體對 PCL窗口加上電壓。使用一外加通過電晶體在S 1及S 1 (動 作)運作狀態時對PCL運作切換至ATX 3.3伏特輸出。第二 線性控制器306在活動狀態中經一外部通過電晶體供應電 月甾系統之2.5伏/3.3伏記憶體電力。在S3狀態,一積體通 過電晶體供應2.5伏/3.3伏休止狀態電力。一第三控制器 307在活動狀態由ATX 5伏特輸出或在休止狀態由ATX 5VSB切換供電至5V DUAL平面。 電路2 2之運作模式(活動狀態輸出或休止狀態輸出)經二 控制管腳319及3 18為一可擇者,邏輯304之進一步控制經 過允許管腳319及320來調整提供不同電力模式之動作。在 活動狀態,3.3V DUAL線性調整器305使用一外部N -通道 通過MOSFET電晶體331連接至輸出314 (V OUT 1),當在處 於最低損失時,由一 ATX(或同等之)電力供給直接供應至 3.3伏特輸入。在休止狀態,3.3V DUAL輸出由ATX 5VSB 3 12經一 NPN電晶體供應,亦可由外部加至控制器。活動 狀態對2.5/3.3伏特MEM輸出輸送電力經一外部之NPN電晶 體332或用於3.3伏設定之一 NM0S半導體開關來完成。在 休止狀態時,在此一輸出通路轉換至一外部通過電晶體。 5 V DUAL輸出3 52經二個外部M0S半導體來供給電力。在 -10- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) --------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 484050 Λ7 H7 8 五、發明說明( 休止狀態,一PM0S(或NPN)半導體;333由aTX 5 VSB輸出接 通黾流。當在活動狀態,電流經過轉換器至一 NM〇s半導 體334連接至ATX 5伏輸出。與接至3 3 v DUAL輸出相 同,5 V DUAL輸出352之運作不但僅由317及318管腳之狀 怨來指揮亦可由EN5VDL允許管腳319—樣來指揮。 一 5 VSB電力加入重置(P0R)信號啟動一軟-起動狀態程序 一内部1 0微安電流電源對一外部電容器充電至5伏。誤差 放大器參考輸入箝位至比例於軟-起動管腳電壓之位準。 當軟·起動管腳電壓自約125至2 5切斷時,輸入箝位使一 快速及控制之輸出電壓得以升高。 圖4示出軟-起動程序,用於標準之應用在一休止狀態及 所有輸出電壓被允許下之起動性形。在5 VSB(偏壓)加至 電路之時間。在時間T 1,5VSB超過FOR之位準,及一内 部快速充電電路迅速將58電容器電壓升至後1伏。在此一 點’一 1 0微安電流電源繼績充電電容器一直至T 2。在 1.25伏(標準)之電壓達到時及一内部之箝位限制進一步充 電。軟-起動電壓之充電(丁2至丁3之期間)應注意電容器應 較〇·1微法拉弟為小。〇1微法之軟-起動電容器及高於此值 表示一軟-起動之坂度為一無效之手坂。在時間T 3,3毫 秒(經過5VSB P〇R (T1)之標準),丨〇微安電流電源再次對 軟-起動電容器充電。在此一點,誤差放大器之參考輸入 起動其轉移,使輸出電壓成正比之上升,上升繼續一直至 當所有電壓達到設定值時之時間T 4。在時間T 5 ,當軟-起 動電容器值達到約2·8伏時,低電壓監視電路動作及軟-起 --------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -11- 484050 Λ7 H7 9 五、發明說明( 動電容器快速放電至時間丁 2所得到之值(約! 1乃伏)。 如317及318—個在時間5VSB加上時為邏輯高,電路22將 假設為一活動狀態及保持控制之外部電晶體為打開一直至 约5 0笔秒在ATX之1 2伏輸出(在輸入3 1丨,12伏被感測)超 過汉足之門松值(標準為〗〇 8伏)之後。此一時間到之特點 是必需的,目的為確保主Ατχ之輸出為安定。此一時間到 當處於休止狀態時亦可保持一休止至活動之平滑轉換。 當在休止至活動狀態轉換時由輸出為起始之〇伏情況(例 如S4/S5至S0,EN3VDL=1及EN5VDL=0轉移,或單一電壓加 入程序直接近入活動狀態),3V DUAL及5V DUAL輸出經 一準軟_起動由經N通道M〇SFET電晶體各別連接至其輸出 與3.3伏及5伏ATX輸出之間之已被提高之體二極體。圖5 示出此一起動之說明。 當主ATX之輸出在時間丁 〇關入時5VSb已出現,同樣, 軟-起動電容器已經被充電至125伏及箝位為活動,等待 至1 2伏POR計時完畢,結果3 3V爪及5V IN上升,3 DUAL及5V DUAL輸出電容器C1&amp;C3經各自之體二極體 Q3及Q5充電(見圖3)。在時間T1,U伏Ατχ輸出超過電 路2 2 H 2伏特低電壓門檻及内部5 〇毫秒(標準)計時器2 $ 被啟動(圖2)。在Τ2時間到啟動一軟-起動,及記憶體輸 出升高,達到在時間Τ 3之調整限制。同時記憶體電壓升 高,DLA輸出321被提升到高(至12伏)將卩3及(^5導通, 及在時間Τ2將3.3V DUAL及5V DUAL輸出加至調整值.。在 時間T4,當軟-起動電壓達到約48伏時,低電壓監視電路 --------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 •12- Α7 Β7 五 、發明說明(1〇 ) 部 智 慧 員 工 消 費 被^許及軟*起動電容器迅速放電至約2.45伏。 j:活動狀態軟-起動升高時要求至休止狀態之牡果 狀態 重置遵循一新的軟,動程序俾進入所需要之 種電力監視電路及方法將一電腦之狀態延遲一直至☆ 力線在一運作安全位準之時。積體電路僅監視起始之電$ 供應輸出及免去對每一供給之監視。電壓供給做成連接$ 伏特及3.3伏特至一起始之丨2伏特供給與確實之規範 同。在1 2伏特供給達到其値之百分之九十後,在4 〇毫 内,ATX電力供給驅動3_3及5〇供給達到其値之百分之 十。一時間延遲電路2 5一直至起始之3·3及5伏特在—安 運作位準後將3 ·3及5伏特二個供給自備用電壓供給延遲 換至主動電壓供給。 元件符號說明 1 0 電力供應 2 ° 電力監視積體電路 22 比較器電路 24 比較器 25 計時延遲電路 2 7、2 9端子 '3 〇 母板 3 04 控制邏輯 3〇5 &gt; 3 0 6 ^ 3 0 7 線性控制器 相 秒 九 全 切 頁 訂 印 I_.____-13- 本紙張尺度適用中關家標準(CNS)A4規格⑵G χ 297公爱I Λ7 B7 V. Description of the invention (6-1): Circuit 22 is introduced to the power monitoring integrated circuit 20, which is more crying: resistance division wiring includes resistance to ㈣, as shown in the figure, the gross resistance is sufficient to make the voltage to compare Device 22 _ within the range of supply voltage. 妗 λ $ u Α is in 5 units of standby ik # ^ ^ The voltage VREF that is fed to the comparator 24 is driven by 5 = power supply. The set maximum reference voltage level is nine. 10. That is, ninety percent of 12 volts, etc. In her specific embodiment, the reference voltage is about ⑽ and the electric control is 106 volts and the 9-k divider. So, when it is connected across the resistance ruler 2 is special, The input to the comparator is equal and the input at the terminal 27 of the comparator is high. It indicates that the voltage Vi2 is about 90% of the mark. The high signal at the terminal 2 7 is transmitted to the drive voltage through the control line 3 2. The way: The high output of comparison state 24 is delayed by a timing delay circuit 25. The signal indicates that the power supply for 5, 3.3 and 2.5 volts is now a suitable level for generating a driving voltage for use. Remove, go to Figure 3, point out the progress of the invention-a description of the The supply voltage is supplied to the motherboard and the warp line 301 is monitored. This line provides an input-to-voltage divider (not shown, see Figure 2). The Qiu-Makeup device includes an internal Monitoring integrated circuit 22. The power monitoring integrated circuit M package, a timing circuit (not shown, see Figure 2) is used to determine the time from when the 12 volt supply equals or exceeds ninety percent of its marked value. This time is shorter than the 100 milliseconds used for the motherboard. When the timing circuit time is up, the control logic 304 controls the transistors Q2, q3, (54 and 〇5 to operate from the power supply of 10.5 volts and 3.3 volts. The second line is switched from the respective standby voltage to the line voltage. Circuit 22 has been simplified to Acci compliance in the microprocessor and computer applications. I-9-This paper size applies to China National Standard (CNS) A4 specification (210 X 297 Public Love) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 484050 A7 B7 V. Description of the invention (7) Line. Circuit 22 integrates two linear controllers and a low-current through transistor, as always on 16-pin Monitoring and control functions in SOIC components. A linear controller 305 The 3.3V DUAL voltage plane generated by the 5VSB output of an ATX power supply is in the rest state S3, S4 / S5. As indicated by the state of the 3.3V DUAL allowable pin, the PCL window is added through an external transistor The voltage is applied. An external transistor is used to switch the PCL operation to ATX 3.3 volt output during S 1 and S 1 (action) operation. The second linear controller 306 is supplied with electricity through an external transistor in an active state. 2.5V / 3.3V memory power of the steroid system. In S3 state, a product supplies 2.5V / 3.3V rest state power through a transistor. A third controller 307 is powered by the ATX 5V output in the active state or switched to the 5V DUAL plane by the ATX 5VSB in the inactive state. The operating mode of the circuit 2 2 (active state output or resting state output) is controlled by the two control pins 319 and 3 18, and the further control of the logic 304 allows the pins 319 and 320 to adjust the action of providing different power modes. . In the active state, the 3.3V DUAL linear regulator 305 uses an external N-channel to connect to the output 314 (V OUT 1) through the MOSFET transistor 331. When at the lowest loss, it is directly powered by an ATX (or equivalent) power supply Supply to 3.3 Volt Input. In the resting state, the 3.3V DUAL output is supplied by an ATX 5VSB 3 12 via an NPN transistor, or it can be externally applied to the controller. The active state delivers power to the 2.5 / 3.3 Volt MEM output via an external NPN transistor 332 or one of the NMOS semiconductor switches used for 3.3 Volt setting. In the quiescent state, an output path is switched to an external pass transistor. 5 V DUAL output 3 52 is supplied by two external MOS semiconductors. In -10- this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -------------------- Order ------ --- Wire (please read the precautions on the back before filling this page) 484050 Λ7 H7 8 V. Description of the invention (Pause state, a PM0S (or NPN) semiconductor; 333 is connected to the current by the aTX 5 VSB output. When in In the active state, the current passes through the converter to an NMOS semiconductor 334 and is connected to the ATX 5 volt output. As with the 3 3 V DUAL output, the operation of the 5 V DUAL output 352 is not only caused by the complaints of the 317 and 318 pins. The command can also be commanded by EN5VDL allowing pin 319. A 5 VSB power-on reset (P0R) signal initiates a soft-start state procedure. An internal 10 microamp current source charges an external capacitor to 5 volts. Error amplifier The reference input clamp is proportional to the level of the soft-start pin voltage. When the soft-start pin voltage is cut off from about 125 to 25, the input clamp increases a fast and controlled output voltage. Figure 4 shows the soft-start sequence, which is used for standard applications in a rest state and where all output voltages are allowed. 5 VSB (bias voltage) is added to the circuit. At time T 1,5VSB exceeds the FOR level, and an internal fast charging circuit quickly raises the voltage of the 58 capacitor to the next 1 volt. At this point '-1 10 microamps The current power source continues to charge the capacitors up to T 2. When the voltage of 1.25 volts (standard) is reached and an internal clamping limit is used for further charging. The charging of the soft-starting voltage (during the period from 2 to 3) should pay attention to the capacitor It is smaller than 0.1 microfarad. The soft-starting capacitor of 1 microfarad and a value higher than this indicates that a soft-starting saka degree is an invalid hand saka. At time T 3, 3 milliseconds (after 5VSB P 〇R (T1) standard), 丨 〇 The micro-ampere current power source charges the soft-start capacitor again. At this point, the reference input of the error amplifier initiates its transfer, causing the output voltage to rise in proportion to it, and the rise continues until all Time T 4 when the voltage reaches the set value. At time T 5, when the value of the soft-start capacitor reaches about 2 · 8 volts, the low-voltage monitoring circuit operates and soft-starts ------------ -------- Order --------- line (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-11- 484050 Λ7 H7 9 V. Description of the invention (the value obtained by quickly discharging the moving capacitor to time D2 (approximately! 1 is volts). Such as 317 and 318—in time When 5VSB is added, it is logic high. The circuit 22 will assume an active state and keep the control of the external transistor turned on until about 50 seconds at the ATX's 12 volt output (at the input 3 1 丨, 12 volt is sensed (Measured) After exceeding the gate loose value of Han Football (the standard is 〖08 volts). The characteristic of this time is necessary to ensure the stability of the output of the master Δτχ. When this time is reached, it can also maintain a smooth transition from rest to activity. When switching from quiescent to active state, the output is the initial 0 volt condition (for example, S4 / S5 to S0, EN3VDL = 1 and EN5VDL = 0 transition, or a single voltage addition program directly enters the active state), 3V DUAL and 5V The DUAL output is connected via a quasi-soft starter via an N-channel MOSFET transistor to the boosted body diode between its output and 3.3 V and 5 V ATX outputs. Figure 5 shows this explanation. When the output of the main ATX is turned on at time D0, 5VSb has appeared. Similarly, the soft-start capacitor has been charged to 125 volts and clamped for activity. Wait until the 12 volt POR timing is completed. As a result, 3 3V claws and 5V IN Ascending, the 3 DUAL and 5V DUAL output capacitors C1 & C3 are charged by their respective body diodes Q3 and Q5 (see Figure 3). At time T1, the U volt Δτχ output exceeds the circuit 2 2 H 2 volt low voltage threshold and the internal 50 millisecond (standard) timer 2 $ is started (Figure 2). At the time of T2, a soft-start is started, and the memory output rises, reaching the adjustment limit at time T3. At the same time, the memory voltage rises, the DLA output 321 is raised high (to 12 volts) to turn on 卩 3 and (^ 5), and at time T2, the 3.3V DUAL and 5V DUAL outputs are added to the adjustment value. At time T4, When the soft-start voltage reaches about 48 volts, the low-voltage monitoring circuit --------------------- Order --------- line (please read first Note on the back, please fill out this page again) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs • 12- Α7 Β7 V. Description of the invention (1) The consumption of the intelligent employees was quickly approved and the soft start capacitor was discharged to approximately 2.45 volts J: active state soft-reset the state of the fruit that is required to stop when the start is raised. Follow a new soft, move the program to enter the required power monitoring circuit and method to delay the state of a computer until ☆ force When the line is at a safe operating level, the integrated circuit only monitors the starting electricity supply and eliminates the need to monitor each supply. The voltage supply is made to connect $ volts and 3.3 volts to a starting 2 volt supply Same as the actual specification. After the 12 volt supply reaches 90% of its value, within 4 milliseconds, ATX The force supply drives 3_3 and 50% supply to reach 10% of its value. A time delay circuit 2 5 until the initial 3 · 3 and 5 volts are set to 3 · 3 and 5 volts. The supply is delayed from the standby voltage supply to the active voltage supply. Symbol description 1 0 Power supply 2 ° Power monitoring integrated circuit 22 Comparator circuit 24 Comparator 25 Timing delay circuit 2 7, 2 9 terminal '3 〇 Mother board 3 04 Control logic 3〇5 &gt; 3 0 6 ^ 3 0 7 Linear controller phase seconds nine full cut page printing I _.____- 13- This paper size applies the Zhongguanjia standard (CNS) A4 size ⑵G χ 297 public love

Claims (1)

、申請專利範圍 • 種用於對一電力供认爽夕+ 電路,該—…: '力加以監視及控制之積體 個電力牵人%…°產生多個不同之輸出電S,其每一 電路肖A 自I始&lt;電力電壓所得到,該積體 於接收由電力供給來之該多個電力輸出之裝 輸出之;制輸入之該電力輸出而產生控制之電壓電力 考作,7七:用於將代表起始電力電壓之-信號與-參 妒^力b =《裝置,其特點為包含裝置用於感測何時起 出電壓達到或超過—⑽參考位準,及裝置用 遲一=⑨力供給達到參考⑽位準後將電力輸出電壓延 埝一選足之延遲時間再連接至電腦。 2. H料利範圍第Η之積體電路,其特點為裝置用於 —電力加入之信號用於指出被監视之電力供給之所 有Μ視之輸出電壓為在或高於—可使用及有效之電壓 位丰,及用作比較之裝置包含一電壓除法器及一比較 益’其中比較器搞合至門财考電壓及電壓除法器搞合 :起始電力電壓及至比較器,及—線性控制器用於控制 電力監视電路之每一個電力輸出電壓之輸出電壓。 3·如申請專利範園第2項之積體電路,其特點為延遲裝置 $含—計時電路及比較器之輸出耦合至計時電路用於在 一被選擇之延遲時間將電力供給電壓連接至電腦。 4. 一種具有監视電力之電腦系統,包含用以產生多個不同 直流電壓之電力供應,一母板包括有記憶單元及一中央 處理單元,其中每一單元需要與其他單元不同之一運作 私壓,及一電力監視積體電路配置於電力供給與母板之 -14 - 本紙張尺度適用中國國家標準(CNS)A4規格⑵Q χ 29Γ公爱 六 、申請專利範 圍 經濟部智慧財產局員工消費合作社印製 電力供應來之電力至母板之供给,該電力 裝置,用二=接自電力供給之多個電力輸出之 之裝w用料制輸人電力輸出以產生控制電壓電力輸出 ^,用於將代表起始電力輸出電壓 ::::較之裝置,其特點爲包含裝置用以 =輸出電壓達到或超過門摇參考位準,及當:寺起 二::到參考門檻位準後用以延遲一選定之延 卞私力輸出電壓連接至電腦之裝置。 5.如::專利範圍第4項之電腦系統,其 信號用於指出被監視之電力供應 裝晋 '、’壓馬在或面於—可使用及有效之電壓位準 用於比較之裝置包含-電壓除法器及 合至起始Γ二:合至一門?參考電壓及電屢除法器 裝置包本:有z t至比較咨’用以對輸出電壓控制 出之輸出電壓之一多個之線性:: .二 第5項之電腦系統,其特點 遲二被比較器之輸出輪合至計時電路用 7姑時間將電力供给電壓連接至電腦 ^種料監視及控由·電力供應來之電力之方^ =供:產生多個不同之輸出電壓,其中每—電力 :m:起始之電力電壓,其特點爲接收:電 力輸出’控制輸入之電壓輸出而產 制“壓電力輸出’將代表起始 力 再 生 : 裝 於 該 輸 生. ----------------ί·^. (請先閱讀背面之注意事項再填寫本頁) -1 5- 297^iT 申請專利範園 一門檻參考位準, 輸出黾壓達到或超過 遲-選定之延遲時=二供給達到參考門捏位準後延 I遲時間再將電力輸 8·如申請專利範圍第9項之方法,』^壓連接至電腦。 上信號用以浐_、击γ、 ‘ '、特點爲產生一電力加 電壓爲=Τ=:=:给之所有被咖 之步驟包含將電壓除= 準’其中比較 一號與,參考 &lt;每一電力輸電壓線性控制。 凰、私路 9. dlf法’其特點爲延遲步驟包含 ““昼除〈信號超過門植參考信號時起 訂 延遲-被選擇之延遲時間將電力供给電壓連接至 線 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 16· 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱)Scope of patent application • A type of circuit for recognizing a power + circuit, which —...: 'Integrated power to be monitored and controlled is a power-intensive%… ° produces multiple different output power S, each circuit Xiao A obtained from I &lt; power voltage, the integrated device receives the plurality of power outputs from the power supply, and outputs the output voltage; the control input voltage is used to generate the control voltage power, 7-7: It is used to represent the -signal and -reference power representing the initial power voltage b = "device, which is characterized by including a device for sensing when the starting voltage reaches or exceeds the -⑽ reference level, and the device uses a delay = After the power supply reaches the reference level, the power output voltage is extended for a selected delay time and then connected to the computer. 2. The integrated circuit of the first range of H material benefits, which is characterized by the device used for-the signal of power addition is used to indicate that all output voltages of the monitored power supply are at or above-usable and effective The voltage level is high, and the device used for comparison includes a voltage divider and a comparative advantage. Among them, the comparator is connected to the door and the voltage and voltage divider are connected: the initial power voltage and the comparator, and-linear control. The device is used to control the output voltage of each power output voltage of the power monitoring circuit. 3. The integrated circuit of item 2 of the patent application park, which is characterized by a delay device. The output of the timing circuit and the comparator is coupled to the timing circuit for connecting the power supply voltage to the computer at a selected delay time. . 4. A computer system with monitoring power, including a power supply for generating a plurality of different DC voltages. A motherboard includes a memory unit and a central processing unit, each of which needs to operate differently from the other one. Voltage, and a power monitoring integrated circuit configured on the power supply and motherboard -14-This paper size applies to China National Standard (CNS) A4 specifications ⑵Q χ 29Γ Public love 6. Patent application scope Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives Print the supply of power from the power supply to the motherboard. The power device uses two = a plurality of power outputs connected to the power supply to input power output to produce a control voltage power output. Will represent the starting power output voltage :::: Compared to the device, it is characterized by including the device used to = the output voltage reaches or exceeds the door swing reference level, and when: Temple 2 :: used to reach the reference threshold level Delay a selected device that connects the private output voltage to the computer. 5. For example: The computer system in item 4 of the patent scope, whose signal is used to indicate that the monitored power supply is installed, or 'pressed or in the face of — the available and effective voltage level for comparison devices include- Voltage Divider and Combine to Start Γ Two: Combine to One? Reference voltage and electrical multiple divider device package: There is zt to comparison, which is used to control the output voltage of one or more of the output voltages. Linearity: .. 2. The computer system of item 5, whose characteristics are compared later The output wheel of the device is connected to the timing circuit. The power supply voltage is connected to the computer with 7 seconds of time. ^ Seed monitoring and control of the power from the power supply. ^ = Supply: Generates a number of different output voltages, each of which : m: the initial power voltage, which is characterized by receiving: the power output 'controls the voltage output of the input and produces the "voltage power output' which will represent the regeneration of the initial power: installed in this output. ------- --------- ί · ^. (Please read the notes on the back before filling out this page) -1 5- 297 ^ iT Patent application threshold threshold level, the output pressure reaches or exceeds the threshold -The selected delay time = the second supply reaches the reference gate pinning level, the delay time is I, and then the power is lost. 8. If the method of the scope of the patent application is No. 9, the pressure is connected to the computer. γ, '', characterized by generating an electric power plus voltage = T =: =: The steps include dividing the voltage = quasi 'which compares No. 1 with reference to <linear control of each power transmission voltage. Phoenix, private road 9. dlf method' is characterized in that the delay step includes "" Reference signal delay time-selected delay time to connect the power supply voltage to the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the consumer co-operative society 16. This paper size applies to China National Standard (CNS) A4 (210 X 297 public love)
TW089107585A 1999-04-23 2000-05-11 Accessing main ATX outputs without monitoring all outputs TW484050B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI396069B (en) * 2008-10-28 2013-05-11 Zippy Tech Corp Multi-voltage supply of power supply

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US6768222B1 (en) * 2000-07-11 2004-07-27 Advanced Micro Devices, Inc. System and method for delaying power supply power-up
JP2005327286A (en) * 2004-05-12 2005-11-24 Samsung Electronics Co Ltd Memory system for safely loading main data and main data loading method
JP5240281B2 (en) 2010-11-29 2013-07-17 オムロン株式会社 air conditioner
CN112416046A (en) * 2019-08-23 2021-02-26 半导体元件工业有限责任公司 Voltage clamping circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI396069B (en) * 2008-10-28 2013-05-11 Zippy Tech Corp Multi-voltage supply of power supply

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JP4472106B2 (en) 2010-06-02
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JP2000339068A (en) 2000-12-08

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