JP4457846B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having at least a capacitor element and a fuse element and a manufacturing method thereof.

  An active element such as a MOS (metal-oxide-semiconductor) type field effect transistor (hereinafter, this transistor is abbreviated as “MOSFET”), a capacitor element, a resistance element, a fuse element, etc. By forming passive elements and connecting these elements with wirings, a semiconductor device having a desired circuit can be obtained.

  Each circuit element is formed, for example, by placing a mask having a predetermined shape on a conductive film formed on a semiconductor substrate, and etching away a conductive film in a region not covered by the mask. However, not all circuit elements have a single layer structure, and there are various types of circuit elements having a laminated structure, so that many steps are required.

  In order to improve the productivity and reduce the manufacturing cost of a semiconductor device in which various circuit elements are integrated, it is desired to reduce the number of steps required for the manufacturing. For this reason, the number of processes is reduced by making the manufacturing processes of a plurality of types of circuit elements partially the same (common).

    For example, Patent Document 1 describes a semiconductor device in which a gate electrode for MOSFET and a fuse element are simultaneously formed in one patterning process.

    Patent Document 2 describes a semiconductor device in which a lower electrode, a fuse element, and a wiring of a capacitor element (capacitor) are formed by one conductive layer.

    Patent Document 3 describes a self-protecting decoupling capacitor in which an upper electrode of a capacitive element (capacitor) and a fuse element are formed simultaneously in one patterning process.

    Patent Document 4 describes a semiconductor integrated circuit device in which a gate electrode for MOSFET and a fuse element are simultaneously formed in one patterning process.

  Patent Document 5 describes a semiconductor device in which an upper electrode and a lower electrode of a capacitor element, a resistor element, and a gate electrode for a MOSFET are formed simultaneously in one patterning process. However, the upper electrode of the capacitor element of this semiconductor device has a two-layer structure, and a patterning step is performed once in advance as a pretreatment for obtaining an upper electrode having a two-layer structure.

    In Patent Document 6, a MOS transistor and a capacitor element are formed so as not to be separated from each other, and an upper electrode (counter electrode) or a lower electrode of the capacitor element and a resistor element or a fuse element are simultaneously formed in one patterning process. A formed semiconductor device is described.

JP-A-60-261154 JP-A-2-290078 JP-A-6-283665 Japanese Patent Laid-Open No. 7-130861 JP-A-8-274257 Japanese Patent Application Laid-Open No. 11-195753

  The capacitor element, the MOSFET, and the fuse element are a memory circuit, a trimming circuit for adjusting a voltage value or a current value, and a defect relief circuit that relieves the circuit and maintains its function even when a defect occurs in a part of the circuit. It is used in various circuits such as (so-called redundant circuit).

  The capacitive element includes a lower electrode, a capacitive insulating film, and an upper electrode, and the number of layers is at least 3 except when the semiconductor substrate is used as the lower electrode. On the other hand, the number of layers of MOSFET gate electrodes and fuse elements is at least one.

  In the case where a capacitor element constituted by at least three layers and a fuse element constituted by at least one layer are formed on a semiconductor substrate by a conventional method, only in the process of obtaining an unwired capacitor element and fuse element. It is necessary to pattern a predetermined layer using at least three types of etching masks.

  If the number of etching masks used for manufacturing a semiconductor device can be reduced, the number of processes can be reduced. It becomes easy to improve the productivity of the semiconductor device and reduce the manufacturing cost.

  An object of the present invention is to provide a capacitor element, a MOSFET, and a fuse element, and to manufacture a plurality of types of fuse elements having different cutting characteristics without changing their line widths, with a small number of processes. A semiconductor device is provided.

  An object of the present invention is to manufacture a semiconductor device including a capacitor element, a MOSFET, and a fuse element with a small number of steps even when a plurality of types of fuse elements having different cutting characteristics are formed without changing their line widths. It is to provide a method for manufacturing a semiconductor device.

According to one aspect of the present invention, there is provided a semiconductor substrate having an element isolation insulating film and a gate insulating film for a MOS field effect transistor formed on one surface, and a capacitor element formed on the element isolation insulating film. A lower electrode, a capacitor insulating film, and an upper electrode are stacked in this order on the element isolation insulating film, and the upper electrode is formed on the capacitor insulating film with the same material as the lower electrode. A capacitive element including a first upper electrode formed on the first upper electrode and a second upper electrode disposed on the first upper electrode with a material different from that of the first upper electrode, and the gate insulating film. A MOS field effect transistor having a gate electrode, wherein the gate electrode is formed of the same material as the lower electrode, and the second upper electrode is formed on the first gate electrode. Flip and a second gate electrode formed of a material, the like properly thickness of the first gate electrode within the thickness of the lower electrode, film of the thickness of the second gate electrode and the second upper electrode an equal correct MOS field effect transistor in thickness, said a base layer disposed over the insulating layer on one surface of a semiconductor substrate, a first base layer formed by the same material as the lower electrode, the and a second base layer formed by a same material as the capacitor insulating film on the first base layer, etc. properly the film thickness of the first underlayer is the thickness of the lower electrode, the second base layer and film thickness is equal correct underlayer thickness of the capacitor insulating film, a first fuse element formed on the underlying layer, the first friendly formed by the same material as the first upper electrode A molten fault, and the same material as the second upper electrode on the first soluble fault. And a second friendly fusing layers, the thickness of the first accepted fusing layer is equal properly the film thickness of the first upper electrode, the thickness of the second-friendly fusing layer of the second upper electrode semiconductor device provided with an equal correct first fuse element in thickness is provided.

  According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which at least a capacitor element, a fuse element, and a MOS field effect transistor are formed on one surface of a semiconductor substrate. An insulating film and a gate insulating film for the MOS field effect transistor are formed. The first conductive layer, the dielectric layer, and the first conductive layer covering the element isolation insulating film and the gate insulating film are made of the same material. A preparation step of preparing a semiconductor substrate in which two conductive layers are laminated in this order; and a first patterning step of etching the dielectric layer and the second conductive layer into a predetermined shape using a single etching mask. The dielectric layer in the region where the capacitive element is to be formed is left as a capacitive insulating film of the capacitive element, and the second conductive layer on the capacitive insulating film is also left, A first patterning step of removing the dielectric layer in the region where the fuse element is to be formed, covering the first conductive layer, the dielectric layer, and the second conductive layer, and Uses a metal or metal silicide to form a third conductive layer made of a metal or metal silicide, and uses the dielectric layer and the element isolation insulating film as an etching stop layer to isolate the element using a single etching mask. A second patterning step of etching each layer on the insulating film into a predetermined shape, wherein the second conductive layer on the capacitive insulating film is formed into a first upper electrode for the capacitive element, and the first upper electrode is formed The upper third conductive layer is formed into a second upper electrode for the capacitive element, the first conductive layer under the capacitive insulating film is left as the lower electrode for the capacitive element, and the first fuse is formed. The first conductive layer in a region where an element is to be formed is left as a first fusible fault for the first fuse element, and the third conductive layer on the first fusible fault is the first fusible fault. There is provided a method for manufacturing a semiconductor device including a second patterning step that remains as a second soluble fault for a fuse element.

  According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which at least a capacitor element, a fuse element, and a MOS field effect transistor are formed on one surface of a semiconductor substrate. An insulating film and a gate insulating film for the MOS field effect transistor are formed. The first conductive layer, the dielectric layer, and the first conductive layer covering the element isolation insulating film and the gate insulating film are made of the same material. A preparation step of preparing a semiconductor substrate in which two conductive layers are laminated in this order; and a first patterning step of etching the dielectric layer and the second conductive layer into a predetermined shape using a single etching mask. The dielectric layer in the region where the capacitive element is to be formed is left as a capacitive insulating film of the capacitive element, and the second conductive layer on the capacitive insulating film is also left, A first patterning step of leaving the dielectric layer in the region where the fuse element is to be formed and also leaving the second conductive layer in the region where the second fuse element is to be formed; A conductive layer forming step of covering a layer, the dielectric layer, and the second conductive layer, and forming a third conductive layer made of a metal or metal silicide, the material being different from the first conductive layer, and the dielectric layer and the A second patterning step of using the element isolation insulating film as an etching stop layer and etching each layer on the element isolation insulating film into a predetermined shape using one etching mask; A conductive layer is formed on the first upper electrode for the capacitive element, and the third conductive layer on the first upper electrode is formed on the second upper electrode for the capacitive element, and is formed under the capacitive insulating film. The first conductive layer is left as a lower electrode for the capacitor element, and the second conductive layer in a region where the second fuse element is to be formed is used as a first fusible fault for the second fuse element. And a second patterning step of forming and leaving the third conductive layer on the first soluble fault as a second soluble fault for the second fuse element.

  The upper electrode of the capacitive element has a two-layer structure of the first upper electrode and the second upper electrode thereon, and the gate electrode and the fuse element for the MOSFET are the lower electrode, the first upper electrode and the second upper electrode of the capacitive element. By forming a laminated structure of two of the three conductive layers used for forming the semiconductor device, these elements can be formed with a small number of steps, and a target semiconductor device can be manufactured with such a small number of steps. It becomes possible to do.

  In addition, a base layer is formed using two layers used for forming the lower electrode of the capacitive element and the capacitive insulating film, and the lower layer is formed using two conductive layers used for forming the upper electrode of the capacitive element. A fuse element can also be formed on the formation. By forming this fuse element, it is possible to form a plurality of types of fuse elements having different cutting characteristics without changing their line widths and without increasing the number of processes.

  In addition, the “soluble fault” in the present specification means a conductive layer that forms a fuse element and is blown (cut) when an overcurrent flows.

  In this specification, the element isolation insulating film and the gate insulating film may be collectively referred to as “an insulating film formed on one surface of a semiconductor substrate”.

  The term “same material” as used in the present specification ignores differences in the contents of inevitable contaminants such as hydrogen and carbon resulting from the film formation method, and further uses it as a donor or acceptor when obtaining an impurity semiconductor. This means that the composition of the plurality of comparative materials is the same as each other when the difference in the content of the element is ignored.

  As described above, according to the present invention, a semiconductor device including a capacitor element, a MOSFET, and a fuse element can be integrated even when a plurality of types of fuse elements having different cutting characteristics are integrated without changing their line widths. It becomes possible to manufacture with a small number of steps. It becomes easy to provide a semiconductor device including a desired circuit at low cost.

  FIG. 1 schematically shows a planar arrangement of a capacitor element 10, a first fuse element 20, a second fuse element 30, a complementary MOSFET 40, a resistance element 60, and a wiring 70 of a semiconductor device 100 according to the first embodiment.

  These circuit elements and wirings are arranged on one surface of the p-type semiconductor substrate 1, and an interlayer insulating film (not shown) is formed thereon. Upper layer wiring (not shown) is provided on the upper surface of the interlayer insulating film.

  The capacitive element 10 includes a lower electrode 12, an upper electrode 16 that is smaller than the lower electrode 12, and a capacitive insulating film (not shown) disposed between the lower electrode 12 and the upper electrode 16.

  The first fuse element 20 and the second fuse element 30 are arranged slightly apart from the capacitive element 10.

  A complementary MOSFET 40 is arranged at a distance from the first fuse element 20. The complementary MOSFET 40 includes a p-channel MOSFET 42 and an n-channel MOSFET 52. The gate electrode 47 of the p-channel MOSFET 42 and the gate electrode 57 of the n-channel MOSFET 52 are connected by a wiring 59.

  The resistance element 60 has a single-layer structure, and is disposed, for example, between the capacitive element 10 and the second fuse element 30.

  The wiring 70 has a two-layer structure, and is disposed between the first fuse element 20 and the complementary MOSFET 40.

  An interlayer insulating film (not shown in FIG. 1) covers the capacitive element 10, the first fuse element 20, the second fuse element 30, the p-channel MOSFET 42, the n-channel MOSFET 52, the resistance element 60, and the wiring 70. In this interlayer insulating film, one to a plurality of contact holes are formed in each circuit element and wiring, and contact plugs (not shown) are embedded therein. FIG. 1 illustrates 15 contact holes CH1 to CH15.

  The specific structure of each circuit element and wiring described above will be described in detail below with reference to FIG.

  FIG. 2 schematically shows a cross section of the semiconductor device 100 taken along the line II-II shown in FIG. The figure also shows an interlayer insulating film 80 (not shown in FIG. 1), upper layer wirings 91 to 97 disposed on the interlayer insulating film 80, and the like.

  As shown in FIG. 2, an element isolation insulating film 5 is formed on one surface of a p-type semiconductor substrate 1 so as to define an active region. A gate insulating film 46 is formed on the active region for the p-channel MOSFET 42, and a gate insulating film 56 is formed on the active region for the n-channel MOSFET 52. The element isolation insulating film 5, the gate insulating film 46, and the gate insulating film 56 are made of, for example, silicon oxide.

  The capacitive element 10 includes a lower electrode 12, a capacitive insulating film 14, and an upper electrode 16. The lower electrode 12 is formed on the element isolation insulating film 5 by, for example, n-type polysilicon, and a capacitive insulating film 14 is formed thereon by a dielectric layer made of silicon oxide, silicon nitride, tantalum oxide, or the like. Is done. An upper electrode 16 is disposed on the capacitive insulating film 14. The upper electrode 16 is composed of two layers, for example, a first upper electrode 16a formed on the capacitor insulating film 14 by n-type polysilicon and a second upper electrode 16b formed thereon by metal or metal silicide, for example. Is done.

  In FIG. 2, one contact hole CH1 corresponding to the lower electrode 12 and one contact hole CH2 corresponding to the upper electrode 16 are shown. Contact plugs P1 and P2 are embedded in these contact holes CH1 and CH2, respectively.

  The lower electrode 12 is electrically connected to the upper layer wiring 91 formed on the interlayer insulating film 80 by the contact plug P1 embedded in the contact hole CH1. The upper electrode 16 is electrically connected to the upper layer wiring 92 formed on the interlayer insulating film 80 by the contact plug P2 embedded in the contact hole CH2.

  The first fuse element 20 has a two-layer structure of a first soluble fault 22 formed on the element isolation insulating film 5 and a second soluble fault 24 formed thereon. The first soluble fault 22 is formed of the same material as the lower electrode 12, for example, n-type polysilicon, and the film thickness thereof is substantially equal to the film thickness of the lower electrode 12. The second soluble fault 24 is formed of the same material as the second upper electrode 16b, for example, metal or metal silicide, and the film thickness thereof is substantially equal to the film thickness of the second upper electrode 16b.

  The second fuse element 30 has a two-layer structure of a first soluble fault 32 formed on a specific underlying layer and a second soluble fault 34 formed thereon. The first soluble fault 32 is formed of the same material as the first upper electrode 16a, for example, n-type polysilicon, and the film thickness thereof is substantially equal to the film thickness of the first upper electrode 16a. The second soluble fault 34 is formed of the same material as the second upper electrode 16b, for example, metal or metal silicide, and the film thickness thereof is substantially equal to the film thickness of the second upper electrode 16b.

  The base layer of the second fuse element 30 is the same material as the lower electrode 12, for example, the first base layer 25 formed of n-type polysilicon, and the second material formed of the same material (dielectric) as the capacitor insulating film 14. It has a two-layer structure with the base layer 26. The film thickness of the first underlayer 25 is substantially equal to the film thickness of the lower electrode 12, and the film thickness of the second underlayer 26 is substantially equal to the film thickness of the capacitive insulating film 14.

  The p-channel MOSFET 42 constituting the complementary MOSFET 40 has a low concentration drain (LDD) structure. A gate electrode 47 is disposed on the gate insulating film 46. Under the gate insulating film 46, a drain region 43D, a lightly doped drain region 44a, a channel region, a lightly doped source region 44b, and a source are sequentially arranged from the n-channel MOSFET 52 side. Region 43S is arranged.

The drain region 43D and the source region 43S are each constituted by a p ⁺ -type impurity doped region formed at a predetermined location of the n-type well region 45 formed under the gate insulating film 46.

Each of the lightly doped drain region 44 a and the lightly doped source region 44 b is constituted by a p ⁻ type impurity doped region formed at a predetermined position of the n type well region 45. The junction depth of the lightly doped drain region 44a is shallower than the junction depth of the drain region 43D, and the junction depth of the lightly doped source region 44b is shallower than the junction depth of the source region 43S. The concentration of the p-type impurity in the p ⁻ type impurity added region is lower than the concentration of the p type impurity in the p ⁺ type impurity added region.

  The channel region is constituted by a region of the n-type well region 45 interposed between the low concentration drain region 44a and the low concentration source region 44b. A gate electrode 47 is located above the channel region.

  The gate electrode 47 has a two-layer structure of a first gate electrode 47a formed on the gate insulating film 46 and a second gate electrode 47b formed thereon.

  The first gate electrode 47 a is formed of the same material as the lower electrode 12, for example, n-type polysilicon, and the film thickness thereof is substantially equal to the film thickness of the lower electrode 12.

The second gate electrode 47b is formed of the same material as the second upper electrode 16b, for example, metal or metal silicide, and the film thickness thereof is substantially equal to the film thickness of the second upper electrode 16b.
On the side surface of the gate electrode 47, the sidewall spacer SW used for ion implantation for forming the drain region 43D and the source region 43S remains. The low-concentration drain region 44a and the low-concentration source region 44b described above are located below the sidewall spacer SW.

  FIG. 2 shows one contact hole CH7 corresponding to the source region 43S and one contact hole CH8 corresponding to the drain region 43D. Contact plugs P3 and P4 are buried in these contact holes CH7 and CH8, respectively.

  The source region 43S is electrically connected to the upper layer wiring 93 formed on the interlayer insulating film 80 by the contact plug P3 embedded in the contact hole CH7. The drain region 43D is electrically connected to the upper layer wiring 94 formed on the interlayer insulating film 80 by the contact plug P4 buried in the contact hole CH8.

  Similarly to the p-channel MOSFET 42, the n-channel MOSFET 52 constituting the complementary MOSFET 40 also has a low concentration drain (LDD) structure. A gate electrode 57 is disposed on the gate insulating film 56. Under the gate oxide film 56, a drain region 53D, a lightly doped drain region 54a, a channel region, a lightly doped source region 54b, and a source are sequentially formed from the p-channel MOSFET 42 side. A region 53S is arranged.

The drain region 53D and the source region 53S are each constituted by an n ⁺ -type impurity doped region formed at a predetermined position of the p-type well region 55 formed under the gate insulating film 56.

Each of the lightly doped drain region 54 a and the lightly doped source region 54 b is constituted by an n ⁻ type impurity added region formed at a predetermined position of the p type well region 55. The junction depth of the lightly doped drain region 54a is shallower than the junction depth of the drain region 53D, and the junction depth of the lightly doped source region 54b is shallower than the junction depth of the source region 53S. The n ^- type impurity concentration in the n ⁻ -type impurity doped region is lower than the n-type impurity concentration in the n ⁺ -type impurity doped region.

  The channel region is constituted by a region of the p-type well region 55 interposed between the low concentration drain region 54a and the low concentration source region 54b. A gate electrode 57 is located above the channel region.

  The gate electrode 57 has a two-layer structure of a first gate electrode 57a formed on the gate insulating film 56 and a second gate electrode 57b formed thereon.

  The first gate electrode 57 a is formed of the same material as the lower electrode 12, for example, polysilicon, and the film thickness thereof is substantially equal to the film thickness of the lower electrode 12.

  The second gate electrode 57b is formed of the same material as the second upper electrode 16b, for example, metal or metal silicide, and the film thickness thereof is substantially equal to the film thickness of the second upper electrode 16b.

  On the side surface of the gate electrode 57, the sidewall spacer SW used for ion implantation for forming the drain region 53D and the source region 53S remains. The low concentration drain region 54a and the low concentration source region 54b described above are located below the sidewall spacer SW.

  FIG. 2 shows one contact hole CH9 corresponding to the source region 53S and one contact hole CH10 corresponding to the drain region 53D. Contact plugs P5 and P6 are buried in the contact holes CH9 and CH10, respectively.

  The source region 53S is electrically connected to the upper layer wiring 95 formed on the interlayer insulating film 80 by the contact plug P5 embedded in the contact hole CH9. The drain region 53D is electrically connected to the upper layer wiring 94 formed on the interlayer insulating film 80 by the contact plug P6 embedded in the contact hole CH10. The upper layer wiring 94 electrically connects the drain region 43D and the drain region 53D.

  The resistance element 60 is formed on the element isolation insulating film 5. The resistance element 60 is formed of the same material as the lower electrode 12, for example, n-type polysilicon, and the film thickness thereof is substantially equal to the film thickness of the lower electrode 12. The upper surface of the resistance element 60 is covered with a dielectric layer 65 made of the same material as that of the capacitive insulating film 14. The film thickness of the dielectric layer 65 is substantially equal to the film thickness of the capacitive insulating film 14.

  In FIG. 2, one contact hole CH13 corresponding to the resistance element 60 is shown. A contact plug P7 is embedded in the contact hole CH13. The resistance element 60 is electrically connected to the upper layer wiring 96 formed on the interlayer insulating film 80 by the contact plug P7.

  The wiring 70 has a two-layer structure of a first wiring layer 72 formed on the element isolation insulating film 5 and a second wiring layer 74 formed thereon. The first wiring layer 72 is made of the same material as the lower electrode 12, for example, n-type polysilicon, and the second wiring layer 74 is made of the same material as the second upper electrode 16b, for example, metal or metal silicide. The film thickness of the first wiring layer 72 is substantially equal to the film thickness of the lower electrode 12, and the film thickness of the second wiring layer 74 is approximately equal to the film thickness of the second upper electrode 16b. The wiring 59 illustrated in FIG. 1 also has a stacked structure similar to the wiring 70.

  In FIG. 2, one contact hole CH15 corresponding to the wiring 70 is shown. A contact plug P8 is embedded in the contact hole CH15. The wiring 70 is electrically connected to the upper wiring 97 formed on the interlayer insulating film 80 by the contact plug P8.

  In order to ensure electrical isolation from the p-type semiconductor substrate 1 in the p-type semiconductor substrate 1 below the capacitive element 10, the first fuse element 20, the second fuse element 30, and the resistance element 60, It is preferable to form n-type well regions NW1 to NW4 as shown.

  A very small capacitance is formed between the lower electrode 12 of the capacitive element 10 and the p-type semiconductor substrate 1 using the element isolation insulating film 5 as a capacitive insulating film. By forming the n-type well region NW1 below the capacitive element 10, it is possible to prevent the charges (holes) in the p-type semiconductor substrate 1 from moving to the region below the lower electrode 12.

  Further, the n-type well region NW2 and the n-type well region NW3 are formed below the first fuse element 20 and the second fuse element 30, respectively, so that the first fuse element 20 and the second fuse element 30 are disconnected. Even if the element isolation insulating film 5 is damaged due to heat generation, it is possible to prevent unnecessary substrate leakage current from flowing.

  In forming the p-channel MOSFET 42 and the n-channel MOSFET 52 having the LDD structure, the side wall spacers SW are formed on the side surfaces of the gate electrodes 47 and 57 as described above. At this time, the side wall spacer SW is also formed on the side surfaces of the capacitor element 10, the first fuse element 20, the second fuse element 30, the resistance element 60 and the wiring 70.

  In the semiconductor device 100 having the structure described above, the constituent elements of the first fuse element 20, the second fuse element 30, the gate electrode 47, the gate electrode 57, the resistance element 60 and the wiring 70 are the lower electrode 12 of the capacitive element 10, The capacitor insulating film 14, the first upper electrode 16a, or the second upper electrode 16b are formed of the same material.

  For this reason, the capacitance element 10, the first fuse element 20, the second fuse element 30, the gate electrode 47, the gate electrode 57, the resistance element 60, and the wiring 70 can be formed by simply patterning a predetermined layer using two types of masks. It becomes possible to form. A target semiconductor device can be manufactured with a small number of steps. A specific manufacturing method will be described later.

  The line widths of the first and second fuse elements 20 and 30 are usually required to use the minimum value of the design rule. However, the layer configurations of the first and second fuse elements 20 and 30 are described above. By adopting the configuration, even if the line widths of the fuse elements 20 and 30 are made the same, the cutting characteristics can be easily made different from each other.

  For example, by making the film thickness of the first fusible fault 22 of the first fuse element 20 and the film thickness of the first fusible fault 32 of the second fuse element 30 different from each other, Even if the line width is the same, the cutting characteristics can be easily varied.

  The thickness of the first soluble fault 22 of the first fuse element 20 is 150 nm, the thickness of the first soluble fault 32 of the second fuse element 30 is 100 nm, and these soluble faults are made of polysilicon having the same composition. If formed, the current value required for cutting the first fuse element 20 is about 10 to 15% larger than the current value required for cutting the second fuse element 30. However, the line width of the first fuse element 20 and the line width of the second fuse element 30 are the same, the film thickness of the second fusible fault 24 of the first fuse element 20 and the second fusible fault of the second fuse element 30. The film thickness 34 is the same.

  It is possible to easily make a fuse element to be cut with a small current and a fuse element to be cut with a large current.

  The first fusible fault 22 of the first fuse element 20 and the first fusible fault 32 of the second fuse element 30 are formed of n-type polysilicon, and the second fusible fault 24 of the first fuse element 20 is formed. When both the second fusible faults 34 of the second fuse element 30 are formed of metal silicide, the cutting characteristics of these fuse elements 20 and 30 can be easily made different by the following method. That is, for example, in the p-type impurity introduction process for forming the source and drain regions 43S and 43D of the complementary MOSFET 40, a p-type impurity is selectively applied only to one of the first and second fuse elements 20 and 30 using a mask. Therefore, the cutting characteristics of the fuse elements 20 and 30 can be easily changed.

  By configuring the base layer of the second fuse element 30 with the first base layer 25 and the second base layer 26 described above, the second fuse element 30 can be preheated. For this purpose, the first ground layer 25 is energized. Even if the first ground layer 25 is energized, the first ground layer 25 and the second fuse element 30 are electrically separated because the second ground layer 26 is a dielectric layer.

  If the second fuse element 30 is preheated, it becomes possible to reduce the current value or voltage value required to cut the second fuse element 30. When the second fuse element 30 is cut by a pulse current, the number of pulses required for cutting can be reduced. The time required for cutting can be shortened.

  By making the size of the first underlayer 25 and the second underlayer 26 in plan view sufficiently larger than that of the second fuse element 30, heat generated when the second fuse element 30 is cut is absorbed or dissipated. Can be made. Thereby, it is possible to reduce damage to peripheral circuit elements when the second fuse element 30 is cut.

  In the case where the second gate electrodes 47b and 57b are formed of metal silicide, when the impurities are added (ion implantation) to the n-type well 45 and the p-type well 55 in the process of manufacturing the MOSFETs 42 and 52, the impurities are It becomes difficult to penetrate through the two gate electrodes 47b and 57b. It becomes easy to obtain gate electrodes 47 and 57 having desired electrical characteristics.

  When the second wiring layer 74 of the wiring 70 is formed of metal or metal silicide, the wiring 70 having a low electric resistance can be obtained. A semiconductor device 100 capable of high-speed operation can be obtained.

  Next, a method for manufacturing a semiconductor device according to the embodiment will be described with reference to FIGS. In the following description, the case where the semiconductor device 100 shown in FIGS. 1 and 2 is manufactured is taken as an example, and the reference numerals used in FIG. 2 are cited.

  3 to 6 show the main part of the manufacturing process of the semiconductor device 100. Among the constituent elements shown in these drawings, the constituent elements already shown in FIG. 2 are assigned the same reference numerals as those used in FIG.

  First, a p-type silicon substrate is prepared as the p-type semiconductor substrate 1, and the n-type well regions NW1 to NW4, the n-type well region 45, and the p-type well region 55 are formed on one surface of the p-type silicon substrate. . Each well region is formed by, for example, ion-implanting n-type impurities or p-type impurities, and then thermally diffusing and activating the impurities.

  Next, a buffer silicon oxide film having a thickness of about 50 nm is formed on the entire surface on the side where these well regions are formed. This silicon oxide film can be formed by thermal oxidation, for example.

  If necessary, a desired impurity may be added to the regions to be the channel regions of the p-channel MOSFET 42 and the n-channel MOSFET 52 before or after the silicon oxide film is formed, for example, by ion implantation. By adding this impurity, the threshold voltage of the finally obtained p-channel MOSFET 42 or n-channel MOSFET 52 can be adjusted. This impurity introduction step for adjusting the threshold voltage may be performed after formation of the gate oxide films 46 and 56 described below.

  Next, as shown in FIG. 3A, an element isolation insulating film 5 having a thickness of about 500 nm and thin gate insulating films 46 and 56 are formed on one surface of the p-type semiconductor substrate 1.

  The element isolation insulating film 5 is formed by, for example, silicon selective oxidation (LOCOS) using a mask having oxygen shielding ability. For example, a mask having a predetermined shape is formed on the buffer silicon oxide film with a silicon nitride film having a thickness of about 150 nm, and the entire p-type semiconductor substrate 1 is subjected to a high-temperature thermal oxidation process. The p-type semiconductor substrate (p-type silicon substrate) 1 in a region not covered with the mask is further oxidized to obtain an element isolation insulating film 5. Thereafter, the silicon nitride film used as the mask is removed using hot phosphoric acid or the like.

  Next, the remaining silicon oxide film with a thickness substantially corresponding to the buffer silicon oxide film is removed using, for example, diluted hydrofluoric acid, and then the entire p-type semiconductor substrate 1 is again subjected to high-temperature thermal oxidation treatment. Thereby, clean gate insulating films 46 and 56 are obtained.

The element isolation insulating film 5 can also be formed based on a method other than the method described above, for example, an STI (shallow trench isolation) method suitable for miniaturization.

  Next, as shown in FIG. 3B, a first conductive layer 111 covering the element isolation insulating film 5, the gate insulating film 46, and the gate insulating film 56 is formed. The first conductive layer 111 is formed conformally by, for example, n-type polysilicon or amorphous silicon.

  When the first conductive layer 111 is formed of n-type polysilicon, a polysilicon layer is first formed by a CVD method (chemical vapor deposition method) or the like. Next, an n-type impurity such as phosphorus is added to the entire polysilicon layer. FIG. 3B and the subsequent drawings show an example in which the first conductive layer 111 is formed of n-type polysilicon.

The polysilicon layer is formed by the CVD method, for example, using a mixed gas in which monosilane (SiH ₄ ) and nitrogen (N ₂ ) are mixed at a ratio of 2: 8 as a source gas, and the flow rate of the source gas is 20
This can be performed under the conditions of 0 sccm, growth (film formation) atmospheric pressure of 30 Pa, and substrate temperature of 600 ° C. When the substrate temperature is lowered, amorphous silicon can be formed. When this amorphous silicon is heated to about 600 ° C. or higher, polysilicon can be obtained.

The thickness of the polysilicon layer can be arbitrarily selected. In order to reduce the sheet resistance of the conductive layer 111, it is desirable that the film thickness be thick. On the other hand, the thinner one is desirable from the viewpoint of microfabrication. For this reason, it is preferably selected within the range of 50 to 1000 nm, more preferably within the range of 100 to 300 nm. The concentration of the impurity added to the polysilicon layer is, for example, about 1 × 10 ²⁰ cm ⁻³ .

  Next, as illustrated in FIG. 3C, the dielectric layer 113 is formed over the first conductive layer 111. The dielectric layer 113 is formed of, for example, a single-layer silicon oxide film or silicon oxynitride film, a stack of a silicon oxide film and a silicon nitride film or a silicon oxynitride film, or a silicon oxide film, a silicon nitride film, and a silicon oxide film. Are formed in a conformal manner. It is also possible to form the dielectric layer 113 by stacking a tantalum oxide film and a silicon oxide film or a silicon nitride film, or by stacking a tantalum oxide film sandwiched between a silicon oxide film and a silicon nitride film.

  In forming the dielectric layer 113, a phosphosilicate glass (PSG) film or a borophosphosilicate glass (BPSG) film formed by a plasma CVD method may be used instead of the silicon oxide film. A ferroelectric film may be used instead of the tantalum oxide film. A silicon oxynitride film may be used instead of the silicon nitride film.

The layer configuration of the dielectric layer 113 and the film thickness and material of each layer constituting the dielectric layer 113 can provide a desired capacitance when a pair of electrodes are formed with the dielectric layer 113 interposed therebetween. As such, it is appropriately selected. Specific examples of the layer structure of the dielectric layer 113 include the following structures (1) to (5). The layer order described in (2) to (5) below indicates the layer order from the upper surface of the dielectric layer toward the element isolation insulating film 5.
(1) Silicon oxide film
(2) Silicon nitride film / silicon oxide film
(3) Silicon oxide film or silicon oxynitride film / silicon nitride film / silicon oxide film or silicon oxynitride film
(4) Silicon oxide film or silicon oxynitride film / tantalum oxide (Ta ₂ O ₅ ) film / silicon oxide film
(5) Tantalum oxide (Ta ₂ O ₅ ) film / silicon oxide film or silicon oxynitride film The silicon oxide film includes, for example, tetraethyl orthosilicate (hereinafter abbreviated as “TEOS”) and ozone (O ₃ ). It can be formed by plasma-excited CVD using a mixed gas as a source gas, or by CVD using electron cyclotron resonance (hereinafter abbreviated as “ECR”) plasma. A silicon oxide film can also be formed by thermal oxidation or a spin-on-glass method.

The silicon nitride film or silicon oxynitride film is formed by, for example, plasma enhanced CVD using a mixed gas containing TEOS and oxygen (O ₂ ) or ozone (O ₃ ) and nitrogen oxide (NO _x ) as a source gas. Alternatively, it can be formed by CVD using ECR plasma.

  Next, as shown in FIG. 4A, a second conductive layer 115 is formed over the dielectric layer 113. The second conductive layer 115 is formed conformally by, for example, polysilicon to which an n-type impurity is added. Since an example of the method for forming the polysilicon layer has already been described in the description of the method for forming the first conductive layer 111, the description thereof is omitted here. The n-type impurity is added at the time of forming the polysilicon film, or is added by ion implantation or the like after the film formation.

When the second conductive layer 115 is formed of n-type polysilicon, the film thickness can be arbitrarily selected. In order to reduce the sheet resistance of the second conductive layer 115, it is desirable that the film thickness be thick. On the other hand, the thinner one is desirable from the viewpoint of microfabrication. For this reason, it is preferably selected within the range of 20 to 1000 nm, more preferably within the range of 80 to 300 nm. In particular, since the process of simultaneously processing the first conductive layer 111 and the second conductive layer 115 is included in the subsequent process, the film thicknesses of the first conductive layer 111 and the second conductive layer 115 are equal or several tens. It is important to be close within the% range. The concentration of n-type impurities such as phosphorus diffused in the second conductive layer 115 is, for example, about 1 × 10 ²⁰ cm ⁻³ . In order to make the workability of the first conductive layer 111 and the second conductive layer 115 the same, it is preferable that the doping concentrations are close to each other.

  If necessary, the p-type semiconductor substrate 1 may be heat treated prior to the formation of the second conductive layer 115. By this heat treatment, the dielectric layer 113 can be densified to improve its electrical and physical properties. Generation of degas and stress from the dielectric layer 113 during heat treatment performed in a process subsequent to the formation of the second conductive layer 115 is suppressed, and adhesion between the dielectric layer 113 and the second conductive layer 115 is improved. To do. The reliability of the finally obtained capacitive element 10 can be improved. In addition, re-diffusion of impurities in the first conductive layer 111 can be prevented. Further, heat treatment of the dielectric layer 113 is expected to have effects such as higher film density and disappearance of pinholes.

  The above is a preparation process for obtaining the semiconductor device 100. By patterning each layer on the substrate formed up to the second conductive layer 115 in the procedure described in detail below, the target semiconductor device 100 can be obtained with a small number of steps.

  First, as shown in FIG. 4B, an etching mask 120 having a predetermined shape is formed on the second conductive layer 115, and the second conductive layer 115 and the dielectric layer 113 therebelow are patterned by etching.

  By this patterning, the dielectric layer 113A and the second conductive layer 115A are formed on the region where the lower electrode 12 of the capacitive element 10 is to be formed, and on the region where the base layer of the second fuse element 30 is to be formed. A dielectric layer 113B and a second conductive layer 115B are formed. Further, the dielectric layer 113C and the second conductive layer 115C are formed on the region where the resistance element 60 is to be formed.

  For the etching mask 120 used at this time, for example, a photoresist such as a novolak-type photoresist is applied on the second conductive layer 115, the photoresist layer is selectively exposed and developed, and the lower part of the capacitive element 10 is developed. It is obtained by leaving a photoresist layer on the electrode 12, the base layer of the second fuse element 30, and the region where the resistance element 60 is to be formed.

  The patterning of the second conductive layer 115 and the patterning of the dielectric layer 113 are performed separately, for example. First, the second conductive layer 115 is patterned by etching.

The patterning of the second conductive layer 115 by etching is performed using, for example, a mixed gas of chlorine (Cl ₂ ) and oxygen (O ₂ ), tetrafluoromethane (CF ₄ ), or sulfur hexafluoride (SF ₆ ) as an etching gas. It can be performed by microwave plasma etching (at a microwave frequency of, for example, 2.45 GHz) or ECR plasma etching with an atmospheric pressure of several mTorr (several decipa). The second conductive layer 115 exposed without being covered with the etching mask 120 is etched and removed.

  Thereafter, the dielectric layer 113 is patterned by etching. Along with the etching of the dielectric layer 113, the surface treatment of the first conductive layer 111, which will later become part of the gate electrodes 47, 57, is performed. Therefore, in patterning the dielectric layer 113 by etching, the surface of the first conductive layer 111 can be kept clean, and the etching selectivity of the dielectric layer 113 with respect to the first conductive layer 111 is increased. It is preferred to select a method.

  For example, when the dielectric layer 113 is a laminated film having a silicon oxide film in the lower layer, the upper layer constituting the dielectric layer 113 is removed by dry etching, and the lower silicon oxide film is removed by wet etching. Is preferred.

When dry etching of the dielectric layer 113 is a silicon oxide film or a silicon nitride film, for example, tetrafluoromethane (CF ₄ ) and trifluoromethane (CHF ₃ )
Can be performed by RF plasma etching with an atmospheric pressure of 160 mTorr (about 16 × 1.333 Pa), an RF power of about 700 W, and an RF signal frequency of 13.56 MHz.

    After etching to the dielectric layer 113, the etching mask 120 is peeled off using a predetermined stripping solution.

After the dielectric layer 113 is etched, silicon oxide residues or particles remain, a damaged layer is formed on the first conductive layer due to dry etching, or a natural oxide film is formed. In this case, for the purpose of removing these, light etching is performed using, for example, buffered hydrofluoric acid (a mixture of hydrofluoric acid (HF), ammonium fluoride (NH ₄ F), and water (H ₂ O)) as an etchant. It is preferable. Thereby, peeling of the 3rd conductive layer formed next can be prevented, and a conductive fall can also be prevented.

  Next, as shown in FIG. 4C, the third conductive layer 125 is made of metal or metal silicide so as to cover the second conductive layers 115A to 115C, the dielectric layers 113A to 113C, and the first conductive layer 111. Formed by.

  When the third conductive layer 125 is formed of a metal, specific examples of the metal include refractory metals such as tungsten (W), molybdenum (Mo), titanium (Ti), and tantalum (Ta), and cobalt (Co). , Transition metals such as chromium (Cr), hafnium (Hf), iridium (Ir), niobium (Nb), platinum (Pt), zirconium (Zr), nickel (Ni), or any of these metals An alloy between metals is mentioned.

When the third conductive layer 125 is formed of metal silicide, the metal silicide may be cobalt silicide, chromium silicide, nickel silicide, or the like. In particular, nickel and cobalt can cause a silicide reaction at a relatively low temperature, and can reduce the resistance of the silicide film. Furthermore, since nickel silicide and cobalt silicide have a low melting point, the fuse element can be easily cut. The silicide film may be a refractory metal silicide film. Specific examples of the refractory metal silicide include tungsten silicide (WSi _x ), molybdenum silicide (MoSi _x ), titanium silicide (TiSi _x ), tantalum silicide (TaSi _x ), refractory metal alloy silicide, and the like. The third conductive layer 125 may be formed of a material having a resistivity lower than that of the second conductive layer 123 other than silicide.

  The thickness of the third conductive layer 125 can be arbitrarily selected. However, the thickness of the third conductive layer 125 is preferably in the range of 25 to 500 nm, and more preferably in the range of 80 to 200 nm. If the thickness is smaller than this range, the resistance of the gate electrode 40 and the wiring 70 increases. If the thickness is larger than this range, the workability in the photolithography process and the dry etching process decreases.

  Even when the third conductive layer 125 is formed of either metal or metal silicide, the third conductive layer 125 can be formed by sputtering or CVD, for example.

When the third conductive layer 125 made of tungsten silicide (WSi _x ) is formed by a DC magnetron sputtering apparatus, for example, a target made of tungsten silicide is used and the atmospheric pressure is 8 mTorr (about 8 × 1.333 × 10 ⁻¹ Pa). ), An argon (Ar) gas flow rate of 30 sccm, a substrate temperature of 180 ° C., and an input power of 2000 W are formed using an argon (Ar) gas as a sputtering gas.

  Even when the third conductive layer 125 is formed by using a metal silicide having another composition, the composition of the target to be used is the same as or similar to the composition of the target third conductive layer 125. The conditions can be selected.

In the case where the third conductive layer 125 made of tungsten silicide (WSi ₂ ) is formed by CVD, for example, tungsten hexafluoride (WF ₆ ) gas and monosilane (SiH ₄ ) gas are used as source gases, and the following WSi ₂ is deposited using the reaction represented by formula (I).

(Chemical formula 1)
WF ₆ + 2SiH ₄ → WSi ₂ + 6HF + H ₂ (I)
In the case where the first conductive layer 111 and / or the second conductive layer 115 is formed of polysilicon or amorphous silicon, the third conductive layer 125 is first formed of a desired metal, and then heat treatment is performed. The third conductive layer 125 made of metal silicide can also be formed by reacting the three conductive layers 125 with the first conductive layer 111 or the second conductive layer 115 underlying the three conductive layers 125.

When the third conductive layer 125 is formed of metal silicide, a heat treatment is performed at about 600 to 1100 ° C. for about 5 to 30 seconds depending on the composition of the third conductive layer 125, for example, a short time annealing apparatus (RTA). Device). For example, when the third conductive layer 125 is formed of tungsten silicide (WSi _x ), it is preferable to perform heat treatment at about 1000 ° C.

  By this heat treatment, the electrical resistance of the upper electrode 16 and the gate electrodes 47 and 57 of the capacitive element 10 finally obtained can be reduced. In addition, when the first conductive layer 111 and / or the second conductive layer 115 is formed of polysilicon, the heat treatment is performed so that the interlayer insulating film 80 is baked after the interlayer insulating film 80 is formed. Therefore, it is possible to prevent peeling between the third conductive layer 125 and the underlying polysilicon layer during the heat treatment performed for the purpose. The heat treatment can be performed at a desired time until the interlayer insulating film 80 is formed.

  Next, as illustrated in FIG. 5A, an etching mask 130 having a predetermined shape is formed over the third conductive layer 125, and the third conductive layer 125, the second conductive layers 115A and 115B, and the first conductive layer 111 are formed. Is patterned by etching.

  By this patterning, the capacitive element 10, the first fuse element 20, the second fuse element 30 and the underlying layer, the gate electrode 47, the gate electrode 57, the wiring 59, the resistance element 60, and the wiring 70 shown in FIG. 1 or FIG. Is obtained. The upper layer wiring is not fabricated.

  For the etching mask 130 used at this time, for example, a photoresist is applied on the third conductive layer 125, and after the photoresist layer is selectively exposed, the upper electrode 16 and the first fuse element of the capacitor element 10 are developed. 20, the second fuse element 30, the gate electrode 47, the gate electrode 57, the wiring 59, and the wiring 70 are obtained by leaving a photoresist layer on the region where the wiring 70 is to be formed.

Etching can be performed using, for example, an ECR plasma etching apparatus. The etching gas used is a mixed gas of chlorine (Cl ₂ ) and oxygen (O ₂ ), and the flow rates thereof are, for example, 25 sccm and 11 sccm. Etching conditions are, for example, an atmospheric pressure of about 2 mTorr (about 2 × 1.333 × 10 ⁻¹ Pa), an RF power of 40 W, an RF frequency of 13.56 MHz, a microwave power of 1400 W, a microwave frequency of 2.45 GHz, and an electrode temperature of 15 to 20 It can be set to ° C.

  At this time, the dielectric layers 113 </ b> A to 113 </ b> C shown in FIG. 4C are slightly thinned by etching the regions not covered with the etching mask 130, but the shape in plan view hardly changes. . These dielectric layers 113A to 113C function as an etching stop layer. The first conductive layer 111 under these dielectric layers 113A to 113C is patterned in a self-aligned manner on the dielectric layers 113A to 113C.

  After the etching is finished, the etching mask 130 is peeled off using a predetermined peeling liquid.

  Thereafter, in order to obtain the p-channel MOSFET 42 and the n-channel MOSFET 52, a predetermined impurity is added to the n-type well region 45 and the p-type well region 55 and activated.

  First, as shown in FIG. 5B, a mask 133 having an opening OP1 is formed above the p-channel MOSFET 42 region. The mask 133 includes most of the element isolation insulating film 5, the capacitor element 10, the first fuse element 20, the second fuse element 30, the gate insulating film 56, the gate electrode 57, the wiring 59, the resistance element 60, and the wiring 70. Are covered in plan view.

Next, p-type impurities (p-type ions such as boron ions) are implanted into the n-type well region 45 through the opening OP1, thereby forming p ⁻ -type low-concentration impurity-added regions 144a and 144b. The mask 133 is removed and heat treatment is performed, so that the p ⁻ type low concentration impurity doped regions 144a and 144 are formed.
The p-type impurity in b is activated.

  Next, as shown in FIG. 5C, an opening OP3 is provided above the n-channel MOSFET 52 region, and an opening OP4 is provided above the first fuse element 20, the second fuse element 30, and the wiring 70. A mask 135 is formed. The mask 135 covers most of the element isolation insulating film 5 and the capacitor element 10, the gate insulating film 46, the gate electrode 47, and the resistance element 60 in plan view.

Next, n-type impurities (n-type ions such as phosphorus ions) are implanted through the openings OP3 and OP4. N ⁻ type lightly doped regions 154 a and 154 b are formed in the p type well region 55, and n type impurities are implanted into the first fuse element 20, the second fuse element 30, and the wiring 70. The mask 135 is removed and heat treatment is performed, and the n ⁻ type low concentration impurity added regions 154 a and 154 b, the first fuse element 20 and the second fuse element 30. In addition, the n-type impurity in the wiring 70 is activated.

In the step illustrated in FIG. 5C, an opening for exposing the capacitor 10 may be formed in the mask 135. When this opening is formed, impurities are also implanted into the second conductive layer 115 constituting the upper electrode of the capacitor 10 in the ion implantation step of FIG. The total concentration of the impurity doped into the second conductive film 115 in the step of FIG. 4A and the impurity implanted in the step of FIG. 5C is 1 × 10 ²⁰ cm ^−3. That's fine. In this case, the concentration of the impurity implanted in the ion implantation step in FIG. 4A is set lower than 1 × 10 ²⁰ cm ⁻³ .

  Next, as shown in FIG. 6A, sidewall spacers SW are formed on the side surfaces of the gate electrode 47 and the side surfaces of the gate electrode 57.

  The sidewall spacer SW is formed, for example, by forming an insulating film such as silicon oxide on the entire surface and etching back the insulating film by anisotropic etching such as reactive ion etching. At the stage where the insulating film on the flat surface is removed, the insulating film as the sidewall spacer SW remains only on the side surface.

  Side wall spacers SW are also formed on the side surfaces of the capacitor element 10, the first fuse element 20, the second fuse element 30, the resistance element 60, and the wiring 70.

  Note that when the sidewall spacer SW is formed, the dielectric layer 65 on the resistance element 60 may also be etched back, but the resistance element 60 (first conductive layer 111) is formed of polysilicon. Not etched. Furthermore, by appropriately selecting the film thickness and material of the dielectric layer 65, and hence the film thickness and material of the dielectric layer 113 (see FIG. 3C), the dielectric layer 65 is used for the resistance element 60. It can function as an etching protective film. Further, when the dielectric layer 65 is a silicon nitride film, it also serves as a mask for etching the silicon oxide film.

  In addition, the gate oxide films 46 and 56 on the source regions 43S and 53S and the gate oxide films 46 and 56 on the drain regions 43D and 53D are generally removed by etch back when forming the sidewall spacer SW. However, a natural oxide film grows thereafter.

  In this specification, for the sake of convenience, a natural oxide film that has subsequently grown in a region where the gate oxide films 46 and 56 are locally removed when the sidewall spacer SW is formed, and a gate oxide film that remains without being removed at this time. 46 and 56 are also referred to as “gate oxide films 46 and 56” even after the formation of the sidewall spacer SW.

  Next, as shown in FIG. 6B, a mask 137 having an opening OP5 is formed above the p-channel MOSFET 42 region. The mask 137 may have an opening above the first fuse element 20 or the second fuse element 30 as necessary. In the illustrated example, an opening OP6 is provided above the second fuse element 30.

  The illustrated mask 137 includes most of the element isolation insulating film 5 and the capacitor element 10, the first fuse element 20, the gate insulating film 56, the gate electrode 57, the wiring 59, the resistance element 60, and the wiring 70 in plan view. cover.

Next, a p-type impurity (boron or the like) is implanted into the n-type well region 45 through the opening OP5 to form the drain region 43D and the source region 43S. Along with this, the p ⁻ type low concentration impurity doped regions 144 a and 144 b become narrow and remain only under the sidewall spacer SW formed on the side surface of the gate electrode 47. A lightly doped drain region 44a and a lightly doped source region 44b are obtained.

  At this time, p-type impurities (such as boron) are also implanted into the second fuse element 30 through the opening OP6. The electrical resistance of the second fuse element 30 increases, and the cutting characteristics thereof change. In this case, the second fuse element 30 is difficult to be cut.

  Thereafter, the mask 137 is removed and heat treatment is performed to activate the p-type impurities in the drain region 43D and the source region 43S and the p-type impurities in the second fuse element 30.

  Note that adding a p-type impurity to the second fuse element 30 is not an essential requirement for obtaining the semiconductor device 100 shown in FIG. Instead of the second fuse element 30, a p-type impurity may be added to the first fuse element 20. Further, no impurity may be added to any of the first and second fuse elements 20 and 30. When no impurity is added to any of the first and second fuse elements 20 and 30, only one opening OP5 is formed in the mask 137.

  Next, as shown in FIG. 6C, a mask 139 having an opening OP7 above the n-channel MOSFET 52 region and an opening OP8 above the first fuse element 20 and the wiring 70 is formed. The mask 139 covers most of the element isolation insulating film 5 and the capacitor element 10, the second fuse element 30, the gate insulating film 46, the gate electrode 47, and the resistance element 60 in plan view.

Next, an n-type impurity (phosphorus or the like) is implanted into the p-type well region 55, the first fuse element 20, and the wiring 70 through the openings OP7 and OP8. A drain region 53D and a source region 53S are formed in the p-type well region 55, and the n ⁻ -type low-concentration impurity-added regions 154a and 154b remain only below the sidewall spacer SW formed on the side surface of the gate electrode 57. A lightly doped drain region 54a and a lightly doped source region 54b are obtained.

  Thereafter, the mask 139 is removed and heat treatment is performed to activate the n-type impurities in the drain region 53D and the source region 53S.

  After forming the impurity doped region constituting the p-channel MOSFET 42 and the impurity doped region constituting the n-channel MOSFET 52 as described above, the interlayer insulating film 80 (see FIG. 2) is formed.

  The interlayer insulating film 80 is a relatively thick electrical insulating film, for example, a silicon oxide film having a thickness of about 300 to 1500 nm, preferably about 500 to 1000 nm, a doped silicon oxide film such as a PSG film or a BPSG film, Alternatively, it is formed by depositing these laminated films by CVD or the like.

  Next, contact holes, for example, contact holes CH1 to CH15 shown in FIG. 1 or FIG. The contact holes CH1 to CH15 are formed, for example, by forming an etching mask having a predetermined shape on the interlayer insulating film 80 and then removing the region exposed from the etching mask by etching.

  After forming a liner metal, for example, a laminated film such as Ti / TiN (TiON) in each contact hole, a conductive material such as tungsten (W), aluminum (or aluminum alloy), or copper (or copper alloy) is formed. After forming the contact plug by embedding, a metal film serving as an upper layer wiring is formed on the interlayer insulating film 80, and an etching mask having a predetermined shape is further formed thereon.

  Thereafter, the region of the metal film exposed from the etching mask is removed by etching to obtain an upper layer wiring having a desired shape. The semiconductor device 100 shown in FIG. 1 or FIG. 2 is obtained. The formation of the plug in the contact hole or the formation of the plug and the wiring may be performed using a damascene process or a dual damascene process.

  According to the manufacturing method described above, the capacitor element 10, the first fuse element 20, the second fuse element 30, and the gate electrode can be obtained simply by patterning a predetermined layer using two types of masks (etching masks 120 and 130). 47, the gate electrode 57, the resistance element 60, and the wiring 70 can be formed on the p-type semiconductor substrate 1. The semiconductor device 100 having the various advantages described above can be manufactured with a small number of steps.

  Next, a modification of the semiconductor device 100 according to the first embodiment described above will be described with reference to FIGS.

  FIG. 7A schematically shows a planar arrangement of the first fuse element 220 and the wiring 270 that are components of the semiconductor device 200 according to the first modification.

  FIG. 7B schematically shows a part of a cross section of the semiconductor device 200 taken along the line VII-VII shown in FIG.

  As shown in FIG. 7A, in the semiconductor device 200, a first fuse element 220 and a wiring 270 are provided on one side of the semiconductor substrate 1 instead of the first fuse element 20 and the wiring 70 shown in FIG. It is formed. The first fuse element 220 and the wiring 270 are arranged in series, and the three contact holes CH20, CH21, and CH22 correspond to the first fuse element 220 and the wiring 270. Other circuit configurations are the same as those of the semiconductor device 100 described above.

  As shown in FIG. 7B, the first fusible fault of the first fuse element 220 and the first wiring layer of the wiring 270 are configured by one conductive layer 210 formed on the element isolation insulating film 205. Is done. The second fusible fault of the first fuse element 220 and the second wiring layer of the wiring 270 are constituted by another conductive layer 215 formed on the first conductive layer 210.

  Note that an n-type well region (not shown) is formed below the first fuse element 220, as in the semiconductor device 100. Sidewall spacers SW are formed on the side surfaces of the first fuse element 220 and the wiring 270.

  In the semiconductor device 200 having such a structure, the conductive layer 210 is formed using the first conductive layer 111 illustrated in FIG. 4C, and the conductive layer 215 is formed using the third conductive layer 125 illustrated in FIG. Thus, like the semiconductor device 100 described above, it can be manufactured with a small number of steps.

  Three contact holes CH20 to CH22 are formed in the interlayer insulating film 80 (see FIG. 7B), and contact plugs P20, P21, and P22 are embedded in these contact holes CH20 to CH22, respectively, thereby forming the first fuse. The element 220 and the upper layer wirings 290 and 291 can be made conductive, and the wiring 270 and the upper layer wirings 291 and 292 can be made conductive.

  The area occupied by a circuit having a desired function can be reduced, and the semiconductor device 200 can be downsized accordingly.

  As shown in FIG. 7C, a notch 220a that extends inward from one edge of the first fuse element 220 may be formed. When the notch 220a is formed, current concentration occurs and the fuse element 220 is easily cut. The shape of the notch can be, for example, a wedge shape.

  Next, a semiconductor device according to a second modification will be described with reference to FIGS. 8A and 8B.

  FIG. 8A schematically shows a planar arrangement of the second fuse element 330 and the wiring 370 which are components of the semiconductor device 300 according to the second modification.

  FIG. 8B schematically shows a part of a cross section of the semiconductor device 300 taken along line VIII-VIII shown in FIG.

  As shown in FIG. 8A, in the semiconductor device 300, a second fuse element 330 and a wiring 370 are provided on one surface of the semiconductor substrate 1 instead of the second fuse element 30 and the wiring 70 shown in FIG. It is formed. The second fuse element 330 and the wiring 370 are arranged in series, and the three contact holes CH30, CH31, and CH32 correspond to the second fuse element 330 and the wiring 370. Other circuit configurations are the same as those of the semiconductor device 100 described above.

  As shown in FIG. 8B, the second fuse element 330 is formed on the insulating film 315 on the base layer 320. The first base layer constituting the base layer 320 and the first wiring layer of the wiring 370 are configured by one conductive layer 310 formed on the element isolation insulating film 305.

  A second foundation layer 315 is formed on the first foundation layer (conductive layer 310), and a first soluble fault 332 and a second soluble fault of the second fuse element 330 are stacked in this order on the second foundation layer 315. . The second soluble fault and the second wiring layer of the wiring 370 are configured by one conductive layer 334 formed from the upper surface of the first soluble fault 332 to the upper surface of the conductive film 310.

  Note that an n-type well region (not shown) is formed below the second fuse element 330, as in the semiconductor device 100. Sidewall spacers SW are formed on the side surfaces of the second fuse element 330 and the wiring 370, respectively.

  In the semiconductor device 300 having such a structure, the conductive layer 310 is formed using the first conductive layer 111 shown in FIG. 4A, and the second base layer 315 is formed using the dielectric layer 113 shown in FIG. be able to. Further, the first soluble fault 332 can be formed by the second conductive layer 115 shown in FIG. 4A, and the conductive layer 334 can be formed by the third conductive layer 125 shown in FIG. 4C.

  Similar to the semiconductor device 100 described above, the semiconductor device 300 can be manufactured with a small number of steps.

  Three contact holes CH30 to CH32 are formed in the interlayer insulating film 80 (see FIG. 8B), and contact plugs P30, P31, or P32 are embedded in these contact holes CH30 to CH32, whereby the second fuse element 330 is formed. And the upper layer wirings 390 to 391 can be conducted, and the wiring 370 and the upper layer wirings 391 to 392 can be conducted.

  The area occupied by a circuit having a desired function can be reduced, and the semiconductor device 300 can be downsized accordingly.

  A cutout similar to the cutout 220a shown in FIG. 7C may be formed in the second fuse element 330.

  Next, a semiconductor device according to a third modification will be described with reference to FIGS. 9A and 9B.

  FIG. 9A schematically shows a planar arrangement of a first fuse element 420 and a resistance element 460 that are components of a semiconductor device 400 according to the third modification.

  FIG. 9B schematically shows part of a cross section of the semiconductor device 400 taken along line IX-IX shown in FIG.

  As shown in FIG. 9A, in the semiconductor device 400, a first fuse element 420 and a resistance element 460 are formed on the semiconductor substrate 1 in place of the first fuse element 20 and the resistance element 60 shown in FIG. It is formed on one side. The first fuse element 420 and the resistance element 460 are arranged in series, and the three contact holes CH40, CH41, and CH42 correspond to the first fuse element 420 and the resistance element 460. Other circuit configurations are the same as those of the semiconductor device 100 described above.

  As shown in FIG. 9B, the first fusible fault of the first fuse element 420 and the resistance element 460 are constituted by one conductive layer 410 formed on the element isolation insulating film 405.

  The first fuse element 420 has a second soluble fault 424 formed on the conductive layer (first soluble fault) 410, and a dielectric layer 465 is disposed on the resistance element 460.

  One end of the dielectric layer 465 is positioned below the contact hole CH41, one end of the second conductive layer 415 is positioned thereon, and one end of the second soluble fault 424 is positioned thereon.

  Similar to the semiconductor device 100, an n-type well region (not shown) is formed below the first fuse element 420 and below the resistance element 460. Sidewall spacers SW are formed on the side surfaces of the first fuse element 420 and the resistance element 460, respectively.

  In the semiconductor device 400 having such a structure, the conductive layer 410 is formed using the first conductive layer 111 illustrated in FIG. 4C, and the second soluble fault 424 is formed using the third conductive layer 125 illustrated in FIG. By forming the semiconductor device 100, it can be manufactured with a small number of steps as in the semiconductor device 100 described above.

  Three contact holes CH40 to CH42 are formed in the interlayer insulating film 80 (see FIG. 9B), and contact plugs P40, P41, and P42 are embedded in these contact holes CH40 to CH42, respectively, thereby forming the first fuse. The element 420 and the upper layer wirings 490 and 491 can be conducted, and the resistance element 460 and the upper layer wiring 491 and 492 can be conducted.

  The area occupied by a circuit having a desired function can be reduced, and the semiconductor device 400 can be downsized accordingly.

  A cutout similar to the cutout 220 a shown in FIG. 7C may be formed in the first fuse element 420.

  Next, a semiconductor device according to a fourth modification will be described with reference to FIGS. 10 (A) and 10 (B).

  FIG. 10A schematically shows a planar arrangement of a second fuse element 530 and a resistance element 560 that are components of a semiconductor device 500 according to the fourth modification.

  FIG. 10B schematically shows part of a cross section of the semiconductor device 500 taken along line XX shown in FIG.

  As shown in FIG. 10A, in the semiconductor device 500, instead of the second fuse element 30 and the resistor element 60 shown in FIG. It is formed on one side. The second fuse element 530 and the resistance element 560 are arranged in series, and the three contact holes CH50, CH51, and CH52 correspond to the second fuse element 530 and the resistance element 560. Other circuit configurations are the same as those of the semiconductor device 100 described above.

  As shown in FIG. 10B, the second fuse element 530 is formed on the base layer 520. The first base layer constituting the base layer 520 and the resistance element 560 are configured by one conductive layer 510 formed on the element isolation insulating film 505.

  A second underlayer 515 is formed on the first underlayer (conductive layer 510), and a first soluble fault 532 and a second soluble fault 534 of the second fuse element 530 are stacked in this order on the second underlayer 515. The A dielectric layer 565 is disposed on the resistance element 560. The material of the dielectric layer 565 and the material of the second underlayer 515 are the same, and are formed by patterning one dielectric layer.

  Below the contact hole CH51, the first conductive layer 510, the first soluble fault 532, and the second soluble fault 534 are sequentially stacked on the element isolation insulating film 505.

  Note that an n-type well region (not shown) is formed below the second fuse element 530 and below the resistance element 560, as in the semiconductor device 100. Sidewall spacers SW are formed on the side surfaces of the second fuse element 530 and the resistance element 560, respectively.

  In the semiconductor device 500 having such a structure, the conductive layer 510 is formed using the first conductive layer 111 shown in FIG. 4A, and the second base layer 515 is formed using the dielectric layer 113 shown in FIG. be able to. 4A, the first soluble fault 532 can be formed by the second conductive layer 115, and the second soluble fault 534 can be formed by the third conductive layer 125 shown in FIG. 4C. .

  Similar to the semiconductor device 100 described above, the semiconductor device 500 can be manufactured with a small number of steps.

  Three contact holes CH50 to CH52 are formed in the interlayer insulating film 80 (see FIG. 10B), and contact plugs P50, P51, and P52 are buried in these contact holes CH50 to CH52, respectively, thereby forming the second fuse. The element 530 and the upper layer wirings 590 to 591 can be conducted, and the resistance element 560 and the upper layer wirings 591 to 592 can be conducted.

  The area occupied by a circuit having a desired function can be reduced, and the semiconductor device 500 can be downsized accordingly.

  A cutout similar to the cutout 220a shown in FIG. 7C may be formed in the second fuse element 530.

  Next, a semiconductor device according to a fifth modification will be described with reference to FIGS. 11 (A) and 11 (B).

  FIG. 11A schematically shows a planar arrangement of a capacitor element 610 and a second fuse element 630 that are components of a semiconductor device 600 according to the fifth modification.

  FIG. 11B schematically shows part of a cross section of the semiconductor device 600 taken along the line XI-XI shown in FIG.

  As shown in FIG. 11A, in the semiconductor device 600, the capacitor element 610 and the second fuse element 630 are replaced with the capacitor element 610 and the second fuse element 30 shown in FIG. It is formed on one side. The capacitive element 610 and the second fuse element 630 are arranged in series. Other circuit configurations are the same as those of the semiconductor device 100 described above.

  Three contact holes CH60, CH61, and CH62 correspond to the capacitor element 610 and the second fuse element 630. The contact hole CH60 corresponds to one end of the second fuse element 630, and the contact hole CH61 corresponds to the other end of the second fuse element 630 and the upper electrode 616 of the capacitor element 610. The contact hole CH62 corresponds to the lower electrode 612 of the capacitor 610.

  As shown in FIG. 11B, the capacitor 610 includes a lower electrode 612 formed over the element isolation insulating film 605, a capacitor insulating film 614 formed thereon, and an upper electrode formed thereon. 616. The upper electrode 616 has a two-layer structure of a first upper electrode 616a formed on the capacitor insulating film 614 and a second upper electrode 616b formed thereon.

  The second fuse element 630 includes a first soluble fault 632 formed on the base layer 620 and a second soluble fault 634 formed thereon. The first soluble fault 632 and the first upper electrode 616a of the capacitive element 610 are formed by patterning one conductive film and are continuous with each other. The second soluble fault 634 is continuous with the second upper electrode 616b of the capacitive element 610, and these are formed by patterning one conductive film.

  The foundation layer 620 includes a first foundation layer 622 formed on the element isolation insulating film 605 and a second foundation layer 624 formed thereon. The first base layer 622 and the lower electrode 612 of the capacitor 610 are formed by patterning one conductive film and are continuous with each other. The second base layer 624 is continuous with the capacitor insulating film 614 of the capacitor element 610, and these are formed by patterning one dielectric layer.

  Note that an n-type well region (not shown) is formed below the capacitor element 610 and below the second fuse element 630, as in the semiconductor device 100. Sidewall spacers SW are formed on the side surfaces of the capacitor element 610 and the second fuse element 630, respectively.

  In the semiconductor device 600 having such a structure, the lower electrode 612 and the first base layer 622 are formed by the first conductive layer 111 shown in FIG. 4A, and the capacitor is insulated by the dielectric layer 113 shown in FIG. A film 614 and a second underlayer 624 can be formed. Further, the first upper electrode 616a and the first soluble fault 632 are formed by the second conductive film 115 shown in FIG. 4A, and the second upper electrode is formed by the third conductive layer 125 shown in FIG. 4C. 616b and a second soluble fault 634 can be formed.

  Similar to the semiconductor device 100 described above, the semiconductor device 600 can be manufactured with a small number of steps.

  Three contact holes CH60 to CH62 are formed in the interlayer insulating film 80 (see FIG. 11B), and contact plugs P60, P61, and P62 are buried in these contact holes CH60 to CH62, respectively, thereby forming the second fuse. The element 630 and the upper layer wirings 690 and 691 can be electrically connected, and the capacitor element 610 and the upper layer wirings 691 and 692 can be electrically connected.

  The area occupied by a circuit having a desired function can be reduced, and the semiconductor device 600 can be downsized accordingly.

  A cutout similar to the cutout 220a shown in FIG. 7C may be formed in the second fuse element 630.

  Next, a semiconductor device according to a second embodiment will be described.

  FIG. 12A schematically shows a planar arrangement of circuit elements in the semiconductor device 700 according to the second embodiment, and FIG. 12B is along the line XII-XII shown in FIG. A cross section is shown schematically.

  The semiconductor device 700 shown in these drawings has four fuse elements and one n-channel MOSFET 52. The configuration of each circuit element is the same as that of the first fuse element 20, the second fuse element 30, or the n-channel MOSFET 52 shown in FIG.

  Of the constituent members shown in FIG. 12, members that are the same as those shown in FIG. 2 are given the same reference numerals as those used in FIG. 2, and descriptions thereof are omitted.

  However, since three of the four fuse elements have the same configuration as the second fuse element 30 shown in FIG. 2, these three fuse elements are distinguished from each other. Are given new reference numbers 30a, 30b and 30c. Further, a specific underlayer composed of a first underlayer and a second underlayer is disposed under the three fuse elements 30a to 30c, similarly to the second fuse element 30 shown in FIG. Has been. In order to distinguish these base layers from each other, new reference numerals 25a, 25b, and 25c are added to the first base layer, and new reference numerals 26a, 26b, and 26c are added to the second base layer. It is.

  The fuse element 20 is disposed on the element isolation insulating film 5. Further, the fuse element 30a is disposed on the element isolation insulating film 5 via the first base layer 25a and the second base layer 26a.

    A p-type well region 55 constituting a channel region of the n-channel MOSFET 52 extends widely to the outside in a plan view of the source region 53S, and further, a gate insulating film 56, a first underlayer 25b, and a second The fuse element 30b is disposed through the base layer 26b.

    In addition to the p-type well region 55, an n-type well region NW10 is formed in the semiconductor substrate 1, and a fuse element is formed thereon via the electrical insulating film 105, the first base layer 25c, and the second base layer 26c. 30c is arranged. The electrical insulating film 105 is formed in the same manner as the gate insulating film 46.

  An interlayer insulating film 80 covers each circuit element, and a predetermined number of upper layer wirings are disposed thereon. In the interlayer insulating film 80, a plurality of contact holes are formed in each circuit element in order to establish electrical connection between a predetermined upper layer wiring and a circuit element therebelow. A contact plug is embedded in each contact hole CH.

  FIG. 12A illustrates 20 contact holes. For the sake of convenience, these contact holes are denoted by the same reference symbol CH except for the two contact holes CH18 and CH19.

  In FIG. 12B, for convenience, each of the upper layer wirings is indicated by the same reference symbol WL, but these upper layer wirings WL are electrically separated from each other. The same applies to the contact plug P shown in FIG.

  In the illustrated semiconductor device 700, the potentials of the first ground layers 25b and 25c can be arbitrarily set, but the potential of the first ground layer 25b is set to the ground potential or the same potential as the potential of the source region 53S. Preferably, the potential of the first base layer 25c is set to the ground potential or the same potential as the potential of the n-type well region NW10.

  For example, the contact plug embedded in the contact hole CH18 shown in FIG. 12A, the contact plug embedded in the contact hole CH19 shown in FIG. 12A, and a predetermined upper layer wiring for connecting these contact plugs Thus, fuse element 30c and n-type well region NW10 are electrically connected. The potential of the first base layer 25c can be set to the same potential as that of the n-type well region NW10.

  The semiconductor device 700 having the above-described configuration also has the same technical effect as the semiconductor device 100 for the same reason as the semiconductor device 100 according to the first embodiment.

  Next, a modification of the semiconductor device 700 according to the second embodiment will be described.

  FIG. 13A schematically shows a planar arrangement of the n-channel MOSFET 52 and the fuse element 30b constituting the semiconductor device 710 according to this modification, and FIG. 13B shows the XIII shown in FIG. Fig. 4 schematically shows a cross section along line -XIII.

  In the semiconductor device 710 shown in these drawings, the drain region 53D of the n-channel MOSFET 52 is arranged on the left side of the gate electrode 57. In plan view, fuse element 30b is arranged outside drain region 53D.

  Since other configurations are the same as those of the semiconductor device 700 according to the second embodiment, the description and illustration thereof are omitted here. Of the constituent members shown in FIG. 13, members that are the same as those shown in FIG. 12 are given the same reference numerals as those used in FIG.

  In the illustrated semiconductor device 710, the first base layer 25b under the fuse element 30b is disposed below the entire length of the fuse element 30b. The second base layer 26b is disposed on the first base layer 25b except under one end of the fuse element 30b, that is, under the end corresponding to the contact hole CH5b.

  The first fusible fault 32b constituting the fuse element 30b is formed only on the second underlayer 26b. There is no first conductive layer 32 at the end corresponding to the contact hole CH5b. The second fusible fault 34b constituting the fuse element 30b is formed over the entire length of the fuse element 30b. At the end corresponding to the contact hole CH5b, the first foundation layer 25b and the second soluble fault 34b are in contact.

  The first base layer 25b and the drain region 53D are electrically connected to each other via the second soluble fault 34b, the contact plug P15 in the contact hole CH5b, the upper layer wiring WL1, and the contact plug P16 in the contact hole CH8a. The The potential of the first base layer 25b is the same as the potential of the drain region 53D.

  In FIG. 13A, nine contact holes are shown. For the sake of convenience, these contact holes are denoted by the same reference symbol CH except for the two contact holes CH5b and CH8a.

  In FIG. 13B, three upper layer wirings and four contact plugs are shown, but for convenience, each upper layer wiring except for one upper layer wiring WL1 is given the same reference symbol WL, Each contact plug except for the two contact plugs P15 and P16 is given the same reference symbol P.

  The semiconductor device 710 having the above-described configuration also has the same technical effect as that of the semiconductor device 100 for the same reason as that of the semiconductor device 100 according to the first embodiment.

  Further, even when the potential of the first base layer 25b and the potential of the drain region 53D are set to the same potential, it is possible to prevent the potential from being directly applied to the semiconductor substrate 1 due to the shadowing effect by the base layer 25b of the fuse element 30b. Can do. Further, it is possible to prevent heat generated at the time of cutting the fuse from being directly transmitted to the substrate side by the base layer 25b.

  Since the first ground layer 25b and the second fusible fault 34b of the fuse element 30b are directly connected, even when the potential of the first ground layer 25b is the same as the potential of the drain region 53D, the first ground layer 25b. Can be made smaller than that of the first base layer 25c shown in FIG. The element area combining the fuse element 30b and the underlying layer can be reduced.

  The semiconductor device according to the embodiment, the manufacturing method thereof, and the semiconductor device according to the modification have been described above, but the present invention is not limited to the embodiment and the modification.

  For example, the semiconductor substrate constituting the semiconductor device is not limited to a p-type substrate. An n-type semiconductor substrate can also be used.

  The semiconductor substrate is not limited to a silicon substrate. In addition to the silicon substrate, various semiconductor substrates having a single-layer structure or a stacked structure can be used.

  The semiconductor device only needs to include at least a capacitor element, a MOSFET, and a fuse element. The fuse element included in the semiconductor device may be, for example, only the same type of fuse element as the first fuse element 20 shown in FIG. 2, or only the same type of fuse element as the second fuse element 30 shown in FIG. It may be.

  The configuration of the circuit formed on the semiconductor substrate can be selected as appropriate according to the intended use of the semiconductor device, including the arrangement of individual circuit elements constituting the circuit. Various circuits such as a memory circuit, a trimming circuit, and a defect relief circuit can be formed.

  The first conductive layer, the second conductive layer, and the third conductive layer described in the method for manufacturing a semiconductor device are not limited to those shown in the first to fifth modifications, but various circuits including a gate electrode. It is possible to pattern the conductive layer shared between the elements.

  The conditions for forming various layers provided on a semiconductor substrate for manufacturing a semiconductor device and the etching conditions for patterning these layers are also limited to the conditions exemplified in the description of the manufacturing method according to the embodiment. It is not something.

  For example, when the lower electrode 12 of the capacitive element 10 shown in FIG. 2 and the first fusible fault 22 of the first fuse element 20 are formed of n-type polysilicon, the first gate electrode 47a of the p-channel MOSFET 42, and The first gate electrode 57a of the n-channel MOSFET 52 can be formed of p-type polysilicon as necessary. For that purpose, for example, in forming the first conductive layer 111 shown in FIG. 3B, after forming a polysilicon layer to which no impurity is added, an n-type impurity such as phosphorus is formed in a predetermined region. And p-type impurities such as boron are ion-implanted into other predetermined regions to obtain the first conductive layer 111.

  A metal silicide film can be formed above the source region and the drain region of the MOSFET, if necessary, instead of the gate insulating film described above.

  FIG. 14A and FIG. 14B show the steps for forming a metal silicide film above the source region and the drain region, respectively.

  Before performing the process shown in FIG. 14A, first, the process shown in FIG. 6C is performed, and then the mask 139 shown in FIG. 6C is removed. Further, the gate oxide films (natural oxide films) 46 and 56 formed on the source regions 43S and 53S and on the drain regions 43D and 53D, respectively, are formed using, for example, diluted hydrofluoric acid (for example, 500: 1 HF). Remove.

  Next, as shown in FIG. 14A, a metal such as titanium (Ti), nickel (Ni), cobalt (Co), tungsten (W), or these metals is formed on the entire surface of the semiconductor substrate 1 by sputtering, CVD, or the like. The metal thin film 140 is formed by depositing the above alloy.

  Since all the components shown in FIG. 14A are shown in FIG. 6C except for the metal thin film 140, the same reference numerals as those used in FIG. 6C are used for these components. Reference numerals are assigned and explanations thereof are omitted.

  The metal thin film 140 is heat-treated using a short-time annealing apparatus (RTA) or the like, so that the metal thin film 140 is silicided. The heat treatment for silicidation is performed in an inert gas atmosphere such as nitrogen gas or argon gas, and the conditions can be, for example, 650 ° C. and 10 seconds.

  The silicidation of the metal thin film 140 occurs only in the region where the silicon and the metal thin film 140 are in direct contact. That is, silicidation of the metal thin film 140 occurs on the source regions 43S and 53S and the drain regions 43D and 53D, and silicidation of the metal thin film 140 does not occur in other regions. That is, since the upper portion of the resistance element (wiring) 60 is covered with the insulating film 65 made of the dielectric layer 113, no silicide is formed on the surface, and the high resistance film remains as it is by self-alignment. It will be. Thus, when a high resistance element is required, the high resistance element can be obtained by a simpler method.

  Thereafter, the metal thin film 140 on the region where silicidation has not occurred is washed out.

  As shown in FIG. 14B, the metal silicide film 142 remains on the source regions 43S and 53S and the drain regions 43D and 53D. The metal silicide film 142 is formed in a self-aligned manner only on the source regions 43S and 53S and the drain regions 43D and 53D.

Thereafter, if necessary, the metal silicide film 142 is heat-treated using a short-time annealing device or the like. This heat treatment is performed in an inert gas atmosphere such as nitrogen gas or argon gas, and the conditions can be set at, for example, 850 ° C. and 10 seconds. This heat treatment, for example, MSi (M is. Representing a metal element forming the metal thin film 140) is MSi _2, and the improved conductivity of the metal silicide film 142.

  By providing the metal silicide film 142 in this manner, the film thickness can be arbitrarily selected and the film thickness can be easily increased, so that the electrical resistance of the MOSFET can be easily reduced.

  Simultaneously with the heat treatment for forming the metal silicide film 142 described above, the second upper electrode 16b of the capacitive element 10, the second soluble fault 24 of the first fuse element 20, the second soluble fault 34 of the second fuse element 30, and the gate The heat treatment of the second gate electrode 47b of the electrode 47, the second gate electrode 57b of the gate electrode 57, and the second conductive layer 74 can also be completed.

  FIG. 15A and FIG. 15B show steps for forming another electrode or layer simultaneously with the formation of the metal silicide film 142 shown in FIG. 14B.

  Before performing the step shown in FIG. 15A, first, the step of forming the third conductive layer 125 shown in FIG. 4C is not performed, and FIGS. 5A to 5C and FIG. The steps from (A) to FIG. 6 (C) are sequentially performed, and then the mask 139 shown in FIG. 6 (C) is removed. Further, the gate oxide films (natural oxide films) 46 and 56 formed on the source regions 43S and 53S and the drain regions 43D and 53D are removed as described above.

  Next, as shown in FIG. 15A, a metal such as titanium (Ti), nickel (Ni), cobalt (Co), tungsten (W), or the like of these metals or the like by sputtering, CVD or the like on the entire surface of the semiconductor substrate 1. An alloy is deposited to form a metal thin film 140.

  Of the components shown in FIG. 15A, all the components except for the metal thin film 140 are shown in FIG. 5A or FIG. 6C. The same reference numerals as those used in FIG. 6A or FIG.

  The metal thin film 140 is heat-treated as described above to silicidize the metal thin film 140. By this silicidation, the first upper electrode 16a, the first soluble faults 22, 32, the source regions 43S, 53S, the drain regions 43D, 53D, the first gate electrodes 47a, 57a, and the first conductive layer A metal silicide film is formed on 72. In regions other than these regions, since the silicon film is not exposed, silicidation of the metal thin film 140 does not occur.

  Thereafter, the metal thin film 140 on the region where silicidation has not occurred is washed out.

  As shown in FIG. 15B, metal silicide is formed on the first upper electrode 16a, the first soluble faults 22 and 32, the first gate electrodes 47a and 57a, and the first conductive layer 72 in a self-aligning manner. The film remains. The second upper electrode 16b, the second soluble faults 24, 34, the second gate electrodes 47b, 57b, and the second conductive layer 74 are formed.

  Further, the metal silicide film 142 remains in a self-aligning manner on the source regions 43S and 53S and the drain regions 43D and 53D.

  Thereafter, if necessary, the heat treatment described above is performed on each metal silicide film using a short time annealing apparatus or the like. The conductivity of each metal silicide film is improved.

  As an application example of this modification, the insulating film 14 around the contact hole CH1 of the capacitor lower electrode and the insulating film 65 around the contact holes CH12 and CH13 of the high resistance element are removed, and the contact portion to the capacitor lower electrode and the high resistance element The contact resistance can be lowered by forming silicide in a self-aligned manner.

  It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like other than those described above are possible.

  A resistance trimming circuit using the fuse element according to the above-described embodiment will be described with reference to FIG.

FIG. 16A illustrates a configuration example of a resistance trimming circuit. First the circuit P ₁ in which the resistance element R ₁ and the fuse element F ₁ are connected in parallel, the second circuit P ₂ and is of a resistance element R ₂ and the fuse element F ₂ are connected in parallel, mutually Connected in parallel. Each of the first circuit P ₁ and the second circuit P ₂ has the same structure as the semiconductor device according to the embodiment shown in FIG. 7 or FIG. 8, for example. The parallel circuit of the first circuit P ₁ and the second circuit P _2, the resistance element R _C are connected in series.

The combined resistance of this circuit is R _C +1 / ((1 / R ₁ ) + (1 / F ₁ ) + (1 / R ₂ ) + (1 / F ₂ )). Combined resistance obtained by cutting the fuse element _{F 1 becomes R C +1 / ((1 /} R 1) + (1 / R 2) + (1 / F 2)). The combined resistance when the _two fuse elements F ₁ and F ₂ are cut is R _C +1 / ((1 / R ₁ ) + (1 / R ₂ )).

One of the fuse elements F ₂ is being cut by the first current-voltage condition not cleaved in the second current-voltage condition, the other of the fuse element F ₁ is a also cut by the second current-voltage condition . When an electric signal having the second current-voltage condition is simultaneously applied to the fuse elements F ₁ and F ₂ , only the fuse element F ₁ can be cut. When applied simultaneously electric signals of the first current-voltage condition to the fuse element F ₁ and F _2, it is possible to cut both the fuse element F ₁ and F _2. In this manner, only _one fuse element F ₁ is selected by appropriately selecting the current voltage condition to be applied without providing a fuse selection circuit for selectively applying a cutting signal to one of the two fuse elements. Can be cut, or both fuse elements F ₁ and F ₂ can be cut. As described above, three types of combined resistors can be realized depending on the cut state of the fuse element.

FIG. 16B shows another resistance trimming circuit. The first circuit S ₁ in which the resistor element R ₁ and the fuse element F ₁ are connected in series, the second circuit S ₂ in which the resistor element R ₂ and the fuse element F ₂ are connected in series, and the resistor element R _C2 is connected in parallel. A resistance element _RC1 is connected in series to this parallel circuit.

FIG. 16C shows still another trimming circuit. First circuit P ₁ and the resistance element R ₁ and the fuse element F ₁ are connected in _parallel, the resistance element R ₂ and the fuse element F ₂ second to and are connected in parallel in the circuit P _2, and another A resistance element _RC is connected in series.

  In the resistance trimming circuit shown in FIGS. 16B and 16C, as well as the circuit shown in FIG. 16A, the voltage / current condition of the cutting signal applied to the fuse element is appropriately selected. Thus, three types of combined resistance can be realized.

  With reference to FIG. 17, a capacitor trimming circuit using the fuse element according to the above-described embodiment will be described.

FIG. 17A illustrates a configuration example of the capacitor trimming circuit. First circuit P _1, the capacitor C ₂ and the second circuit P ₂ in which the fuse element F ₂ are connected in _parallel, and another capacitor C and the capacitor C ₁ and the fuse element F ₁ are connected in parallel _C is connected in series. Each of the first circuit P1 and the second circuit P2 has the same structure as that of the semiconductor device according to the embodiment shown in FIG. 11, for example.

When the fuse elements F ₁ and F ₂ are not cut, the combined capacitance is C _C. When the fuse element _{F 1,} combined capacitance will _{1 / ((1 / C C} ) + (1 / C 1)). When both the fuse elements F ₁ and F ₂ are cut, the combined capacitance becomes 1 / ((1 / C _C ) + (1 / C ₁ ) + (1 / C ₂ )). In this way, three types of combined capacity can be realized.

FIG. 17B illustrates another configuration example of the capacitor trimming circuit. A circuit in which the capacitor C ₁ and the fuse element F ₁ are connected in series and the capacitor C _C1 are connected in parallel to form a _first circuit P ₁ . A capacitor C ₂ and the fuse element F ₂ constitutes a circuit connected in series, the second circuit P ₂ and the capacitor C _C2 is connected in parallel. First circuit P ₁ and the second circuit P ₂ are connected in series. Each of the series circuit of the capacitor C ₁ and the fuse element F ₁ and the series circuit of the capacitor C ₂ and the fuse element F ₂ have the same structure as the semiconductor device shown in FIG. 8, for example. Also in this configuration example, three types of combined capacitors can be realized.

FIG. 17C illustrates still another configuration example of the capacitor trimming circuit. A capacitor C ₁ and the fuse element F ₁ constitutes a first circuit P ₁ are connected in parallel. A capacitor C ₂ and the fuse element F ₂ constitutes a circuit connected in series, the second of the another capacitor C _C is connected in parallel circuit P _2. First circuit P ₁ and the second circuit P ₂ are connected in series. Each of the parallel circuit composed of the capacitor C ₁ and the fuse element F ₁ and the series circuit composed of the capacitor C ₂ and the fuse element F ₂ have the same structure as the semiconductor device shown in FIG. 11, for example. Synthesis capacity and the fuse element F ₂ is reduced, further cutting the fuse element F _1, combined capacitance becomes smaller. Also in this configuration example, three types of combined capacitors can be realized.

  18A and 18B show a trimming circuit in which the resistor trimming circuit in FIG. 16C and the capacitor trimming circuit in FIG. 17A are connected in parallel and a trimming circuit in series. . As described above, it is possible to variously combine the resistance trimming circuit and the capacitor trimming circuit.

  If the fuse selection circuit is formed on the integrated circuit, the fuse selection circuit is used in combination with the method of selectively cutting the fuse element according to the difference in the cutting conditions, and a complicated structure using a multi-stage resistor and fuse element is used. A trimming circuit can also be formed.

It is the schematic which shows the plane arrangement | positioning of the capacitive element of the semiconductor device by an Example, a 1st fuse element, a 2nd fuse element, a complementary MOSFET, a resistive element, and wiring. It is the schematic of a cross section when the semiconductor device shown in FIG. 1 is cut along the II-II line shown in the figure. FIG. 3 is a cross sectional view schematically showing a part of the manufacturing process for the semiconductor device shown in FIGS. 1 and 2. FIG. 5 is a cross sectional view schematically showing another portion of the manufacturing process of the semiconductor device shown in FIGS. 1 and 2. FIG. 5 is a cross sectional view schematically showing still another portion of the manufacturing process of the semiconductor device shown in FIGS. 1 and 2. FIG. 5 is a cross sectional view schematically showing still another portion of the manufacturing process of the semiconductor device shown in FIGS. 1 and 2. FIG. 7A is a schematic diagram showing a planar arrangement of the first fuse element and the wiring of the semiconductor device according to the first modification of the first embodiment, and FIG. FIG. 7C is a schematic view showing a part of a cross section of the semiconductor device shown in FIG. 7 taken along the line VII-VII shown in FIG. It is the schematic which shows a part of cross section of the made semiconductor device. FIG. 8A is a schematic diagram showing a planar arrangement of the second fuse element and the wiring of the semiconductor device according to the second modification of the first embodiment, and FIG. 1 is a schematic view showing a part of a cross section when the semiconductor device shown in FIG. 2 is cut along the line VIII-VIII shown in FIG. FIG. 9A is a schematic diagram showing a planar arrangement of the first fuse element and the resistance element of the semiconductor device according to the third modification of the first embodiment, and FIG. It is the schematic which shows a part of cross section when the semiconductor device shown to A) is cut along the IX-IX line shown to the same figure. FIG. 10A is a schematic diagram showing a planar arrangement of the second fuse element and the resistance element of the semiconductor device according to the fourth modification of the first embodiment, and FIG. It is the schematic which shows a part of cross section when the semiconductor device shown to A) is cut along the XX line shown to the same figure. FIG. 11A is a schematic diagram showing a planar arrangement of a capacitor element and a second fuse element of a semiconductor device according to a fifth modification of the first embodiment, and FIG. It is the schematic which shows a part of cross section when the semiconductor device shown to A) is cut along the XI-XI line shown to the same figure. FIG. 12A is a schematic diagram showing a planar arrangement of circuit elements in the semiconductor device according to the second embodiment, and FIG. 12B is along the line XII-XII shown in FIG. It is the schematic of a cross section. FIG. 13A is a schematic diagram showing a planar arrangement of a p-channel MOSFET and a fuse element in a modification of the semiconductor device according to the second embodiment, and FIG. 13B is shown in FIG. It is the schematic of the cross section along line XIII-XIII. FIG. 14A is a cross-sectional view schematically showing a part of a process for forming a metal silicide film on a source region and a drain region of a MOSFET, and FIG. 14B is a source region of the MOSFET. It is sectional drawing which shows schematically another part of process at the time of forming a metal silicide film | membrane on an upper region and a drain region. FIG. 15A is a cross-sectional view schematically showing a part of a process for forming other electrodes or layers together when forming a metal silicide film on the source region and the drain region of the MOSFET. FIG. 15B is a cross-sectional view schematically showing another part of the step of forming other electrodes or layers together when forming the metal silicide film on the source region and the drain region of the MOSFET. FIG. FIG. 6 is an equivalent circuit diagram showing a configuration example of a resistance trimming circuit using the semiconductor device according to the embodiment. It is an equivalent circuit diagram which shows the other structural example of the resistance trimming circuit using the semiconductor device by the said Example. It is an equivalent circuit diagram which shows the other structural example of the resistance trimming circuit using the semiconductor device by the said Example. FIG. 6 is an equivalent circuit diagram showing a configuration example of a capacitor trimming circuit using the semiconductor device according to the embodiment. FIG. 6 is an equivalent circuit diagram showing another configuration example of the capacitor trimming circuit using the semiconductor device according to the embodiment. FIG. 6 is an equivalent circuit diagram showing another configuration example of the capacitor trimming circuit using the semiconductor device according to the embodiment. FIG. 6 is an equivalent circuit diagram illustrating a configuration example of a resistor and capacitor trimming circuit. FIG. 6 is an equivalent circuit diagram illustrating another configuration example of a resistor and capacitor trimming circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 5 ... Element isolation insulating film, 10 ... Capacitor element, 12 ... Lower electrode of capacitive element, 14 ... Capacitor insulating film, 16 ... Upper electrode, 16a ... 1st upper electrode, 16b ... 2nd upper electrode, DESCRIPTION OF SYMBOLS 20 ... 1st fuse element, 22 ... 1st soluble fault of 1st fuse element, 24 ... 2nd soluble fault of 1st fuse element, 25 ... 1st ground layer, 26 ... 2nd ground layer, 30 ... 1st 2 fuse elements, 32 ... first fusible fault of the second fuse element, 34 ... second fusible fault of the second fuse element, 40 ... complementary MOSFET, 42 ... p-channel MOSFET, 46, 56 ... gate insulating film, 47, 57 ... gate electrodes, 47a, 57a ... first
Gate electrode, 47b, 57b ... second gate electrode, 52 ... n-channel MOSFET, 60 ... resistance element 70 ... wiring, 100, 700 ... semiconductor device, 111 ... first conductive film,
113 ... Dielectric layer, 115 ... Second conductive film, 120, 130 ... Etching mask, 125 ... Third conductive film.

Claims (8)

A semiconductor substrate having an element isolation insulating film and a gate insulating film for a MOS field effect transistor formed on one surface;
The capacitive element formed on the element isolation insulating film has a layer configuration in which a lower electrode, a capacitive insulating film, and an upper electrode are stacked in this order on the element isolation insulating film, and the upper electrode A first upper electrode formed on the capacitive insulating film by the same material as the lower electrode, and a second upper electrode disposed on the first upper electrode by a material different from the first upper electrode. A capacitive element,
A MOS field effect transistor having a gate electrode formed on the gate insulating film, wherein the gate electrode is formed of the same material as the lower electrode, and the first gate electrode is formed on the first gate electrode. and a second gate electrode formed of the same material as the second upper electrode, etc. properly in the thickness of each of said first gate electrode is the lower electrode, the film thickness of the second gate electrode and the a MOS field effect transistor equal correct the thickness of the second upper electrode,
A base layer disposed on one surface of the semiconductor substrate via an insulating film, the first base layer formed of the same material as the lower electrode; and the capacitive insulating film on the first base layer; and a second base layer formed from the same material, the thickness of the film thickness of the first underlayer is equal properly the film thickness of the lower electrode, the film thickness of the second base layer is the capacitor insulating film and etc. correct the underlying layer,
A first fuse element formed on the underlayer, the first fusible fault formed of the same material as the first upper electrode, and the second upper electrode on the first soluble fault. and a second friendly fusing layer formed by the same material, the thickness of the first accepted fusing layer is equal properly the film thickness of the first upper electrode, the film thickness of the second-friendly blowing layer wherein the semiconductor device provided with an equal correct first fuse element to the thickness of the second upper electrode. Further, a second fuse element formed on the element isolation insulating film, the third fusible fault formed of the same material as the lower electrode, and the second upper part on the third soluble fault and a fourth friendly fusing layer formed by the same material as the electrode, the third friendly film thickness of the fusing layer is equal properly the film thickness of the lower electrode, the film thickness of the fourth-friendly blowing layer wherein the the semiconductor device according to claim 1 having an equal correct the second fuse elements in the film thickness of the second upper electrode. 3. The semiconductor device according to claim 1, wherein the lower electrode and the first upper electrode are made of polysilicon, and the second upper electrode is made of metal or metal silicide. A method of manufacturing a semiconductor device in which at least a capacitor element, a fuse element, and a MOS field effect transistor are formed on one surface of a semiconductor substrate,
An element isolation insulating film and a gate insulating film for the MOS field effect transistor are formed on one surface, and a first conductive layer, a dielectric layer, and the first conductive layer covering the element isolation insulating film and the gate insulating film are formed. A preparation step of preparing a semiconductor substrate in which second conductive layers made of the same material as the layers are stacked in this order;
A first patterning step of etching the dielectric layer and the second conductive layer into a predetermined shape using one etching mask, wherein the dielectric layer in a region where the capacitive element is to be formed is A first patterning step of leaving the dielectric layer in the region where the first fuse element is to be formed, leaving the second insulating layer on the capacitive insulating film as well as leaving the capacitor insulating film of the element;
A conductive layer forming step of covering the first conductive layer, the dielectric layer, and the second conductive layer, and forming a third conductive layer made of a metal or metal silicide that is made of a different material from the first conductive layer;
A second patterning step of using the dielectric layer and the element isolation insulating film as an etching stop layer and etching each layer on the element isolation insulating film into a predetermined shape using one etching mask, Forming the second conductive layer on the film as a first upper electrode for the capacitive element, and forming the third conductive layer on the first upper electrode as a second upper electrode for the capacitive element; The first conductive layer under the capacitor insulating film is left as a lower electrode for the capacitor element, and the first conductive layer in the region where the first fuse element is to be formed is used for the first fuse element. with left as 1 Allowed blown layer, viewed contains a second patterning step of leaving said third conductive layer on the first friendly blowing layer as the second-friendly fusing layer for said first fuse element,
In the first patterning step, the dielectric layer is left in a region where the second fuse element is to be formed, and the second conductive layer is also formed in the region where the second fuse element is to be formed. Leave,
In the second patterning step, the second conductive layer is left in the region where the second fuse element is to be formed by using the dielectric layer as an etching stop layer. And forming the third conductive layer on the first soluble fault into a second soluble fault for the second fuse element . The method of manufacturing a semiconductor device according to claim 4 , wherein the first conductive layer and the second conductive layer are formed of polysilicon. A method of manufacturing a semiconductor device in which at least a capacitor element, a fuse element, and a MOS field effect transistor are formed on one surface of a semiconductor substrate,
An element isolation insulating film and a gate insulating film for the MOS field effect transistor are formed on one surface, and a first conductive layer, a dielectric layer, and the first conductive layer covering the element isolation insulating film and the gate insulating film are formed. A preparation step of preparing a semiconductor substrate in which second conductive layers made of the same material as the layers are stacked in this order;
A first patterning step of etching the dielectric layer and the second conductive layer into a predetermined shape using one etching mask, wherein the dielectric layer in a region where the capacitive element is to be formed is In addition to leaving the capacitor insulating film of the element, the second conductive layer on the capacitor insulating film is also left, leaving the dielectric layer in the region where the second fuse element is to be formed, and the second fuse element A first patterning step that also leaves the second conductive layer in the region to be formed;
A conductive layer forming step of covering the first conductive layer, the dielectric layer, and the second conductive layer, and forming a third conductive layer made of a metal or metal silicide that is made of a different material from the first conductive layer;
A second patterning step of using the dielectric layer and the element isolation insulating film as an etching stop layer and etching each layer on the element isolation insulating film into a predetermined shape using one etching mask, Forming the second conductive layer on the film as a first upper electrode for the capacitive element, and forming the third conductive layer on the first upper electrode as a second upper electrode for the capacitive element; The first conductive layer under the capacitor insulating film is left as a lower electrode for the capacitor element, and the second conductive layer in a region where the second fuse element is to be formed is used as the second fuse element second electrode. A second patterning step of forming a first soluble fault and leaving the third conductive layer on the first soluble fault as a second soluble fault for the second fuse element. . In the first patterning step, the second conductive layer and the dielectric layer in a region where the first fuse element is to be formed are removed,
In the second patterning step, the first conductive layer in a region where the first fuse element is to be formed is left as a first soluble fault for the first fuse element, and the first possible fault is The method of manufacturing a semiconductor device according to claim 6 , wherein the third conductive layer on the molten fault is left as a second soluble fault for the first fuse element. The method of manufacturing a semiconductor device according to claim 6, wherein the first conductive layer and the second conductive layer are formed of polysilicon.

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