JPH1154700A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a capacitance element having a less voltage-dependent capacitance, by arranging a lower electrode on part of an insulating area formed on the surface of a substrate, and successively forming a dielectric layer and an upper electrode on the lower electrode. SOLUTION: A semiconductor layer 61 is provided on a substrate 60 having an insulating surface, and a lower electrode in which a high-concentration area 61a containing an impurity at a high concentration and a low-concentration area 61b containing the impurity at a low concentration are demarcated is formed in the semiconductor layer 61. Then, a dielectric layer 62 composed of a dielectric material is formed on the lower electrode, and an upper electrode 63 which contains the impurity at a concentration which is intermediate between the impurity concentrations in the areas 61b and 61a is formed on the layer 62. Therefore, a capacitance element having a less voltage-dependent capacitance can be manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a digital / analog integrated circuit device, for example, a MOSFET, a capacitor, and a resistor are formed on one chip. When the gate electrode of the MOSFET, the lower electrode of the capacitor, and the resistor are formed of the same polysilicon layer, an increase in the number of manufacturing steps can be prevented.

In this case, in order to lower the resistance of the gate electrode, the impurity concentration of the portion of the polysilicon layer which will become the gate electrode is increased. Further, the impurity concentration of a portion to be a high-resistance element is reduced. Normally, the lower electrode of the capacitor has one of these impurity concentrations.

When the impurity concentration of the lower electrode is high, it is preferable to lower the impurity concentration of the upper electrode in order to reduce the leakage current of the capacitor. However, when the difference between the impurity concentrations of the upper and lower electrodes increases, the voltage dependency of the capacitance increases.

When the impurity concentration of the lower electrode is low,
Even if the impurity concentration of the upper electrode and that of the lower electrode are equal, the voltage dependence proportional to the square of the voltage remains theoretically, and the dependence increases as the impurity concentration decreases.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a technique for forming a capacitive element with low voltage dependence on a supporting substrate.

[0007]

According to one aspect of the present invention, there is provided a substrate having an insulating region defined on a part of a surface thereof, a semiconductor device disposed on a part of the insulating region on the substrate surface, A lower electrode formed of a material and including a low-concentration region and a high-concentration region having mutually different impurity concentrations; a dielectric layer formed of a dielectric material formed on the lower electrode; Formed at an intermediate impurity concentration between the impurity concentration of the low concentration region and the impurity concentration of the high concentration region of the lower electrode, facing the low concentration region and the high concentration region of the lower electrode, There is provided a semiconductor device having a body layer and an upper electrode constituting a capacitor.

The capacitance of this capacitor is such that a first capacitor composed of a low-concentration region and an upper electrode and a second capacitor composed of a high-concentration region and an upper electrode are connected in parallel. It is the same as the combined capacity in the case. The impurity concentration of the upper electrode is set to an intermediate value between the impurity concentrations of the low concentration region and the high concentration region. For this reason, the capacitances of the first and second capacitance elements have mutually opposite voltage dependencies. This 2
When two capacitive elements are connected in parallel, the voltage dependence of the capacitance cancels each other out.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference to FIG. 1, a description will be given of a basic configuration and an operation principle of a capacitive element according to an embodiment of the present invention.

FIG. 1A is a sectional view showing a basic configuration of a capacitor according to an embodiment of the present invention. On a substrate 60 having an insulating surface, a semiconductor layer 61, a dielectric layer 62, and a semiconductor layer 63 are stacked in this order. Semiconductor layer 61
Defines a high concentration region 61a having a high impurity concentration and a low concentration region 61b having a low impurity concentration. The capacitive element is equal to the combined capacitance when connecting the capacitance elements constituted C _b in parallel by the capacitance elements constituted C _a lightly doped region 61b and the upper electrode 63 by the high concentration region 61a and the upper electrode 63 With a capacitance of

In general, the capacitance of a capacitor using a semiconductor layer as two electrodes sandwiching an insulating layer depends on the voltage applied between the two electrodes. The voltage dependency of capacitance is characterized by a difference in impurity concentration of a semiconductor layer serving as an electrode.

FIG. 1B shows the voltage dependence of the capacitance of three capacitive elements having different impurity concentration differences between two semiconductor layers. The horizontal axis represents the voltage applied between the electrodes in units of V,
The vertical axis represents the rate of change of the capacitance with reference to no voltage application. The direction in which the upper electrode has a higher potential than the lower electrode is defined as a positive voltage.

The sample used for the evaluation is a capacitor in which the lower electrode and the upper electrode are formed of phosphorus (P) -doped polysilicon, and the insulating layer is formed of a 50 nm-thick SiO ₂ film.
The dose of the impurity in the lower electrode is 1 × 10 ¹⁵ cm ^−2.
Thus, three types of samples in which the doses of impurities of the upper electrode were different from each other were produced. Curves c ₁ , c ₂ and c in the figure
₃ means that the impurity dose of the upper electrode is 5 × 10 ¹⁴
The capacitance variation rates of samples of cm ⁻² , 1 × 10 ¹⁵ cm ⁻² , and 5 × 10 ¹⁵ cm ⁻² are shown.

As shown by the curve c ₂ , when the impurity concentration of the upper electrode is equal to that of the lower electrode, the rate of change of the capacitance decreases. When the impurity concentration of the upper electrode is lower than the impurity concentration of the lower electrode and vice versa, the rate of change of the capacitance has negative and positive slopes, respectively.

In the capacitive element shown in FIG. 1A, if the impurity concentration of the upper electrode 63 is set to an intermediate value between the impurity concentration of the high concentration region 61a and the impurity concentration of the low concentration region 61b, voltage dependence of the capacitance of the capacitor C _a and C _b exhibits a characteristic opposite to each other. For this reason, the voltage dependences of the two cancel each other out, and the voltage dependence of the combined capacitance of the two is reduced.

[0016] If the absolute value of the inclination of the capacitance change rate of the capacitance element C _a and C _b are different from each other, the high concentration region 61
The voltage dependency can be optimized by adjusting the area ratio of the low concentration region 61b to the low concentration region 61b. For example, the absolute value of the slope of the capacitance variation rate of the capacitor C _a is the case is that of n times the capacitance element C _b is the area of the capacitor C _a in the area of the capacitor C _b 1 / n times.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a plan view showing the configuration of the analog MOS integrated circuit device according to the embodiment. FIG. 2 shows a capacitance element C and resistance elements R ₁ and R formed on a semiconductor substrate 100.
₂ and the MOSFET 50 are illustrated. The capacitance element C includes a lower electrode L ₁ and an upper electrode L ₂ ,
Lower electrodes L ₁ is composed of a low-concentration region L ₁₁ impurity high concentration region L _12. The MOSFET 50 includes an active region A and a gate electrode G crossing the active region A.

FIGS. 3 to 13 are views for explaining a method of manufacturing the integrated circuit device shown in FIG. 2, and correspond to the cross-sectional views taken along dashed line II in FIG. Hereinafter, each manufacturing process according to the present embodiment will be described with reference to FIGS.

A semiconductor substrate 100 made of silicon shown in FIG. 3 is prepared. As shown in FIG.
A gate oxide film 4 having a predetermined thickness is formed on the surface of the substrate. Next, a mask pattern (not shown) made of a SiN film or the like is formed on the gate oxide film 4. Using this mask pattern as a mask, the surface layer of semiconductor substrate 100 is selectively thermally oxidized to form field oxide film 3. No oxide film is formed in the area covered by the mask pattern,
An active region in which only the thin gate oxide film 4 is formed is obtained. After the formation of the field oxide film 3, the mask pattern is removed. FIG. 5 shows a state after the mask pattern is removed. Note that the gate oxide film 4 may be formed after the field oxide film 3 is formed.

As shown in FIG. 6, a polysilicon layer 2 having a thickness of about 150 nm is deposited on the entire surface of the substrate by chemical vapor deposition (CVD). The source gases used for growing the polysilicon layer 2 are SiH ₄ (20%) and N ₂ (80
%), The flow rate is 200 sccm, the pressure during growth is 30 Pa, and the substrate temperature is 600 ° C. When the substrate temperature is significantly lower than the above temperature, amorphous silicon grows instead of polysilicon. In this case, when the substrate temperature is heated to the above temperature or higher, the amorphous silicon is crystallized to be polysilicon.

The polysilicon layer 2 has a dose of 1 × 10 ¹⁵
Phosphorus (P) ions are implanted under the conditions of cm ⁻² and an acceleration energy of 15 keV.

As shown in FIG. 7, resist patterns 2A and 2B are formed on the polysilicon layer 2. The resist patterns 2A and 2B correspond to the low concentration regions L in FIG.
₁₁ and the resistance element covers a region R ₂ is formed. Using resist patterns 2A and 2B as a mask, dose amount 7 × 1
P ions are implanted into the polysilicon layer 2 under the conditions of 0 ¹⁵ cm ^-2 and an acceleration energy of ¹⁵ keV. The impurity concentration of the region of the polysilicon layer 2 covered with the resist patterns 2A and 2B becomes lower than the impurity concentration of the other regions,
The low-density regions 2a and 2b are respectively defined in the region.

As shown in FIG. 8, a dielectric film 1 used as a capacitor film is conformally deposited on the surface of the polysilicon layer 2. The dielectric film 1 may be composed of a single layer of a silicon oxide film, a laminated structure of a silicon oxide film and a silicon nitride film, or a laminated structure of a tantalum oxide film and a silicon oxide film.

The dielectric film 1 may have a three-layer structure in which a silicon nitride film is interposed between two silicon oxide films. A silicon oxynitride film may be used instead of the silicon nitride film.

For example, a silicon oxide film is formed by plasma-excited CVD using a mixed gas containing tetraethylorthosilicate (TEOS) and ozone (O ₃ ) as a source gas.
Or by electron cyclotron resonance (EC
R) It is formed by CVD using plasma.

Further, a silicon oxide film is formed on a phosphosilicate glass (PS) formed by plasma-excited CVD.
G) Film or borophosphosilicate glass (BPS)
G) It may be a film. Further, the silicon oxide film may be formed by thermal oxidation of the polysilicon film, or may be formed by a spin-on-glass (SOG) method. The material and thickness of the dielectric film are selected so as to obtain a suitable capacitance with the dielectric film interposed therebetween. For example, a TEOS film having a thickness of 50 nm is used.

On the dielectric film 1, a thickness of 100 is formed by CVD.
A second polysilicon layer 6a of nm is deposited. The polysilicon layer 6a is deposited, for example, by mixing SiH ₄ and N ₂ in a ratio of 2: 8.
Using a gas mixed at a pressure of 30 Pa and a flow rate of 20
The process is performed under the conditions of 0 sccm and a substrate temperature of 600 ° C.

On the second polysilicon layer 6a, under the conditions of a dose of 5 × 10 ¹⁵ cm ⁻² and an acceleration energy of ¹⁵ keV,
P ions are implanted. That is, the impurity concentration of the polysilicon layer 6a is lower than that of the low concentration regions 2a, 2a of the polysilicon layer 2.
It is higher than the impurity concentration of b and lower than the impurity concentrations of other high concentration regions. Note that P may be added by depositing POCl ₃ on the polysilicon layer 6a and performing a heat treatment at 860 ° C. for 20 minutes.

Heat treatment may be performed before depositing the second polysilicon layer 6a. By this heat treatment, the reliability of the finally formed capacitive element C can be improved. This is because the electrical and physical properties of the dielectric film 1 are improved by the densification of the dielectric film 1, and degassing and stress changes from the dielectric film 1 during heat treatment before and after the deposition of the polysilicon layer 6a. This is considered to be due to the fact that the polysilicon layer 6a is hardly peeled off. In particular, the adhesion between the polysilicon layer 6a and the dielectric film 1 becomes stronger. Re-diffusion of impurities in the polysilicon layer 2 can also be prevented.

Resist patterns 5a, 5b and 5c are formed on polysilicon layer 6a. Resist pattern 5a, 5b and 5c, the lower electrode L ₁ of FIG. 2, respectively, the resistance element R _1, and covers an area corresponding to R _2.

As shown in FIG. 9, the resist pattern 5
a, 5b, and 5c as masks, the polysilicon layer 6a
And the dielectric film 1 is partially etched. In this manner, the laminated structure of the polysilicon layer 6a and the dielectric film 1 is left in the region where the lower electrode L ₁ and the resistance elements R ₁ and R ₂ are to be formed.

The removal of the polysilicon layer 6a is a mixed gas of Cl ₂ and O ₂ as etching gas, CF ₄ gas or using a SF ₆ gas, microwave plasma etching (frequency 2 under a pressure of number mTorr,. 45 GHz)
Alternatively, it is performed by ECR plasma etching.

With the etching of the dielectric film 1, M
The surface of the polysilicon layer 2 serving as the gate electrode of the OSFET is cleaned. In order to perform sufficient cleaning, it is preferable to employ etching conditions that increase the etching selectivity of the dielectric film with respect to polysilicon.
For example, when the dielectric film 1 has a laminated structure having a silicon oxide film in the lower layer, the upper layer is removed by dry etching, and the silicon oxide film in the lower layer is replaced with buffered hydrofluoric acid (HF + NH) capable of performing stable etching. ₄ F +
(H ₂ O)) and the like. The upper portion may be removed by RF plasma etching under a condition of a pressure of 160 mTorr using a mixed gas of CF ₄ and CHF ₃ as an etching gas. At this time, the RF power is set to about 70
0W and the frequency is 13.56 MHz.

After partially etching the polysilicon layer 6a and the dielectric film 1, the resist patterns 5a, 5b and 5c are removed. The remaining dielectric film 1 corresponds to the region of the lower electrode L ₁ of the capacitance element C and the resistance elements R ₁ and R ₂ .

As shown in FIG. 10, a high melting point metal silicide layer 6b such as tungsten silicide (WSi) is deposited on the entire surface of the substrate, and the polysilicon layers 2, 6a and the dielectric film 1 are conformally covered. .

The WSi film is formed by sputtering or CVD.
Formed by In the case of forming by sputtering, for example, WSi is used as a target material, Ar is used as a sputtering gas, and the pressure is several mTorr.
This is performed by magnetron sputtering. CVD
In the case of forming by using, for example, tungsten hexafluoride (WF ₆ ) and silane (SiH
₄ )

[0037]

Embedded image A WSi ₂ film is deposited using a reaction of WF ₆ + 2SiH ₄ → WSi ₂ + 6HF + H ₂ .

The refractory metal silicide layer 6b is made of MoS
i, TiSi, TaSi or the like. Further, the refractory metal silicide layer 6b may be formed of a metal instead of the refractory metal silicide.

After the deposition of the refractory metal silicide layer 6b and before the formation of the interlayer insulating film, a heat treatment at about 1100 ° C. is performed to reduce the electric resistance of the refractory metal silicide layer 6b.

Steps up to the step shown in FIG. 11 will be described. First, the first refractory metal silicide layer 6b on the surface to form a resist pattern 7a and 7b respectively cover the area where the gate electrode G of the upper electrode L ₂ and MOSFET50 of the capacitor C is formed.

Using the resist patterns 7a and 7b as a mask, normal polycide etching is performed. The polycide electrode is etched using, for example, an ECR plasma etching apparatus. The etching gas is Cl ₂ + O ₂ gas, and the respective gas flow rates are 25 sccm and 11 sc
cm. For example, pressure is about 2 mTorr, RF power is 40 W, RF frequency is 13.56 MHz, microwave power is 1400 W, microwave frequency is 2.45 GH
z, the electrode temperature is 15-20 ° C.

As a result, the high melting point silicide layer 6b and the polysilicon layer 6a are selectively etched, and the capacitor C
Upper electrode L ₂ and the gate electrode G of the MOSFET are formed simultaneously. Further, the polysilicon layer 2 in a region not covered with the dielectric film 1 is removed. Since the dielectric film 1 functions as an etching stop layer, the resistive elements R ₁ , R ₂ and the lower electrode L ₁ of the capacitive element C are simultaneously formed in the remaining region of the dielectric film 1 in a self-aligned manner.

The dielectric film 1 acts as an etching stop layer, but is slightly etched by the etching gas. In this case, it is etched into the upper electrode regions and a resistor R ₁ that arranged non of L _2, the region formed of the R ₂ dielectric film 1 slightly out of the capacitor region. The dielectric film 1 in the capacitive element region has a thickness and a surface that is substantially the same as the dielectric film 1 on the resistance elements R ₁ and R ₂ (a surface having a uniform height from the surface of the field oxide film 3). Have.

After the polycide and polysilicon etching steps, the resist patterns 7a and 7b on the refractory metal silicide layer 6b are removed. In a portion corresponding to the gate electrode G, a silicide layer 6b is formed on the polysilicon layer 2, and a polycide electrode is formed as a whole.

After removing the resist patterns 7a and 7b,
Ion implantation for forming a low concentration drain structure is performed using the gate electrode G as a mask.

As shown in FIG. 12, the side wall of the gate electrode G
A sidewall spacer 8 is formed thereon. Side wall
The spacer 8 is formed by deposition of an insulating film by CVD and anisotropy.
Using reactive ion etching (RIE)
Is done. At this time, the resistance R ₁, R_Two, Lower electrode L₁Passing
And upper electrode L_TwoSidewall spacer 8 on the side wall
Is formed.

Using the gate electrode G and the sidewall spacer 8 as a mask, ion implantation for forming source / drain regions is performed. By performing activation annealing,
Source / drain regions 10 are formed.

As shown in FIG. 13, the steps of forming an interlayer insulating film 20, forming a contact hole CN for extracting an electrode, depositing and patterning a metal wiring M, and the like are sequentially performed.

An integrated device manufactured by using the manufacturing method of this embodiment.
In the circuit device, the lower electrode L of the capacitive element C₁Thickness
And the thickness of the polysilicon layer 2 forming the gate electrode G
It is almost equal. The resistance element R₁, R_TwoConductive part of
Min top height and lower electrode L ₁The height of the upper surface is almost the same
U.

The part of the lower electrode L ₁ of the capacitor C is a low-concentration region 2a, the other region is a high concentration region which is ion-implanted in the step of FIG. That is, the basic configuration of the capacitor C is the same as the basic configuration of the capacitor illustrated in FIG. Therefore, the low-concentration region 2a, the high concentration region of the surrounding, and the impurity concentration of the upper electrode L _2, and by adjusting the area of the low-concentration region 2a, to obtain a less stable capacitance in voltage dependence Can be.

Here, the low concentration region 2a is doped with impurities by ion implantation in the state of FIG.
It has the same impurity concentration as ₂ . The high concentration region of the lower electrode L ₁ is doped with an impurity by ion implantation in the step of FIG. 6 and FIG. 7, has the same impurity concentration and the polysilicon layer 2 of the resistance element R ₁ and the gate electrode G. Thus, the impurity concentration of the lower electrode L ₁ is determined by factors other than the preferred conditions in the capacitive element. Even in this case, by adjusting the area ratio between the low-density region 2a and the other high-density regions, it is possible to obtain a stable capacitance with small voltage dependency.

[0052] Further, the low concentration region 2a covers the areas corresponding to the resistance element R ₂ in the step shown in FIG. 7 with the resist pattern 2B, by also a region corresponding to the low concentration region 2a is covered with a resist pattern 2A They are formed in the same process. For this reason, it can be formed without adding a special step.

3 to 13 show one MOSFET as a typical example, FIG. 14 shows an n-channel MOS
C including FET50N and p-channel MOSFET50P
2 shows a MOS configuration. In the case of a CMOS configuration, FIG.
A well is formed in the active region before the field oxide film 3 is formed in the step shown in FIG. For example, silicon substrate 1
When 00 is a p-type, the p-channel MOSFET 5
An n-type well 11 is formed in a region where OP is to be formed. n
Channel MOSFET 50N and p-channel MOSFET
The respective gate electrodes GN and GP of 50P are formed at the same time in the same step up to the step shown in FIG.

In the heat treatment for forming the source and drain regions, an n-type impurity such as phosphorus is added to the source and drain regions 10N of the n-channel MOSFET 50N by p-type impurities.
A p-type impurity such as boron is added to the source and drain regions 10P of the channel MOSFET 50P. In addition,
In order to obtain a desired threshold voltage, a predetermined concentration of impurities may be added to the channel region after defining the active region in the step shown in FIG. 5, or after forming the polysilicon layer 2 shown in FIG. , N-channel MOSFET 50N or p
The work function of the gate electrode may be changed by adding an appropriate impurity to the region serving as the gate electrode of the channel MOSFET 50P.

Next, another embodiment of the present invention will be described with reference to FIGS. As shown in FIG.
Polysilicon layer 2 with defined low concentration regions 2a and 2b
To form This polysilicon layer 2 is formed through the same steps as the steps from FIG. 3 to FIG.

The dielectric film 1 is deposited on the polysilicon layer 2 in the same manner as the dielectric film 1 shown in FIG. In the case of FIG. 8, the polysilicon layer 6a is deposited following the dielectric film 1, but in this embodiment, the dielectric film 1 is patterned before depositing the polysilicon layer. The regions corresponding to the lower electrode L ₁ and the resistance elements R ₁ and R ₂ shown in FIG. 1 are covered with resist patterns 5a, 5b and 5c, respectively. Using the resist patterns 5a, 5b and 5c as a mask, the dielectric film 1 is partially etched.

As shown in FIG. 16, a polysilicon layer 6c is deposited so as to cover the polysilicon layer 2 and the dielectric film 1. The deposition of the polysilicon layer 6c is performed in the same manner as the polysilicon layer 6a of FIG. Next, the polysilicon layer 6c
Then, a refractory metal silicide layer 6d is deposited in the same manner as the refractory metal silicide layer 6b shown in FIG.

As shown in FIG. 17, in the same manner as the method described with reference to FIG. 11, FIG. 12, and FIG.
The resistance elements R ₁ and R ₂ and the MOSFET are formed, contact holes are opened, and wiring is formed. FIG. 17 shows a case where an n-channel MOS transistor 50N and a p-channel MOS transistor 50P are formed.

Fabricated using the manufacturing method of the other embodiment described above.
In the integrated circuit device, the gate electrodes GN and GP are
The polysilicon layer constituting the lower electrode L of the capacitive element C₁
At the same time, the polysilicon layer 2 and the upper electrode L_Two
Polysilicon deposited at the same time as the polysilicon layer part
And a layer 6c. Therefore, the gate electrodes GN and
And the thickness of the polysilicon layer forming the GP is determined by the lower electrode L
₁Thickness and upper electrode L _TwoAnd the thickness of the polysilicon layer
Is approximately equal to the sum of

The resistance element R₁And R_TwoConductive part of
Is the lower electrode L of the capacitive element C. ₁Almost equal to the upper surface of
High height.

[0061] In other embodiments above, the lower electrode L ₁ of the capacitor C, composed of the low-concentration region 2a and the other high density region. For this reason, the first shown in FIGS.
As in the case of the embodiment, a stable capacitance with little voltage dependency can be obtained.

In the above two embodiments, a case has been described in which polysilicon is used as the gate electrode of the MOSFET or the electrode of the capacitor, but amorphous silicon may be used instead of polysilicon. Further, another semiconductor material may be used.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0064]

As described above, according to the present invention,
A capacitance element having a small voltage dependency and having a capacitance can be manufactured without complicating the manufacturing process.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view illustrating a basic configuration of a capacitor according to an embodiment of the present invention, and FIG. 1B is a graph illustrating voltage dependence of capacitance of the capacitor. is there.

FIG. 2 is a plan view illustrating a structure of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view of a substrate for explaining a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view of a substrate for describing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view of a substrate for explaining a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view of a substrate for describing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a cross-sectional view of a substrate for explaining a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a cross-sectional view of a substrate for explaining a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a cross-sectional view of a substrate for describing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 10 is a cross-sectional view of a substrate for describing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 11 is a cross-sectional view of a substrate for explaining a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 12 is a cross-sectional view of a substrate for describing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 13 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 14 is a cross-sectional view of a semiconductor device having a CMOS structure to which an embodiment of the present invention is applied.

FIG. 15 is a cross-sectional view of a substrate for describing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 16 is a cross-sectional view of a substrate for describing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 17 is a cross-sectional view of a semiconductor device having a CMOS structure to which another embodiment of the present invention is applied.

[Explanation of symbols]

1, 62: dielectric film, 2, 6a, 6c: polysilicon layer, 2a, 2b: low concentration region, 2A, 2B, 5a, 5
b, 5c, 7a, 7b resist pattern, 3 field oxide film, 4 gate oxide film, 6b, 6d refractory metal silicide layer, 10 source / drain region, 11
n-type well, 50 ... MOSFET, 60 ... substrate, 61,
63: semiconductor layer, 61a: high concentration region, 61b: low concentration region, 100: semiconductor substrate

Claims (9)

[Claims] A substrate having an insulating region defined on a part of a surface thereof; and a substrate disposed on a part of the insulating region on the substrate surface;
A lower electrode formed of a semiconductor material and including a low-concentration region and a high-concentration region having mutually different impurity concentrations; a dielectric layer made of a dielectric material formed on the lower electrode; The lower electrode has an impurity concentration intermediate between the impurity concentration of the low-concentration region and the impurity concentration of the high-concentration region of the lower electrode, and faces the low-concentration region and the high-concentration region of the lower electrode. A semiconductor device comprising: a dielectric layer and an upper electrode forming a capacitor. 2. A semiconductor region is further defined on a part of the surface of the substrate, and a source layer and a drain layer are formed on a surface layer of a part of the semiconductor region on the substrate surface and on the surface layer. region,
And a gate electrode, wherein the gate electrode of the transistor is formed of the same material as the lower electrode, has the same thickness, is doped with the same impurity as the high-concentration region, and has a concentration of 2. The semiconductor device according to claim 1, wherein the semiconductor device is substantially the same as that of the high concentration region. 3. An insulating region on the surface of the substrate, on which the lower electrode is not formed, formed of the same material as the lower electrode, and doped with the same impurity as the low-concentration region. 3. The semiconductor device according to claim 1, further comprising a first resistance element having a concentration substantially equal to that of the low concentration region. 4. An insulating region on the surface of the substrate, on which the lower electrode is not formed, formed of the same material as the lower electrode, and doped with the same impurity as the high-concentration region. The semiconductor device according to claim 1, further comprising a second resistance element having a concentration substantially equal to that of the high concentration region. 5. A MOS formed on a surface of a semiconductor substrate
In a method of manufacturing a FET and a semiconductor device including a capacitive element in which a lower electrode, a dielectric layer, and an upper electrode are stacked on the semiconductor substrate in this order, a gate insulating film is formed on a part of the surface region. Preparing a semiconductor substrate on which an insulating film thicker than the gate insulating film is formed in another surface region; and forming a first semiconductor material made of a first semiconductor material on the gate insulating film and the thick insulating film. Forming a conductive layer; and forming a conductive layer of the first conductive layer on a portion of the first conductive layer corresponding to a gate electrode of the MOSFET and a portion of a region corresponding to a lower electrode of the capacitor. Adding an impurity for increasing the efficiency; forming a dielectric layer on the first conductive layer; and forming a second conductive layer made of the first semiconductor material on the dielectric layer. Forming, and the second Partially etching the conductive layer and the dielectric layer to leave a laminated structure of the second conductive layer and the dielectric layer on a region corresponding to a lower electrode of the capacitive element; Forming a third conductive layer made of metal or metal silicide so as to cover the conductive layer, the dielectric layer, and the first conductive layer; and forming an upper electrode of the capacitive element on the third conductive layer. Forming a mask member covering a region corresponding to the above and a region corresponding to the gate electrode of the MOSFET; and using the mask member as an etching mask, the dielectric layer as an etching stop layer and not covered with the mask member. Removing the third and second conductive layers in a region, and removing the first conductive layer in a region that is not covered with the dielectric layer or the mask member. A lower electrode formed by a part of the first conductive layer; an upper electrode formed by a part of the second and third conductive layers; and the lower electrode sandwiched between the upper electrode and the lower electrode. A method for manufacturing a semiconductor device including a part of a dielectric layer. 6. A MOS formed on a surface of a semiconductor substrate
In a method of manufacturing a semiconductor device including a FET, a resistance element, and a capacitance element formed by stacking a lower electrode, a dielectric layer, and an upper electrode in this order on the semiconductor substrate, A step of preparing a semiconductor substrate on which a film is formed and an insulating film thicker than the gate insulating film is formed in another surface region; and a first semiconductor material formed on the gate insulating film and the thick insulating film. Forming a first conductive layer; and forming a first conductive layer in a region of the first conductive layer corresponding to a gate electrode of the MOSFET and a part of a region corresponding to a lower electrode of the capacitor. Adding an impurity that increases the conductivity of the layer; forming a dielectric layer on the first conductive layer; and forming a second layer of the first semiconductor material on the dielectric layer. Forming a conductive layer; The second conductive layer and the dielectric layer are partially etched to form the second conductive layer and the dielectric layer on a region corresponding to a lower electrode of the capacitor and a region corresponding to the resistor. Forming a third conductive layer made of metal or metal silicide so as to cover the second conductive layer, the dielectric layer, and the first conductive layer; Forming, on the conductive layer, a mask member that covers a region corresponding to the upper electrode of the capacitive element and a region corresponding to the gate electrode of the MOSFET; and using the mask member as an etching mask, forming the dielectric layer on the conductive layer. As an etching stop layer, the third and second conductive layers in a region not covered with the mask member are removed, and the first conductive layer in a region not covered with the dielectric layer or the mask member is removed. Removing the capacitor, wherein the capacitive element is a lower electrode formed by a part of the first conductive layer, an upper electrode formed by a part of the second and third conductive layers, and A method of manufacturing a semiconductor device, comprising a part of the dielectric layer sandwiched between an upper electrode and a lower electrode, wherein the resistance element is constituted by a part of the first conductive layer. 7. A semiconductor substrate having a surface on which a semiconductor region and an insulating region are defined, a gate insulating film formed on the semiconductor region on the surface of the semiconductor substrate, and an insulating region on the surface of the semiconductor substrate. A lower electrode made of a first semiconductor material, a dielectric layer, and an upper electrode formed by laminating a layer made of the first semiconductor material and a layer made of metal or metal silicide are formed on a part of the region. A lower electrode, which is stacked in order, wherein the lower electrode is formed on a capacitor element including a low concentration region and a high concentration region having different impurity concentrations from each other; A first gate layer, a second gate layer deposited simultaneously with a layer made of the first semiconductor material forming the upper electrode, and the metal or metal silicide forming the upper electrode. A gate electrode having a stacked structure including a third gate layer deposited simultaneously with the layer. 8. A MOS formed on a surface of a semiconductor substrate
In a method of manufacturing a FET and a semiconductor device including a capacitive element in which a lower electrode, a dielectric layer, and an upper electrode are stacked on the semiconductor substrate in this order, a gate insulating film is formed on a part of the surface region. Preparing a semiconductor substrate on which an insulating film thicker than the gate insulating film is formed in another surface region; and forming a first semiconductor material made of a first semiconductor material on the gate insulating film and the thick insulating film. Forming a conductive layer; and forming a conductive layer of the first conductive layer on a portion of the first conductive layer corresponding to a gate electrode of the MOSFET and a portion of a region corresponding to a lower electrode of the capacitor. Adding an impurity that increases the efficiency; forming a dielectric layer on the first conductive layer; partially etching the dielectric layer to form a region corresponding to a lower electrode of the capacitor; The dielectric layer And to process, so as to cover the dielectric layer and the first conductive layer, the first
Forming a second conductive layer made of a semiconductor material of the following; forming a third conductive layer made of metal or metal silicide on the second conductive layer; Forming a mask member overlying a region corresponding to the upper electrode of the capacitive element and a region corresponding to the gate electrode of the MOSFET; and using the mask member as an etching mask and using the dielectric layer as an etching stop layer. Removing the third and second conductive layers in a region not covered by the mask member and removing the first conductive layer in a region not covered by the dielectric layer or the mask member; Wherein the capacitive element is a lower electrode formed by the first conductive layer, an upper electrode formed by the second and third conductive layers, and a portion between the upper electrode and the lower electrode. A method for manufacturing a semiconductor device comprising a part of the dielectric layer sandwiched between the semiconductor devices. 9. A MOS formed on a surface of a semiconductor substrate
In a method of manufacturing a semiconductor device including a FET, a resistance element, and a capacitance element formed by stacking a lower electrode, a dielectric layer, and an upper electrode in this order on the semiconductor substrate, A step of preparing a semiconductor substrate on which a film is formed and an insulating film thicker than the gate insulating film is formed in another surface region; and a first semiconductor material formed on the gate insulating film and the thick insulating film. Forming a first conductive layer; and forming a first conductive layer in a region of the first conductive layer corresponding to a gate electrode of the MOSFET and a part of a region corresponding to a lower electrode of the capacitor. Adding an impurity that increases the conductivity of the layer; forming a dielectric layer on the first conductive layer; partially etching the dielectric layer to correspond to a lower electrode of the capacitive element Area and front A step of leaving said dielectric layer in the region corresponding to the resistive element, so as to cover the dielectric layer and the first conductive layer, the first
Forming a second conductive layer made of a semiconductor material of the following; forming a third conductive layer made of metal or metal silicide on the second conductive layer; Forming a mask member overlying a region corresponding to the upper electrode of the capacitive element and a region corresponding to the gate electrode of the MOSFET; and using the mask member as an etching mask and using the dielectric layer as an etching stop layer. Removing the third and second conductive layers in a region not covered by the mask member and removing the first conductive layer in a region not covered by the dielectric layer or the mask member; A lower electrode formed by a part of the first conductive layer; an upper electrode formed by a part of the second and third conductive layers; It is constituted by a portion of the dielectric layer sandwiched between electrodes, the resistance element, a manufacturing method of the formed semiconductor device by a part of the first conductive layer.