JP5549049B2 - Thin film resistor, semiconductor device, and method of manufacturing thin film resistor - Google Patents

Thin film resistor, semiconductor device, and method of manufacturing thin film resistor Download PDF

Info

Publication number
JP5549049B2
JP5549049B2 JP2007221669A JP2007221669A JP5549049B2 JP 5549049 B2 JP5549049 B2 JP 5549049B2 JP 2007221669 A JP2007221669 A JP 2007221669A JP 2007221669 A JP2007221669 A JP 2007221669A JP 5549049 B2 JP5549049 B2 JP 5549049B2
Authority
JP
Japan
Prior art keywords
thin film
resistor
film resistor
silicon oxide
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007221669A
Other languages
Japanese (ja)
Other versions
JP2009054885A (en
Inventor
英記 加藤
公彦 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP2007221669A priority Critical patent/JP5549049B2/en
Publication of JP2009054885A publication Critical patent/JP2009054885A/en
Application granted granted Critical
Publication of JP5549049B2 publication Critical patent/JP5549049B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Description

本発明は、半導体装置の薄膜抵抗体に関し、薄膜抵抗体の下層膜厚の製造バラツキの影響がなく、薄膜抵抗体の特性に影響のない安定したレーザトリミングが可能な半導体装置の薄膜抵抗体に関するものである。   The present invention relates to a thin film resistor of a semiconductor device, and relates to a thin film resistor of a semiconductor device capable of stable laser trimming without being affected by manufacturing variations in the lower layer thickness of the thin film resistor and without affecting the characteristics of the thin film resistor. Is.

従来、薄膜抵抗体にレーザを照射し、そのレーザが照射した領域のみをトリミングし、抵抗値及び製品特性を調整するレーザトリミング技術がある。しかしながら、このレーザトリミングプロセスにおいては、薄膜抵抗体の下層膜厚の製造バラツキにより、薄膜抵抗体が正常にトリミングできない問題がある。   Conventionally, there is a laser trimming technique in which a thin film resistor is irradiated with a laser, only a region irradiated with the laser is trimmed, and a resistance value and product characteristics are adjusted. However, in this laser trimming process, there is a problem that the thin film resistor cannot be trimmed normally due to manufacturing variations in the lower layer thickness of the thin film resistor.

例えば、図7は、従来の半導体装置の薄膜抵抗領域の断面図を示したものであり、シリコン基板1上にフィールド酸化膜2及び第1の層間絶縁膜3を形成し、その上に導電端子4を配置し、更にその上層に第2の層間絶縁膜5を形成し、その上に薄膜抵抗体7及びパシベーション膜8を形成したものである。薄膜抵抗体7は、スルーホール6を介して導電端子4へ電気的に接続されており、他のデバイスへ接続されている。図8は、波長1.3umのレーザ光を図7に示す半導体装置表面側より、照射した場合の深さ方向のレーザ強度のシミュレーション結果を示すものである。製造バラツキとして薄膜抵抗体の下層のシリコン酸化膜厚について±5%で膜厚を変化させて行ったものである。薄膜抵抗体の下層膜厚が非常に薄く、殆どのレーザ光が薄膜抵抗体を透過してしまうために、シリコン基板界面での反射光強度が強く、その反射光が再び薄膜抵抗体へ照射されることより、入射光と反射光の干渉が生じている。反射光の位相は、薄膜抵抗体の下層膜厚に依存するため、下層膜厚の製造バラツキにより、薄膜抵抗体での実効的なレーザ強度が大きく変化することが分かる。そのことにより、ウエハ面内/ウエハ間/ロット間のトリミングが安定して行えなくなる不具合が生じる。   For example, FIG. 7 shows a cross-sectional view of a thin film resistance region of a conventional semiconductor device, in which a field oxide film 2 and a first interlayer insulating film 3 are formed on a silicon substrate 1, and a conductive terminal is formed thereon. 4, a second interlayer insulating film 5 is further formed thereon, and a thin film resistor 7 and a passivation film 8 are formed thereon. The thin film resistor 7 is electrically connected to the conductive terminal 4 through the through hole 6 and is connected to another device. FIG. 8 shows a simulation result of the laser intensity in the depth direction when a laser beam having a wavelength of 1.3 μm is irradiated from the surface side of the semiconductor device shown in FIG. As a manufacturing variation, the silicon oxide film thickness under the thin film resistor is changed by ± 5%. The film thickness of the thin film resistor is very thin, and most of the laser light is transmitted through the thin film resistor. Therefore, the reflected light intensity at the silicon substrate interface is strong, and the reflected light is irradiated to the thin film resistor again. As a result, interference between incident light and reflected light occurs. Since the phase of the reflected light depends on the lower layer film thickness of the thin film resistor, it can be seen that the effective laser intensity at the thin film resistor varies greatly depending on the manufacturing variation of the lower layer film thickness. As a result, there arises a problem that trimming within the wafer surface / between wafers / between lots cannot be performed stably.

薄膜抵抗体を安定してトリミングするためには、レーザの吸収率を上げれば良く、例えば、Poly Siを用いた、薄膜抵抗体においては、あらかじめ、レーザを照射する領域に高濃度に不純物注入を行う方法がある(図9参照)。また、下層膜厚にLOCOS段差を形成し、レーザパワーが強くなる領域が必ず存在するようにする方法や、併せて薄膜抵抗体表面にWの発熱膜を形成する方法(図10参照)が提案されている。   In order to stably trim the thin film resistor, it is only necessary to increase the laser absorptance. For example, in a thin film resistor using Poly Si, an impurity is implanted at a high concentration in a region irradiated with the laser in advance. There is a method to perform (see FIG. 9). Also proposed are a method of forming a LOCOS step in the lower layer thickness to ensure that there is a region where the laser power is strong, and a method of forming a W heating film on the surface of the thin film resistor (see FIG. 10). Has been.

また、レーザビームが照射されて切断又は変質されて抵抗値調整される複数の金属薄膜抵抗体R1,R2,R3が直列に接続されてなる抵抗回路を備え、金属薄膜抵抗体R1,R2,R3の抵抗値調整範囲ΔR1,ΔR2,ΔR3、総抵抗値調整範囲ΔR0(=ΔRa+ΔRb+ΔRc)、抵抗値調整精度R1_step,R2_step,R3_stepの関係が、ΔR2≧R1_step、ΔR3≧R2_step、R3_step≦0.001×ΔR0<R2_step≦0.01×ΔR0<R1_step≦0.1×ΔR0の関係を満たすことで、複数の金属薄膜抵抗体が直列に接続されている抵抗回路を備えた半導体装置において、広範囲な抵抗値調整範囲を高精度に抵抗値調整することができる技術が開示されている(例えば、特許文献1参照)。
特開2007−096174号公報
In addition, a resistor circuit is provided in which a plurality of metal thin film resistors R1, R2, and R3 whose resistance values are adjusted by being cut or altered by irradiation with a laser beam are provided, and the metal thin film resistors R1, R2, and R3 are provided. The resistance value adjustment ranges ΔR1, ΔR2, and ΔR3, the total resistance value adjustment range ΔR0 (= ΔRa + ΔRb + ΔRc), and the resistance value adjustment accuracy R1_step, R2_step, R3_step are ΔR2 ≧ R1_step, ΔR3 ≧ R2_step, R3_step ≦ 0.001 × ΔR0 <R2_step By satisfying the relationship of ≦ 0.01 × ΔR0 <R1_step ≦ 0.1 × ΔR0, a semiconductor device having a resistance circuit in which a plurality of metal thin film resistors are connected in series can be used to accurately resist a wide range of resistance value adjustment. A technique capable of adjusting the value is disclosed (for example, see Patent Document 1).
JP 2007-096174 A

しかしながら、Poly Siに高濃度な不純物を導入する方法や、表面にWの発熱膜を形成する方法においては、追加のマスク及びプロセス工程が必要となり、プロセスコストが増加する問題がある。また、高精度なアナログ集積回路の高集積化には、抵抗素子の抵抗値は、高い方が好ましく、レーザの吸収率を上げるには、薄膜抵抗体の膜厚を厚くする必要があるが、膜厚を厚くすると逆に抵抗値は低下する問題もある。   However, the method of introducing a high-concentration impurity into Poly Si and the method of forming a W heating film on the surface require an additional mask and a process step, which increases the process cost. In order to increase the integration of a high-precision analog integrated circuit, the resistance value of the resistance element is preferably high. To increase the absorption rate of the laser, it is necessary to increase the film thickness of the thin film resistor. On the contrary, there is a problem that the resistance value decreases when the film thickness is increased.

本発明はこのような状況に鑑みてなされたものであり、本発明は、新たなマスク及びプロセス工程を追加することなく、製造バラツキに影響がなく、薄膜抵抗体の特性に影響を与えることなく、安定したレーザトリミングを可能にすることを目的とする。   The present invention has been made in view of such a situation, and the present invention does not affect the manufacturing variation without adding a new mask and a process step, and does not affect the characteristics of the thin film resistor. An object is to enable stable laser trimming.

上記目的を達成するために、本発明の一態様は、半導体基板上に形成された、レーザトリミングがなされる薄膜抵抗体であって、前記レーザトリミングの対象である厚さ3〜50nmの膜厚で形成された第1の抵抗体と、前記第1の抵抗体の上層に10〜30nmの厚さで形成されたシリコン酸化膜と、前記シリコン酸化膜の上層に厚さ50nm以上の膜厚で形成された第2の抵抗体とを積層構造に有し、前記第2の抵抗体は、前記シリコン酸化膜によって前記第1の抵抗体と電気的に分離されており、前記レーザトリミングの際に透過するレーザ光の強度を弱めることを特徴とする。 In order to achieve the above object, one embodiment of the present invention is a thin film resistor which is formed on a semiconductor substrate and is subjected to laser trimming, and has a thickness of 3 to 50 nm which is a target of the laser trimming. A silicon oxide film formed in a thickness of 10 to 30 nm on the upper layer of the first resistor, and a film thickness of 50 nm or more on the upper layer of the silicon oxide film. The second resistor is formed in a laminated structure, and the second resistor is electrically separated from the first resistor by the silicon oxide film. During the laser trimming, the second resistor is electrically separated from the first resistor by the silicon oxide film. It is characterized in that the intensity of transmitted laser light is weakened .

本発明によれば、新たなマスク及びプロセス工程を追加することなく、製造バラツキに影響がなく、薄膜抵抗体の特性に影響を与えることなく、安定したレーザトリミングを可能にすることができる。   According to the present invention, it is possible to perform stable laser trimming without adding a new mask and process steps, without affecting manufacturing variations, and without affecting the characteristics of the thin film resistor.

図1は、本発明の第1の実施形態の薄膜抵抗体を備える半導体装置の断面図を示したものである。本構造は、図7に示した従来の第1の薄膜抵抗体7の上層にシリコン酸化膜9を形成し、更にその上層に第2の薄膜抵抗体10を積層した構造となっている。薄膜抵抗体を2層構造とし、それらの薄膜抵抗体の間に絶縁膜であるシリコン酸化膜9を形成することにより、上層と下層の薄膜抵抗体は電気的に分離されることより、製品に必要な抵抗値特性は、従来通り下層の第1薄膜抵抗体7の特性で決定され、上層の第2の薄膜抵抗体10は、レーザを吸収するのに必要な膜厚を独立して設定することが可能となる。   FIG. 1 shows a cross-sectional view of a semiconductor device including the thin film resistor according to the first embodiment of the present invention. This structure has a structure in which a silicon oxide film 9 is formed on an upper layer of the conventional first thin film resistor 7 shown in FIG. 7, and a second thin film resistor 10 is further stacked thereon. By forming the thin film resistor into a two-layer structure and forming a silicon oxide film 9 as an insulating film between the thin film resistors, the upper layer and the lower layer thin film resistors are electrically separated from each other. The required resistance value characteristic is determined by the characteristic of the first thin film resistor 7 in the lower layer as in the past, and the second thin film resistor 10 in the upper layer independently sets the film thickness necessary for absorbing the laser. It becomes possible.

図2は、上層の第2の薄膜抵抗体10の膜厚とレーザ強度の深さ方向分布のシミュレーション結果を示す図である。図2から、上層の第2の薄膜抵抗体10の膜厚が厚くなるのに伴い、第1の薄膜抵抗体7を透過するレーザ強度が弱くなることが分かる。このシミュレーション結果を用いて、第1の薄膜抵抗体7下層の層間絶縁膜内のレーザの振幅巾と上層の第2の薄膜抵抗体10の膜厚との関係を図3に示す。図3に示す通り、第2の薄膜抵抗体10の膜厚が50nm以上で薄膜抵抗体の透過レーザ強度が飽和し、第2の薄膜抵抗体10の膜厚を50nm以上に形成することで、上層の第2の薄膜抵抗体10でレーザ光を吸収し、同時に図2に示すように透過レーザ光のエネルギーが少なくなるので、光干渉効果も抑制され、製造バラツキによるレーザパワーの実効的なバラツキがなくなり、安定したトリミングが容易に実現可能となる。   FIG. 2 is a diagram showing a simulation result of the thickness direction distribution of the upper thin film resistor 10 and the laser intensity in the depth direction. From FIG. 2, it can be seen that the intensity of the laser beam transmitted through the first thin film resistor 7 decreases as the thickness of the second thin film resistor 10 in the upper layer increases. Using this simulation result, FIG. 3 shows the relationship between the amplitude width of the laser in the interlayer insulating film under the first thin film resistor 7 and the film thickness of the second thin film resistor 10 in the upper layer. As shown in FIG. 3, the transmission laser intensity of the thin film resistor is saturated when the film thickness of the second thin film resistor 10 is 50 nm or more, and the film thickness of the second thin film resistor 10 is formed to be 50 nm or more. The upper second thin film resistor 10 absorbs the laser beam, and at the same time, as shown in FIG. 2, the energy of the transmitted laser beam is reduced, so that the optical interference effect is suppressed, and the effective variation in laser power due to manufacturing variation. Therefore, stable trimming can be easily realized.

以下、図4を参照して、第1の実施形態の薄膜抵抗体を備える半導体装置の製造方法を説明する。まず、公知の半導体製造方法により、シリコン基板1上にフィールド酸化膜2、層間絶縁膜3及びAl−SiCu等の導電膜12を形成する(a)。   Hereinafter, with reference to FIG. 4, the manufacturing method of a semiconductor device provided with the thin film resistor of 1st Embodiment is demonstrated. First, a field oxide film 2, an interlayer insulating film 3, and a conductive film 12 such as Al-SiCu are formed on a silicon substrate 1 by a known semiconductor manufacturing method (a).

引き続き、公知な半導体製造方法の写真製版及びドライエッチング法により、導電膜12をパターニングし、導電端子4を形成する(b)。   Subsequently, the conductive film 12 is patterned by the known photolithography and dry etching methods of the semiconductor manufacturing method to form the conductive terminals 4 (b).

同様に、公知の半導体製造方法により、例えば、NSGやBPSG若しくは、TEOS膜等の層間絶縁膜を形成し、写真製版工程及びドライエッチング法により、第1の薄膜抵抗体7と、導電端子4とを電気的に接続するスルーホール6を形成する(c)。   Similarly, an interlayer insulating film such as NSG, BPSG, or TEOS film is formed by a known semiconductor manufacturing method, and the first thin film resistor 7, the conductive terminal 4, and the like are formed by a photolithography process and a dry etching method. Through holes 6 are formed to electrically connect the two (c).

次に、例えばSiCrターゲットを用いたスパッタ法により、第1の薄膜抵抗体7を3〜50nmの厚さで製膜し、その上層には、SiH4/N2Oの混合ガスを用いたプラズマCVD法により、シリコン酸化膜9を10〜20nm製膜し、その上層に再び下層の第1の薄膜抵抗体7と同様な方法により、第2の薄膜抵抗体10を50nm以上製膜する(d)。   Next, the first thin film resistor 7 is formed to a thickness of 3 to 50 nm by, for example, sputtering using a SiCr target, and the upper layer is formed by plasma CVD using a mixed gas of SiH 4 / N 2 O. Then, the silicon oxide film 9 is formed into a thickness of 10 to 20 nm, and the second thin film resistor 10 is formed into an upper layer again by the same method as the first thin film resistor 7 in the lower layer (d).

引き続き、公知の写真製版工程により、薄膜抵抗体7を形成する領域のみにレジスト13を残し(e)、Ar/SF6/Heの混合ガスを用いて上下層の薄膜抵体と間のシリコン酸化膜を同時にエッチング処置を行い薄膜抵抗体のパターンを形成し、一般的なプラズマCVD法により、例えば、シリコン窒化膜から成るパシベーション膜8を形成し完成する(f)。その際、シリコン酸化膜の選択比は1程度であるために、シリコン酸化膜が間に形成されていても問題となることは無い。 Subsequently, by a known photolithography process, the resist 13 is left only in the region where the thin film resistor 7 is to be formed (e), and silicon oxide is formed between the upper and lower thin film resistors using a mixed gas of Ar / SF 6 / He. The film is etched simultaneously to form a thin film resistor pattern, and a passivation film 8 made of, for example, a silicon nitride film is formed by a general plasma CVD method to complete (f). At that time, since the selection ratio of the silicon oxide film is about 1, there is no problem even if the silicon oxide film is formed therebetween.

図5は、本発明の第2の実施形態の薄膜抵抗体を備える半導体装置の断面図を示したものである。本構造は、第1の実施形態の構造に対して、上下の薄膜抵抗体間のシリコン酸化膜9を形成しない代わりに、上層の第3の薄膜抵抗体11の抵抗値が下層の第1の薄膜抵抗体7の抵抗値より、10倍以上の抵抗値となるように形成されている。シリコン酸化膜形成を省くことで、工程が簡略化されプロセスコストの削減が可能となる。また、抵抗値を高くすることで、下層の第1の薄膜抵抗体7の抵抗値への特性変動を抑えることが可能となる。抵抗値の比が10倍であれば、約10%の特性変動を受けることとなるが、アナログトリミング技術を使用すれば、許容範囲である。しかし、より高精度な製品においては、影響を少なくするために100倍以上あることが好ましい。例えば、第1の薄膜抵抗体7をSi/Cr組成比70/30のターゲットを用いて、スパッタ法にて5nm製膜することで、10kΩ/□の抵抗値の薄膜抵抗体が形成でき、第3の薄膜抵抗体11としては、Si/Cr組成比82/18のターゲットを用いて、スパッタチャンバに窒素を11sccm導入して50nm製膜することで、130kΩ/□の薄膜抵抗体を形成することができる。   FIG. 5 shows a cross-sectional view of a semiconductor device including the thin film resistor according to the second embodiment of the present invention. This structure is different from the structure of the first embodiment in that the resistance value of the upper third thin film resistor 11 is lower than that of the lower first thin film resistor 11 instead of forming the silicon oxide film 9 between the upper and lower thin film resistors. The resistance value of the thin film resistor 7 is 10 times or more. By omitting the formation of the silicon oxide film, the process can be simplified and the process cost can be reduced. Further, by increasing the resistance value, it is possible to suppress the characteristic variation to the resistance value of the first thin film resistor 7 in the lower layer. If the ratio of the resistance values is 10 times, the characteristic fluctuation is about 10%. However, if the analog trimming technique is used, it is an allowable range. However, in a more accurate product, it is preferably 100 times or more in order to reduce the influence. For example, a thin film resistor having a resistance value of 10 kΩ / □ can be formed by forming the first thin film resistor 7 to a thickness of 5 nm by sputtering using a target having a Si / Cr composition ratio of 70/30. As the thin film resistor 11 of No. 3, a 130 k / □ thin film resistor is formed by introducing 11 sccm of nitrogen into the sputtering chamber and forming a film of 50 nm using a target having a Si / Cr composition ratio of 82/18. Can do.

以上のように、薄膜抵抗体の抵抗値制御は、SiCrを用いた薄膜抵抗体においては、スパッタ装置のSi/Crターゲット組成をSi濃度が濃いターゲットを用いたり、スパッタ時に窒素を導入することで、容易に制御することができる。   As described above, in the thin film resistor using SiCr, the resistance value of the thin film resistor can be controlled by using a Si / Cr target composition of the sputtering apparatus with a high Si concentration target or introducing nitrogen during sputtering. Can be easily controlled.

また、第2の実施形態の薄膜抵抗体を備える半導体装置の製造方法は、第1の実施形態の製造方法のシリコン酸化膜形成工程を省き、第3の薄膜抵抗体11の製膜条件を変更することのみで実現可能である。具体的には、図6に示すように、公知の半導体製造方法により、シリコン基板1上にフィールド酸化膜2、層間絶縁膜3及びAl−SiCu等の導電膜12を形成する(a)。   Further, in the method of manufacturing a semiconductor device including the thin film resistor according to the second embodiment, the silicon oxide film forming step of the manufacturing method according to the first embodiment is omitted, and the film forming conditions of the third thin film resistor 11 are changed. This is possible only by doing. Specifically, as shown in FIG. 6, a field oxide film 2, an interlayer insulating film 3, and a conductive film 12 such as Al—SiCu are formed on the silicon substrate 1 by a known semiconductor manufacturing method (a).

引き続き、公知な半導体製造方法の写真製版及びドライエッチング法により、導電膜12をパターニングし、導電端子4を形成する(b)。   Subsequently, the conductive film 12 is patterned by the known photolithography and dry etching methods of the semiconductor manufacturing method to form the conductive terminals 4 (b).

同様に、公知の半導体製造方法により、例えば、NSGやBPSG若しくは、TEOS膜等の層間絶縁膜を形成し、写真製版工程及びドライエッチング法により、第1の薄膜抵抗体7と、導電端子4とを電気的に接続するスルーホール6を形成する(c)。   Similarly, an interlayer insulating film such as NSG, BPSG, or TEOS film is formed by a known semiconductor manufacturing method, and the first thin film resistor 7, the conductive terminal 4, and the like are formed by a photolithography process and a dry etching method. Through holes 6 are formed to electrically connect the two (c).

次に、例えば、組成比が70/30のSiCrターゲットを用いたスパッタ法により、第1の薄膜抵抗体7を3〜50nmの厚さで製膜し、その上層に第3の薄膜抵抗体11と同様なスパッタ法により、Si/Cr組成比82/18 の ターゲットを用い、窒素を11sccm導入して50nm製膜する(d)。   Next, for example, the first thin film resistor 7 is formed with a thickness of 3 to 50 nm by sputtering using a SiCr target having a composition ratio of 70/30, and the third thin film resistor 11 is formed thereon. Using a target having a Si / Cr composition ratio of 82/18, 11 sccm of nitrogen is introduced to form a film of 50 nm by the same sputtering method (d).

引き続き、公知の写真製版工程により、薄膜抵抗体7を形成する領域のみにレジスト13を残し(e)、Ar/SF6/Heの混合ガスを用いて上下層の薄膜抵体をエッチング処置により薄膜抵抗体のパターンを形成し、一般的なプラズマCVD法により、例えば、シリコン窒化膜から成るパシベーション膜8を形成し完成する(f)。 Subsequently, the resist 13 is left only in the region where the thin film resistor 7 is to be formed by a known photolithography process (e), and the upper and lower thin film resistors are etched by using a mixed gas of Ar / SF 6 / He. A resistor pattern is formed, and a passivation film 8 made of, for example, a silicon nitride film is formed and completed by a general plasma CVD method (f).

薄膜抵抗体を2層の積層構造とし、上層の薄膜抵抗体の抵抗値が下層の薄膜抵抗素子の10倍以上とすることで、上層の抵抗値特性の影響を抑制するとともに、レーザ光の吸収効率の良い薄膜抵抗体を形成でき、安定したトリミングが実現できる。   The thin film resistor has a two-layer structure, and the resistance value of the upper layer thin film resistor is 10 times or more that of the lower layer thin film resistor element, thereby suppressing the influence of the upper layer resistance value characteristic and absorbing the laser beam. An efficient thin film resistor can be formed, and stable trimming can be realized.

本発明の第3の実施形態の薄膜抵抗体を備える半導体装置としては、図1に示すシリコン酸化膜9にリンまたはボロンを導入したことを特徴としている。シリコン酸化膜にリンやボロンの不純物を導入することで、シリコン酸化膜の融点が下がり、レーザ照射時の薄膜抵抗体との化学反応及び物理的変化が起こり易くなり、より安定したトリミングを行うことが可能となる。   The semiconductor device including the thin film resistor according to the third embodiment of the present invention is characterized in that phosphorus or boron is introduced into the silicon oxide film 9 shown in FIG. By introducing phosphorus or boron impurities into the silicon oxide film, the melting point of the silicon oxide film is lowered, and chemical reactions and physical changes with the thin film resistor during laser irradiation are likely to occur, so that more stable trimming can be performed. Is possible.

シリコン酸化膜へのリンやボロンを導入は、公知の半導体プロセスの通り、PH3やB26ガスを導入してプラズマCVD法により形成する。 Phosphorus or boron is introduced into the silicon oxide film by plasma CVD using a PH 3 or B 2 H 6 gas as in known semiconductor processes.

なお、上述する各実施の形態は、本発明の好適な実施の形態であり、本発明の要旨を逸脱しない範囲内において種々変更実施が可能である。   Each of the above-described embodiments is a preferred embodiment of the present invention, and various modifications can be made without departing from the scope of the present invention.

本発明の第1の実施形態の薄膜抵抗体を備える半導体装置の断面図である。It is sectional drawing of a semiconductor device provided with the thin film resistor of the 1st Embodiment of this invention. 本発明の深さ方向のレーザ強度のシミュレーション結果である。It is a simulation result of the laser intensity of the depth direction of this invention. 第2の薄膜抵抗体膜厚と抵抗体を透過するレーザ強度の関係を示す図である。It is a figure which shows the relationship between the 2nd thin film resistor film thickness, and the laser intensity which permeate | transmits a resistor. 本発明の第1の実施形態の製造方法を説明する図である。It is a figure explaining the manufacturing method of the 1st Embodiment of this invention. 本発明の第2の実施形態の薄膜抵抗体を備える半導体装置の断面図である。It is sectional drawing of a semiconductor device provided with the thin film resistor of the 2nd Embodiment of this invention. 本発明の第2の実施形態の製造方法を説明する図である。It is a figure explaining the manufacturing method of the 2nd Embodiment of this invention. 従来例の半導体装置の断面図である。It is sectional drawing of the semiconductor device of a prior art example. 従来例の深さ方向のレーザ強度のシミュレーション結果を示す図である。It is a figure which shows the simulation result of the laser intensity of the depth direction of a prior art example. 従来例の半導体装置の一例の説明図である。It is explanatory drawing of an example of the semiconductor device of a prior art example. 従来例の半導体装置の一例の説明図である。It is explanatory drawing of an example of the semiconductor device of a prior art example.

符号の説明Explanation of symbols

1 シリコン基板
2 フィールド酸化膜
3 第1の層間絶縁膜
4 導電端子
5 第2の層間絶縁膜
6 スルーホール
7 第1の薄膜抵抗体
8 パシベーション膜
9 シリコン酸化膜
10 第2の薄膜抵抗体
11 第3の薄膜抵抗体
12 導電性膜
13 レジスト
14 発熱する導電性膜
15 高光吸収領域
16 低光吸収領域
17 拡散層
DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Field oxide film 3 1st interlayer insulation film 4 Conductive terminal 5 2nd interlayer insulation film 6 Through hole 7 1st thin film resistor 8 Passivation film 9 Silicon oxide film 10 2nd thin film resistor 11 1st 3 Thin film resistor 12 Conductive film 13 Resist 14 Heat generating conductive film 15 High light absorption region 16 Low light absorption region 17 Diffusion layer

Claims (7)

半導体基板上に形成された、レーザトリミングがなされる薄膜抵抗体であって、
前記レーザトリミングの対象である厚さ3〜50nmの膜厚で形成された第1の抵抗体と、
前記第1の抵抗体の上層に10〜30nmの厚さで形成されたシリコン酸化膜と、
前記シリコン酸化膜の上層に厚さ50nm以上の膜厚で形成された第2の抵抗体と
を積層構造に有し、
前記第2の抵抗体は、前記シリコン酸化膜によって前記第1の抵抗体と電気的に分離されており、前記レーザトリミングの際に透過するレーザ光の強度を弱めることを特徴とする薄膜抵抗体。
A thin film resistor formed on a semiconductor substrate and subjected to laser trimming,
A first resistor formed with a thickness of 3 to 50 nm, which is an object of the laser trimming ;
A silicon oxide film formed in a thickness of 10 to 30 nm on an upper layer of the first resistor;
A second resistor formed in a thickness of 50 nm or more on the upper layer of the silicon oxide film in a laminated structure;
The thin film resistor, wherein the second resistor is electrically separated from the first resistor by the silicon oxide film, and weakens the intensity of the laser beam transmitted during the laser trimming. .
前記第1の抵抗体と前記第2の抵抗体の材料としてSiCrを用いたことを特徴とする請求項1に記載の薄膜抵抗体。 2. The thin film resistor according to claim 1, wherein SiCr is used as a material for the first resistor and the second resistor. 前記シリコン酸化膜にリンまたはボロンが導入されていることを特徴とする請求項1又は2に記載の薄膜抵抗体。 3. The thin film resistor according to claim 1, wherein phosphorus or boron is introduced into the silicon oxide film. 請求項1から3のいずれか1項に記載の薄膜抵抗体を備えることを特徴とする半導体装置。   A semiconductor device comprising the thin film resistor according to claim 1. 半導体基板上に形成された、レーザトリミングがなされる薄膜抵抗体の製造方法であって、
前記レーザトリミングの対象である第1の抵抗体を厚さ3〜50nmの膜厚で形成するステップと、
シリコン酸化膜を前記第1の抵抗体の上層に10〜30nmの厚さで形成するステップと、
前記シリコン酸化膜により前記第1の抵抗体とは電気的に分離されており、前記レーザトリミングの際に透過するレーザ光の強度を弱める第2の抵抗体を前記シリコン酸化膜の上層に厚さ50nm以上の膜厚で形成するステップと
を有することを特徴とする薄膜抵抗体の製造方法。
A method of manufacturing a thin film resistor formed on a semiconductor substrate and subjected to laser trimming,
Forming the first resistor to be laser trimmed with a thickness of 3 to 50 nm;
Forming a silicon oxide film on the first resistor in a thickness of 10 to 30 nm;
The silicon oxide film is electrically isolated from the first resistor, and a second resistor that weakens the intensity of the laser beam that is transmitted during the laser trimming has a thickness above the silicon oxide film. Forming a thin film resistor having a film thickness of 50 nm or more.
前記第1の抵抗体と前記第2の抵抗体の材料としてSiCrを用いることを特徴とする請求項5に記載の薄膜抵抗体の製造方法。  6. The method of manufacturing a thin film resistor according to claim 5, wherein SiCr is used as a material for the first resistor and the second resistor. 前記シリコン酸化膜にリンまたはボロンが導入されていることを特徴とする請求項5又は6に記載の薄膜抵抗体の製造方法。 7. The method of manufacturing a thin film resistor according to claim 5, wherein phosphorus or boron is introduced into the silicon oxide film.
JP2007221669A 2007-08-28 2007-08-28 Thin film resistor, semiconductor device, and method of manufacturing thin film resistor Active JP5549049B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007221669A JP5549049B2 (en) 2007-08-28 2007-08-28 Thin film resistor, semiconductor device, and method of manufacturing thin film resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007221669A JP5549049B2 (en) 2007-08-28 2007-08-28 Thin film resistor, semiconductor device, and method of manufacturing thin film resistor

Publications (2)

Publication Number Publication Date
JP2009054885A JP2009054885A (en) 2009-03-12
JP5549049B2 true JP5549049B2 (en) 2014-07-16

Family

ID=40505683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007221669A Active JP5549049B2 (en) 2007-08-28 2007-08-28 Thin film resistor, semiconductor device, and method of manufacturing thin film resistor

Country Status (1)

Country Link
JP (1) JP5549049B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6919137B2 (en) * 2017-05-11 2021-08-18 新日本無線株式会社 Manufacturing method of semiconductor devices

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2536303B2 (en) * 1989-07-28 1996-09-18 日本電装株式会社 Semiconductor device manufacturing method
JPH09232118A (en) * 1996-02-28 1997-09-05 Matsushita Electric Works Ltd Semiconductor device
JPH09246384A (en) * 1996-03-08 1997-09-19 Hitachi Ltd Fuse element and semiconductor integrated circuit device provided therewith
JP4457846B2 (en) * 2003-10-24 2010-04-28 ヤマハ株式会社 Semiconductor device and manufacturing method thereof
JP4776199B2 (en) * 2004-09-30 2011-09-21 株式会社リコー Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
JP2009054885A (en) 2009-03-12

Similar Documents

Publication Publication Date Title
US7416951B2 (en) Thin film resistors integrated at two different metal interconnect levels of single die
JP4776199B2 (en) Manufacturing method of semiconductor device
CN103972211A (en) Semiconductor device
KR20070076449A (en) Semiconductor device and fabrication method thereof
JP2005251822A (en) Semiconductor device
JP5824330B2 (en) Semiconductor device and manufacturing method of semiconductor device
US8748988B2 (en) Semiconductor device having resistor formed of a polycrystalline silicon film
US20200403061A1 (en) Method and structure for dual sheet resistance trimmable thin film resistors
JP5549049B2 (en) Thin film resistor, semiconductor device, and method of manufacturing thin film resistor
US10014253B2 (en) Method of manufacturing semiconductor integrated circuit device
JP2006222410A (en) Semiconductor device and manufacturing method thereof
JP2005235888A (en) Semiconductor device and its manufacturing method
JP6595873B2 (en) Semiconductor integrated circuit device and manufacturing method thereof
JP2005235995A (en) Semiconductor device and its manufacturing method
CN103035613A (en) Semiconductor device
KR100350030B1 (en) Semiconductor device manufacturing method
JP2006310829A (en) Fuse element, method of cutting same, and semiconductor device having same
JP4675050B2 (en) Semiconductor device
JP4646891B2 (en) Semiconductor device and manufacturing method thereof
JP5025774B2 (en) Manufacturing method of semiconductor device
JP4610247B2 (en) Semiconductor device and manufacturing method thereof
JP4498819B2 (en) Thin film resistance device and resistance temperature characteristic adjusting method
JP2005303051A (en) Semiconductor device and manufacturing method thereof
JP4497975B2 (en) Semiconductor device
JP2009239068A (en) Semiconductor device and manufacturing method therefor

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100316

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20121130

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130108

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130311

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130917

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140422

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140505

R151 Written notification of patent or utility model registration

Ref document number: 5549049

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250