JP4454206B2 - Memory circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory circuit, and more particularly to a configuration of a memory circuit having SRAM type memory cells.
[0002]
[Prior art]
FIGS. 16 and 17 are circuit diagrams showing the configuration of a conventional memory circuit having SRAM type memory cells (see Japanese Patent Laid-Open No. 10-222985). The memory circuit shown in FIG. 16 includes a write word line WLw and a transistor Tr101, a read word line WLr and a transistor Tr102, a bit line BL, and a latch circuit in which inverter circuits INV101 and INV102 are cross-connected. I have. Each one electrode of the transistors Tr101 and Tr102 is connected to the bit line BL.
[0003]
In the memory circuit shown in FIG. 17, the write word line WLw and the transistor Tr105, the read word line WLr and the transistors Tr103 and Tr104, the bit line BL, and the inverter circuits INV101 and INV102 are cross-connected. And a latch circuit. Each one electrode of the transistors Tr103 and Tr105 is connected to the bit line BL.
[0004]
[Problems to be solved by the invention]
In the memory circuit shown in FIG. 16, two transistors Tr101 and Tr102 are connected to the bit line BL for each memory cell. Similarly, in the memory circuit shown in FIG. 17, two transistors Tr103 and Tr105 are connected to the bit line BL. For this reason, the conventional memory circuit has a problem that the load capacity of the bit line BL increases and the access time and power consumption increase.
[0005]
The present invention has been made to solve such a problem, and an object of the present invention is to obtain a memory circuit capable of reducing the load capacity of the bit line BL and shortening the time required for the read operation. .
[0006]
[Means for Solving the Problems]
  The memory circuit according to claim 1 of the present invention includes a bit line, a word line,A first storage node to which data is written, and a second storage node to which data having a polarity opposite to that of data written to the first storage node is writtenA latch circuit, a control electrode connected to the word line, and one electrode connected to the bit line;The secondA first electrode having the other electrode connected to one storage nodeN channelA transistor and a firstStorage nodeOne end connected to theFirst potential lower than the potential set by the precharge of the bit lineThe other end connected to the potential andA second N-channel transistor and a third N-channel transistor connected in series, and the control electrode of the second N-channel transistor is connected to the second storage node, and the third N-channel transistor A signal for conducting between the one electrode and the other electrode of the third N-channel transistor is inputted to the control electrode of the transistor in the read state.Is.
[0007]
  Moreover, the memory circuit according to claim 2 of the present invention includes:A latch circuit having a bit line, a word line, a first storage node to which data is written, and a second storage node to which data having a polarity opposite to that of data written to the first storage node is written; A first N-channel transistor having a control electrode connected to, one electrode connected to the bit line, and the other electrode connected to the first storage node, and one connected to the second storage node A logic circuit having an input terminal, another input terminal to which a predetermined signal indicating whether the latch circuit is in a writing state or a reading state is input, and an output terminal; and the other electrode of the first N-channel transistor One connected electrode, the other electrode connected to the first potential lower than the potential set by the precharge of the bit line, and the output of the logic circuit A second N-channel transistor having a control electrode connected to the child, wherein the second N-channel transistor receives a signal output from the logic circuit and the predetermined signal indicates a read state Is conductive or non-conductive depending on the state of the second storage node, and is non-conductive when a predetermined signal indicates a write state.Is.
[0008]
  Moreover, the memory circuit according to claim 3 of the present invention isA latch circuit having a bit line, a word line, a first storage node to which data is written, and a second storage node to which data having a polarity opposite to that of data written to the first storage node is written; A first N-channel transistor having a control electrode connected to, one electrode connected to the bit line, and the other electrode connected to the first storage node, and one connected to the first storage node A logic circuit having an input terminal, another input terminal to which a predetermined signal indicating whether the latch circuit is in a writing state or a reading state is input, and an output terminal; and the other electrode of the first N-channel transistor One connected electrode, the other electrode connected to the first potential lower than the potential set by the precharge of the bit line, and the output of the logic circuit A second N-channel transistor having a control electrode connected to the child, wherein the second N-channel transistor receives a signal output from the logic circuit and the predetermined signal indicates a read state Is conductive or non-conductive depending on the state of the first storage node, and is non-conductive when a predetermined signal indicates a write state.Is.
[0009]
  According to a fourth aspect of the present invention, the memory circuit according to the first aspect is the memory circuit according to the first aspect,A control electrode connected to the first storage node; one electrode connected to the second storage node; and the other electrode connected between the second N-channel transistor and the third N-channel transistor. A fourth N-channel transistor havingIt is characterized by this.
[0010]
  According to a fifth aspect of the present invention, the memory circuit includes the first and second bit lines, the first and second word lines, the first memory node to which data is written, and the first memory. A latch circuit having a second storage node to which data having a polarity opposite to that of data written to the node is written; a control electrode connected to the first word line; and one electrode connected to the first bit line And a first N-channel transistor having the other electrode connected to the first storage node, one end connected to the first storage node, and a potential set by precharging the first bit line. A second N-channel transistor and a third N-channel transistor connected in series between the other end connected to the lower first potential and a second word line A fourth N-channel transistor having a control electrode, one electrode connected to the second bit line, the other electrode connected to the second storage node, and one end connected to the second storage node; A fifth N-channel transistor and a sixth N-channel transistor connected in series between the other end connected to the first potential, and a second N-channel transistorAnd the control electrode of the second storage node is connected to the second storage node,The control electrode of the fifth N-channel transistor is the first1Is connected to the storage node of the third N-channel transistor, and in the read state, a signal for conducting between the one electrode and the other electrode of the third N-channel transistor is input to the control electrode of the third N-channel transistor. In the read state, a signal for conducting between one electrode and the other electrode of the sixth N-channel transistor is input to the control electrode of the transistor.
[0011]
  A memory circuit according to a sixth aspect of the present invention is the memory circuit according to any one of the first to fifth aspects,The latch circuit includes a first inverter having a first P-channel transistor and a first other N-channel transistor, and a second inverter having a second P-channel transistor and a second other N-channel transistor. The input terminal of the first inverter and the output terminal of the second inverter are connected to the first storage node, and the output terminal of the first inverter and the input terminal of the second inverter are the second Connected to other storage nodesIt is characterized by this.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a memory circuit according to Embodiment 1 of the present invention, which has an SRAM type memory cell having a single port configuration and a single end configuration. As shown in FIG. 1, the memory circuit according to the first embodiment includes a bit line BL, a word line WL, a latch circuit 1 disposed at an intersection of the bit line BL and the word line WL, a transistor Tr1 to Tr3.
[0013]
The latch circuit 1 is configured by cross-connecting two inverter circuits INV1 and INV2. Specifically, the output terminal of the inverter circuit INV1 is connected to the input terminal of the inverter circuit INV2, and the output terminal of the inverter circuit INV2 is connected to the input terminal of the inverter circuit INV1. The input terminal of the inverter circuit INV1 is defined as the first storage node ND1, and the input terminal of the inverter circuit INV2 is defined as the second storage node ND2.
[0014]
The drain electrode of the transistor Tr1 is connected to the bit line BL, the source electrode is connected to the first storage node ND1, and the gate electrode is connected to the word line WL. The drain electrode of the transistor Tr2 is connected to the source electrode of the transistor Tr1, and the gate electrode is connected to the second storage node ND2. The drain electrode of the transistor Tr3 is connected to the source electrode of the transistor Tr2, and the source electrode is connected to the ground potential. A write signal / WR obtained by inverting a predetermined write signal WR is input to the gate electrode of the transistor Tr3. Here, the symbol “/” means an overbar. The write signal / WR is a signal indicating whether the latch circuit 1 (strictly, a memory cell) is in a write state or a read state. The potential of the write signal / WR is low when the latch circuit 1 is in the write state, and is high when the latch circuit 1 is in the read state.
[0015]
FIG. 2 is a circuit diagram showing a specific configuration of the latch circuit 1. The inverter circuit INV1 has transistors Q1 and Q2, and the inverter circuit INV2 has transistors Q3 and Q4. The gate electrode of the transistor Q2 is connected to the first storage node ND1, the drain electrode is connected to the second storage node ND2, and the source electrode is connected to the ground potential. The gate electrode of the transistor Q4 is connected to the second storage node ND2, the drain electrode is connected to the first storage node ND1, and the source electrode is connected to the ground potential.
[0016]
Hereinafter, an operation of the memory circuit illustrated in FIG. 1 will be described.
[0017]
First, a data write operation will be described. In this case, the high write signal WR is inverted, and the low write signal / WR is input to the gate electrode of the transistor Tr3. As a result, the transistor Tr3 is turned off. After that, by applying a high voltage to the word line WL, a high voltage is applied to the gate electrode of the transistor Tr1, and the transistor Tr1 is turned on. In this state, by applying high or low data to be written to the memory cell to the bit line BL, the data is written to the first storage node ND1 via the transistor Tr1. The data written to the first storage node ND1 is inverted by the inverter circuit INV1 and written to the second storage node ND2.
[0018]
Here, when low data is written to the first storage node ND1, the potential of the second storage node ND2 becomes High, and this potential is applied to the gate electrode of the transistor Tr2, so that the transistor Tr2 is turned on. It becomes. However, since the transistor Tr3 is in the off state in the write state as described above, no through current flows through the path from the transistor Tr1 to the ground potential via the transistors Tr2 and Tr3, and a high-speed write operation is realized. ing.
[0019]
Next, a data read operation will be described. In this case, the low write signal WR is inverted, and the high write signal / WR is input to the gate electrode of the transistor Tr3. As a result, the transistor Tr3 is turned on. Further, the potential of the bit line BL is set to High by precharging. After that, by applying a high voltage to the word line WL, the transistor Tr1 is turned on, and the bit line BL and the first storage node ND1 are made conductive.
[0020]
When high data is stored in the first storage node ND1, the potential of the second storage node ND2 is low and the transistor Tr2 is in an off state. Therefore, no charge is extracted from the bit line BL, and the potential of the bit line BL is kept high. Accordingly, by detecting that the potential of the bit line BL is high after a predetermined time has elapsed, high data is read from the memory cell.
[0021]
On the other hand, when low data is stored in the first storage node ND1, the potential of the second storage node ND2 is High, and the transistor Tr2 is on. Further, as described above, the transistor Tr3 is in the on state in the reading state. Therefore, the source electrode of the transistor Tr1 and the source electrode (ground potential) of the transistor Tr3 are electrically connected, and the charge is extracted from the bit line BL to the ground potential via the transistors Tr1 to Tr3 in this order (first path). It is. Referring to FIG. 2, when low data is stored in first storage node ND1, the potential of second storage node ND2 is high and transistor Q4 is in an on state. Therefore, charge is extracted from the bit line BL to the ground potential via the transistor Tr1, the first storage node ND1, and the transistor Q4 in this order (second path). Accordingly, by detecting that the potential of the bit line BL is low after a predetermined time has elapsed, low data is read from the memory cell.
[0022]
Thus, according to the memory circuit of the first embodiment, as shown in FIG. 1, only one transistor Tr1 is connected to the bit line BL for each memory cell. Therefore, compared with the conventional memory circuit shown in FIGS. 16 and 17, the load capacity of the bit line BL can be reduced, and the access time can be shortened and the power consumption can be reduced.
[0023]
Further, when the low data is read from the first storage node ND1 by the operation of the transistors Tr2 and Tr3 as the selection means, the bit line BL is not only used by the second path but also by the first path. The charge is extracted. Therefore, the efficiency of extracting charges from the bit line BL is high, and the time required for the read operation can be shortened, so that a high-speed operation can be realized as a whole. Further, since the charge extraction efficiency is increased by the addition of the first path, the size (channel width W) of the transistor Q4 configuring the second path can be reduced. Therefore, it is possible to reduce the required area when the transistor Q4 is formed in the semiconductor substrate.
[0024]
Embodiment 2. FIG.
FIG. 3 is a circuit diagram showing a memory circuit according to Embodiment 2 of the present invention. The storage circuit according to the second embodiment is a single port configuration storage circuit shown in FIG. 1 developed into a dual port configuration. As shown in FIG. 3, bit lines BL1 and BL2 and word lines WL1 and WL2, a latch circuit 1, and transistors Tr1 to Tr6.
[0025]
The drain electrode of the transistor Tr1 is connected to the bit line BL1, the source electrode is connected to the first storage node ND1, and the gate electrode is connected to the word line WL1. The drain electrode of the transistor Tr2 is connected to the source electrode of the transistor Tr1, and the gate electrode is connected to the second storage node ND2. The drain electrode of the transistor Tr3 is connected to the source electrode of the transistor Tr2, and the source electrode is connected to the ground potential. A write signal / WR1 obtained by inverting a predetermined write signal WR1 is input to the gate electrode of the transistor Tr3.
[0026]
The drain electrode of the transistor Tr4 is connected to the bit line BL2, the source electrode is connected to the second storage node ND2, and the gate electrode is connected to the word line WL2. The drain electrode of the transistor Tr5 is connected to the source electrode of the transistor Tr4, and the gate electrode is connected to the first storage node ND1. The drain electrode of the transistor Tr6 is connected to the source electrode of the transistor Tr5, and the source electrode is connected to the ground potential. A write signal / WR2 obtained by inverting a predetermined write signal WR2 is input to the gate electrode of the transistor Tr6.
[0027]
Note that the word lines WL1 and WL2 can operate independently of each other. The polarity of the data is inverted between reading data stored in the memory cell via the bit line BL1 and reading data via the bit line BL2. The same applies when data is written to the memory cell.
[0028]
Hereinafter, an operation of the memory circuit illustrated in FIG. 3 will be described.
[0029]
First, a data write operation will be described. When accessing from the bit line BL1, the transistor Tr3 is turned off by applying the low write signal / WR1, and then the transistor Tr1 is turned on by applying a high voltage to the word line WL1. Desired data is written to the memory cell from line BL1. By turning off the transistor Tr3, it is possible to prevent a through current from flowing through the path from the transistor Tr1 to the ground potential via the transistors Tr2 and Tr3. Similarly, when accessing from the bit line BL2, the transistor Tr6 is turned off by applying the low write signal / WR2, and then the transistor Tr4 is turned on by applying a high voltage to the word line WL2. In the state, desired data is written into the memory cell from the bit line BL2. By turning off the transistor Tr6, it is possible to prevent a through current from flowing through the path from the transistor Tr4 to the ground potential via the transistors Tr5 and Tr6.
[0030]
However, the transistors Tr3 and Tr6 may both be turned off in the write state regardless of which of the bit lines BL1 and BL2 is accessed. As a result, a through current does not flow through a path reaching the ground potential via the transistors Tr2 and Tr3 and a path reaching the ground potential via the transistors Tr5 and Tr6, thereby realizing a higher-speed write operation.
[0031]
Next, a data read operation will be described. In this case, the transistors Tr3 and Tr6 are both turned on by applying the high write signals / WR1 and / WR2.
[0032]
When accessing from the bit line BL1, the potential of the bit line BL1 is set to High by precharging, and then the transistor Tr1 is turned on by applying a high voltage to the word line WL1. When high data is stored in the first storage node ND1, no charge is extracted from the bit line BL1. Accordingly, by detecting that the potential of the bit line BL1 after the elapse of a predetermined time is high, high data is read from the first storage node ND1. On the other hand, when low data is stored in the first storage node ND1, charges are extracted from the bit line BL1 to the ground potential through the transistors Tr1 to Tr3 in this order, and from the bit line BL1 to the transistor Tr1, The charge is extracted to the ground potential through the one storage node ND1 and the transistor Q4 in this order. Therefore, by detecting that the potential of the bit line BL1 after a predetermined time has passed is low, low data is read from the first storage node ND1.
[0033]
When accessing from the bit line BL2, the potential of the bit line BL2 is set to High by precharging, and then the transistor Tr4 is turned on by applying a high voltage to the word line WL2. When high data is stored in the second storage node ND2, no charge is extracted from the bit line BL2. Accordingly, by detecting that the potential of the bit line BL2 after a predetermined time has elapsed is high, high data is read from the second storage node ND2. On the other hand, when low data is stored in the second storage node ND2, charges are extracted from the bit line BL2 to the ground potential through the transistors Tr4 to Tr6 in this order, and from the bit line BL2 to the transistor Tr4. The charge is extracted to the ground potential through the second storage node ND2 and the transistor Q2 in this order. Therefore, by detecting that the potential of the bit line BL2 after the lapse of a predetermined time is low, low data is read from the second storage node ND2.
[0034]
Thus, according to the memory circuit of the second embodiment, as shown in FIG. 3, only one transistor Tr1, Tr4 is connected to each of the bit lines BL1, BL2 for each memory cell. Absent. Therefore, the load capacity of the bit lines BL1 and BL2 can be reduced, and the access time can be shortened and the power consumption can be reduced.
[0035]
Further, when reading low data from the first storage node ND1 and reading low data from the second storage node ND2 by the operation of the transistors Tr2 and Tr3 and the transistors Tr5 and Tr6 as selection means, Charges are extracted from the bit lines BL1 and BL2 through two paths. Therefore, the efficiency of extracting charges from the bit lines BL1 and BL2 is high, and the time required for the read operation can be shortened, so that a high-speed operation can be realized as a whole.
[0036]
In the above description, the memory circuit having the dual port configuration is described, but a memory circuit having a 3-port configuration or more may be used. The same applies to the third embodiment described later.
[0037]
Embodiment 3 FIG.
FIG. 4 is a circuit diagram showing a memory circuit according to Embodiment 3 of the present invention. The memory circuit according to the third embodiment is obtained by combining the transistors Tr3 and Tr6 shown in FIG. 3 into a transistor Tr7, and the other configurations are the same as those in FIG. The drain electrode of the transistor Tr7 is connected to the source electrodes of the transistors Tr2 and Tr5, respectively, and the source electrode is connected to the ground potential. A write signal / WR obtained by inverting a predetermined write signal WR is input to the gate electrode of the transistor Tr7. Since the operation of the circuit is the same as that of the second embodiment, description thereof is omitted.
[0038]
As described above, according to the memory circuit of the third embodiment, in addition to the same effects as those of the second embodiment, the following effects can be obtained. That is, since one transistor Tr7 is provided instead of the two transistors Tr3 and Tr6 shown in FIG. 3, the device area can be reduced as compared with the second embodiment.
[0039]
Embodiment 4 FIG.
FIG. 5 is a circuit diagram showing a memory circuit according to Embodiment 4 of the present invention. The storage circuit according to the fifth embodiment is obtained by developing the single-ended storage circuit shown in FIG. 1 into a dual-ended configuration. As shown in FIG. 5, the bit lines BL and / BL and the word circuit A line WL, a latch circuit 1, and transistors Tr1 to Tr6 are provided.
[0040]
The drain electrode of the transistor Tr4 is connected to the bit line / BL, the source electrode is connected to the second storage node ND2, and the gate electrode is connected to the word line WL. The drain electrode of the transistor Tr5 is connected to the source electrode of the transistor Tr4, and the gate electrode is connected to the first storage node ND1. The drain electrode of the transistor Tr6 is connected to the source electrode of the transistor Tr5, and the source electrode is connected to the ground potential. A write signal / WR obtained by inverting a predetermined write signal WR is input to the gate electrode of the transistor Tr6. Other configurations are the same as those in FIG.
[0041]
Hereinafter, an operation of the memory circuit illustrated in FIG. 5 will be described.
[0042]
First, a data write operation will be described. In this case, the transistors Tr3 and Tr6 are turned off by applying a low write signal / WR, and then the transistors Tr1 and Tr4 are turned on by applying a high voltage to the word line WL. In this state, desired data (for example, High) is written from the bit line BL to the first storage node ND1, and data having a reverse polarity (for example, Low) is written from the bit line / BL to the second storage node ND2. Since the transistors Tr3 and Tr6 are both turned off in the write state, no through current flows through the path reaching the ground potential via the transistors Tr2 and Tr3 and the path reaching the ground potential via the transistors Tr5 and Tr6. A high-speed write operation is realized.
[0043]
Next, a data read operation will be described. In this case, the transistors Tr3 and Tr6 are both turned on by applying the high write signal / WR. Then, the potentials of the bit lines BL and / BL are set to high by precharging, and then the transistors Tr1 and Tr4 are turned on by applying a high voltage to the word line WL.
[0044]
When high data is stored in the first storage node ND1 and low data is stored in the second storage node ND2, no charge is extracted from the bit line BL. Accordingly, by detecting that the potential of the bit line BL is high after a predetermined time has elapsed, high data is read from the first storage node ND1. In this case, charges are extracted from the bit line / BL to the ground potential through the transistors Tr4 to Tr6 in this order, and the transistor Tr4, the second storage node ND2, and the transistor Q2 are connected in this order from the bit line / BL. The charge is extracted to the ground potential. Therefore, by detecting that the potential of the bit line / BL is low after a predetermined time has elapsed, low data is read from the second storage node ND2.
[0045]
On the other hand, when low data is stored in the first storage node ND1 and high data is stored in the second storage node ND2, no charge is extracted from the bit line / BL. Accordingly, by detecting that the potential of the bit line / BL is high after a predetermined time has elapsed, high data is read from the second storage node ND2. In this case, charges are extracted from the bit line BL to the ground potential through the transistors Tr1 to Tr3 in this order, and from the bit line BL to the transistor Tr1, the first storage node ND1, and the transistor Q4 in this order. Charge is drawn to ground potential. Accordingly, by detecting that the potential of the bit line BL is low after a predetermined time has elapsed, low data is read from the first storage node ND1.
[0046]
Thus, according to the memory circuit of the fourth embodiment, as shown in FIG. 5, only one transistor Tr1, Tr4 is connected to the bit lines BL, / BL for each memory cell. Not. Therefore, the load capacity of the bit lines BL and / BL can be reduced, and the access time can be shortened and the power consumption can be reduced.
[0047]
Further, when reading low data from the first storage node ND1 and reading low data from the second storage node ND2 by the operation of the transistors Tr2 and Tr3 and the transistors Tr5 and Tr6 as selection means, Charges are extracted from the bit lines BL and / BL through two paths. Therefore, the efficiency of extracting charges from the bit lines BL and / BL is high, and the time required for the read operation can be shortened, so that a high-speed operation can be realized as a whole.
[0048]
Embodiment 5 FIG.
FIG. 6 is a circuit diagram showing a memory circuit according to Embodiment 5 of the present invention. The memory circuit according to the sixth embodiment is obtained by combining the transistors Tr3 and Tr6 shown in FIG. 5 into a transistor Tr7, and the other configurations are the same as those in FIG. Since the operation of the circuit is the same as that of the fourth embodiment, description thereof is omitted.
[0049]
As described above, according to the memory circuit of the fifth embodiment, in addition to the same effects as those of the fourth embodiment, the following effects can be obtained. That is, since one transistor Tr7 is provided instead of the two transistors Tr3 and Tr6 shown in FIG. 5, the device area can be reduced as compared with the fourth embodiment.
[0050]
Embodiment 6 FIG.
FIG. 7 is a circuit diagram showing a memory circuit according to Embodiment 6 of the present invention. The memory circuit according to the sixth embodiment is obtained by reversing the connection order of the transistors Tr2 and Tr3 shown in FIG. 1, and the other configurations are the same as those in FIG. The drain electrode of the transistor Tr3 is connected to the source electrode of the transistor Tr1. The drain electrode of the transistor Tr2 is connected to the source electrode of the transistor Tr3, and the source electrode is connected to the ground potential. Since the operation of the circuit is the same as that of the first embodiment, description thereof is omitted.
[0051]
According to the memory circuit of the sixth embodiment, the same effect as in the first embodiment can be obtained.
[0052]
Embodiment 7. FIG.
FIG. 8 is a circuit diagram showing a memory circuit according to Embodiment 7 of the present invention. The memory circuit according to the seventh embodiment is obtained by reversing the connection order of the transistors Tr2 and Tr3 and the connection order of the transistors Tr5 and Tr6 shown in FIG. 3, and other configurations are the same as those in FIG. is there. The drain electrode of the transistor Tr6 is connected to the source electrode of the transistor Tr4. The drain electrode of the transistor Tr5 is connected to the source electrode of the transistor Tr6, and the source electrode is connected to the ground potential. Since the operation of the circuit is the same as that of the second embodiment, description thereof is omitted.
[0053]
According to the memory circuit of the seventh embodiment, the same effect as in the second embodiment can be obtained.
[0054]
Embodiment 8 FIG.
FIG. 9 is a circuit diagram showing a memory circuit according to Embodiment 8 of the present invention. In the memory circuit according to the eighth embodiment, the connection order of the transistors Tr2 and Tr3 and the connection order of the transistors Tr5 and Tr6 shown in FIG. 5 are reversed, and the other configurations are the same as those in FIG. is there. The drain electrode of the transistor Tr3 is connected to the source electrode of the transistor Tr1. The drain electrode of the transistor Tr2 is connected to the source electrode of the transistor Tr3, and the source electrode is connected to the ground potential. The drain electrode of the transistor Tr6 is connected to the source electrode of the transistor Tr4. The drain electrode of the transistor Tr5 is connected to the source electrode of the transistor Tr6, and the source electrode is connected to the ground potential. Since the operation of the circuit is the same as that of the fourth embodiment, description thereof is omitted.
[0055]
According to the memory circuit of the eighth embodiment, the same effect as in the fourth embodiment can be obtained.
[0056]
Embodiment 9 FIG.
FIG. 10 is a circuit diagram showing a memory circuit according to Embodiment 9 of the present invention, which has an SRAM type memory cell having a single port configuration and a single end configuration. As shown in FIG. 10, the memory circuit according to the ninth embodiment includes a bit line BL, a word line WL, a latch circuit 1, transistors Tr1 and Tr11, and an AND circuit AND1.
[0057]
The drain electrode of the transistor Tr11 is connected to the source electrode of the transistor Tr1, the source electrode is connected to the ground potential, and the gate electrode is connected to the output terminal of the AND circuit AND1. One input terminal of the AND circuit AND1 is connected to the second storage node ND2. A write signal / WR obtained by inverting a predetermined write signal WR is input to the other input terminal of the AND circuit AND1.
[0058]
Hereinafter, an operation of the memory circuit illustrated in FIG. 10 will be described.
[0059]
First, a data write operation will be described. In this case, the low write signal / WR is input to the other input terminal of the AND circuit AND1. As a result, Low is output from the AND circuit AND1, and the transistor Tr11 is turned off. After that, by applying a high voltage to the word line WL, the transistor Tr1 is turned on. In this state, by applying high or low data to be written to the memory cell to the bit line BL, the data is written to the first storage node ND1 via the transistor Tr1. Since the transistor Tr11 is in the off state in the writing state as described above, a through current does not flow through the path from the transistor Tr1 to the ground potential via the transistor Tr11, and a high-speed writing operation is realized.
[0060]
Next, a data read operation will be described. In this case, the high write signal / WR is input to the other input terminal of the AND circuit AND1. Further, the potential of the bit line BL is set to High by precharging. After that, by applying a high voltage to the word line WL, the transistor Tr1 is turned on, and the bit line BL and the first storage node ND1 are made conductive.
[0061]
When High data is stored in the first storage node ND1, the potential of the second storage node ND2 is Low, and this potential is input to one input terminal of the AND circuit AND1, so that the AND circuit Low is output from AND1. As a result, the transistor Tr11 is turned off. Therefore, no charge is extracted from the bit line BL, and high data is read from the memory cell by detecting that the potential of the bit line BL is high after a predetermined time has elapsed.
[0062]
On the other hand, when low data is stored in the first storage node ND1, since the potential of the second storage node ND2 is High, the AND circuit AND1 outputs High and the transistor Tr11 is turned on. Become. Therefore, the source electrode of the transistor Tr1 and the source electrode (ground potential) of the transistor Tr11 become conductive, and charge is extracted from the bit line BL to the ground potential via the transistors Tr1 and Tr11 in this order (first path). It is. Referring to FIG. 2, the charge is extracted from the bit line BL to the ground potential through the transistor Tr1, the first storage node ND1, and the transistor Q4 in this order (second path). Accordingly, by detecting that the potential of the bit line BL is low after a predetermined time has elapsed, low data is read from the memory cell.
[0063]
Thus, according to the memory circuit of the ninth embodiment, as shown in FIG. 10, only one transistor Tr1 is connected to the bit line BL for each memory cell. Therefore, compared with the conventional memory circuit shown in FIGS. 16 and 17, the load capacity of the bit line BL can be reduced, and the access time can be shortened and the power consumption can be reduced.
[0064]
Further, when the low data is read from the first storage node ND1 by the operation of the transistor Tr11 and the AND circuit AND1 as selection means, the bit line is used not only by the second path but also by the first path. Charge is extracted from BL. Therefore, the efficiency of extracting charges from the bit line BL is high, and the time required for the read operation can be shortened, so that a high-speed operation can be realized as a whole.
[0065]
Embodiment 10 FIG.
FIG. 11 is a circuit diagram showing a memory circuit according to Embodiment 10 of the present invention. The storage circuit according to the tenth embodiment is an expansion of the single-port storage circuit shown in FIG. 10 into a dual-port configuration. As shown in FIG. 11, bit lines BL1 and BL2 and word lines WL1, WL2, latch circuit 1, transistors Tr1, Tr4, Tr11, Tr12, and AND circuits AND1, AND2.
[0066]
The drain electrode of the transistor Tr12 is connected to the source electrode of the transistor Tr4, the source electrode is connected to the ground potential, and the gate electrode is connected to the output terminal of the AND circuit AND2. One input terminal of the AND circuit AND2 is connected to the first storage node ND1. A write signal / WR2 obtained by inverting a predetermined write signal WR2 is input to the other input terminal of the AND circuit AND2. A write signal / WR1 obtained by inverting a predetermined write signal WR1 is input to the other input terminal of the AND circuit AND1.
[0067]
Hereinafter, an operation of the memory circuit illustrated in FIG. 11 will be described.
[0068]
First, a data write operation will be described. When accessing from the bit line BL1, the transistor Tr11 is turned off by applying the low write signal / WR1, and then the transistor Tr1 is turned on by applying a high voltage to the word line WL1. Desired data is written to the memory cell from line BL1. By turning off the transistor Tr11, it is possible to prevent a through current from flowing through the path from the transistor Tr1 to the ground potential via the transistor Tr11. Similarly, when accessing from the bit line BL2, the transistor Tr12 is turned off by applying the low write signal / WR2, and then the transistor Tr4 is turned on by applying a high voltage to the word line WL2. In the state, desired data is written into the memory cell from the bit line BL2. By turning off the transistor Tr12, it is possible to prevent a through current from flowing through a path from the transistor Tr4 to the ground potential via the transistor Tr12.
[0069]
However, the transistors Tr11 and Tr12 may both be turned off in the write state regardless of which of the bit lines BL1 and BL2 is accessed. Thereby, a through current does not flow through a path reaching the ground potential via the transistor Tr11 and a path reaching the ground potential via the transistor Tr12, and a higher-speed write operation is realized.
[0070]
Next, a data read operation will be described. In this case, high write signals / WR1, / WR2 are input to the other input terminals of the AND circuits AND1, AND2, respectively.
[0071]
When accessing from the bit line BL1, the potential of the bit line BL1 is set to High by precharging, and then the transistor Tr1 is turned on by applying a high voltage to the word line WL1. When high data is stored in the first storage node ND1, no charge is extracted from the bit line BL1. Accordingly, by detecting that the potential of the bit line BL1 after the elapse of a predetermined time is high, high data is read from the first storage node ND1. On the other hand, when low data is stored in the first storage node ND1, charges are extracted from the bit line BL1 to the ground potential through the transistors Tr1 and Tr11 in this order, and the transistor Tr1 from the bit line BL1 The charge is extracted to the ground potential through the one storage node ND1 and the transistor Q4 in this order. Therefore, by detecting that the potential of the bit line BL1 after a predetermined time has passed is low, low data is read from the first storage node ND1.
[0072]
When accessing from the bit line BL2, the potential of the bit line BL2 is set to High by precharging, and then the transistor Tr4 is turned on by applying a high voltage to the word line WL2. When high data is stored in the second storage node ND2, no charge is extracted from the bit line BL2. Accordingly, by detecting that the potential of the bit line BL2 after a predetermined time has elapsed is high, high data is read from the second storage node ND2. On the other hand, when low data is stored in the second storage node ND2, charges are extracted from the bit line BL2 to the ground potential through the transistors Tr4 and Tr12 in this order, and from the bit line BL2 to the transistor Tr4. The charge is extracted to the ground potential through the second storage node ND2 and the transistor Q2 in this order. Therefore, by detecting that the potential of the bit line BL2 after the lapse of a predetermined time is low, low data is read from the second storage node ND2.
[0073]
Thus, according to the memory circuit of the tenth embodiment, as shown in FIG. 11, only one transistor Tr1, Tr4 is connected to each of the bit lines BL1, BL2 for each memory cell. Absent. Therefore, the load capacity of the bit lines BL1 and BL2 can be reduced, and the access time can be shortened and the power consumption can be reduced.
[0074]
When reading low data from the first storage node ND1 and reading low data from the second storage node ND2 by the operation of the transistors Tr11 and Tr12 and the AND circuits AND1 and AND2 as selection means. , Charges are extracted from the bit lines BL1 and BL2 through two paths. Therefore, the efficiency of extracting charges from the bit lines BL1 and BL2 is high, and the time required for the read operation can be shortened, so that a high-speed operation can be realized as a whole.
[0075]
In the above description, the memory circuit having the dual port configuration is described, but a memory circuit having a 3-port configuration or more may be used.
[0076]
Embodiment 11 FIG.
FIG. 12 is a circuit diagram showing a memory circuit according to Embodiment 11 of the present invention. The storage circuit according to the eleventh embodiment is an expansion of the single-ended storage circuit shown in FIG. 10 into a dual-ended configuration. As shown in FIG. 12, bit lines BL and / BL and word A line WL, a latch circuit 1, transistors Tr1, Tr4, Tr11, Tr12, and AND circuits AND1, AND2 are provided.
[0077]
The drain electrode of the transistor Tr4 is connected to the bit line / BL. The drain electrode of the transistor Tr12 is connected to the source electrode of the transistor Tr4, the source electrode is connected to the ground potential, and the gate electrode is connected to the output terminal of the AND circuit AND2. One input terminal of the AND circuit AND2 is connected to the first storage node ND1. A write signal / WR obtained by inverting a predetermined write signal WR is input to the other input terminal of the AND circuit AND2. Other configurations are the same as those in FIG.
[0078]
Hereinafter, an operation of the memory circuit illustrated in FIG. 12 will be described.
[0079]
First, a data write operation will be described. In this case, the transistors Tr11 and Tr12 are turned off by applying the low write signal / WR, and then the transistors Tr1 and Tr4 are turned on by applying a high voltage to the word line WL. In this state, desired data (for example, High) is written from the bit line BL to the first storage node ND1, and data having a reverse polarity (for example, Low) is written from the bit line / BL to the second storage node ND2. Since the transistors Tr11 and Tr12 are both turned off in the writing state, a through current does not flow through the path reaching the ground potential via the transistor Tr11 and the path reaching the ground potential via the transistor Tr12, and the high-speed writing operation Is realized.
[0080]
Next, a data read operation will be described. In this case, a high write signal / WR is input to each of the other input terminals of the AND circuits AND1 and AND2.
[0081]
When high data is stored in the first storage node ND1 and low data is stored in the second storage node ND2, no charge is extracted from the bit line BL. Accordingly, by detecting that the potential of the bit line BL is high after a predetermined time has elapsed, high data is read from the first storage node ND1. In this case, charges are extracted from the bit line / BL to the ground potential via the transistors Tr4 and Tr12 in this order, and the transistor Tr4, the second storage node ND2, and the transistor Q2 are connected in this order from the bit line / BL. The charge is extracted to the ground potential. Therefore, by detecting that the potential of the bit line / BL is low after a predetermined time has elapsed, low data is read from the second storage node ND2.
[0082]
On the other hand, when low data is stored in the first storage node ND1 and high data is stored in the second storage node ND2, no charge is extracted from the bit line / BL. Accordingly, by detecting that the potential of the bit line / BL is high after a predetermined time has elapsed, high data is read from the second storage node ND2. In this case, the charge is extracted from the bit line BL to the ground potential via the transistors Tr1 and Tr11 in this order, and from the bit line BL via the transistor Tr1, the first storage node ND1, and the transistor Q4 in this order. Charge is drawn to ground potential. Accordingly, by detecting that the potential of the bit line BL is low after a predetermined time has elapsed, low data is read from the first storage node ND1.
[0083]
Thus, according to the memory circuit of the eleventh embodiment, as shown in FIG. 12, only one transistor Tr1, Tr4 is connected to each of the bit lines BL, / BL for each memory cell. Not. Therefore, the load capacity of the bit lines BL and / BL can be reduced, and the access time can be shortened and the power consumption can be reduced.
[0084]
When reading low data from the first storage node ND1 and reading low data from the second storage node ND2 by the operation of the transistors Tr11 and Tr12 and the AND circuits AND1 and AND2 as selection means. , Charges are extracted from the bit lines BL1 and BL2 through two paths. Therefore, the efficiency of extracting charges from the bit lines BL1 and BL2 is high, and the time required for the read operation can be shortened, so that a high-speed operation can be realized as a whole.
[0085]
Embodiment 12 FIG.
FIG. 13 is a circuit diagram showing a memory circuit according to the twelfth embodiment of the present invention, which has an SRAM type memory cell having a single port configuration and a single end configuration. As shown in FIG. 13, the memory circuit according to the twelfth embodiment includes a bit line BL, a word line WL, a latch circuit 1, transistors Tr1 and Tr21, and a NOR circuit NOR1.
[0086]
The drain electrode of the transistor Tr21 is connected to the source electrode of the transistor Tr1, the source electrode is connected to the ground potential, and the gate electrode is connected to the output terminal of the NOR circuit NOR1. One input terminal of the NOR circuit NOR1 is connected to the first storage node ND1. A predetermined write signal WR is input to the other input terminal of the NOR circuit NOR1.
[0087]
Hereinafter, an operation of the memory circuit illustrated in FIG. 13 will be described.
[0088]
First, a data write operation will be described. In this case, the high write signal WR is input to the other input terminal of the NOR circuit NOR1. As a result, Low is output from the NOR circuit NOR1, and the transistor Tr21 is turned off. After that, by applying a high voltage to the word line WL, the transistor Tr1 is turned on. In this state, by applying high or low data to be written to the memory cell to the bit line BL, the data is written to the first storage node ND1 via the transistor Tr1. Since the transistor Tr21 is in the off state in the write state as described above, a through current does not flow through the path from the transistor Tr1 to the ground potential via the transistor Tr21, and a high-speed write operation is realized.
[0089]
Next, a data read operation will be described. In this case, the low write signal WR is input to the other input terminal of the NOR circuit NOR1. Further, the potential of the bit line BL is set to High by precharging. After that, by applying a high voltage to the word line WL, the transistor Tr1 is turned on, and the bit line BL and the first storage node ND1 are made conductive.
[0090]
When High data is stored in the first storage node ND1, since this High is input to one input terminal of the NOR circuit NOR1, Low is output from the NOR circuit NOR1. As a result, the transistor Tr21 is turned off. Therefore, no charge is extracted from the bit line BL, and high data is read from the memory cell by detecting that the potential of the bit line BL is high after a predetermined time has elapsed.
[0091]
On the other hand, when Low data is stored in the first storage node ND1, High is output from the NOR circuit NOR1, and the transistor Tr21 is turned on. Therefore, the source electrode of the transistor Tr1 and the source electrode (ground potential) of the transistor Tr21 are brought into conduction, and charge is extracted from the bit line BL through the transistor Tr21 (first path) to the ground potential. Referring to FIG. 2, the charge is extracted from the bit line BL to the ground potential through the transistor Tr1, the first storage node ND1, and the transistor Q4 in this order (second path). Accordingly, by detecting that the potential of the bit line BL is low after a predetermined time has elapsed, low data is read from the memory cell.
[0092]
As described above, according to the memory circuit of the twelfth embodiment, as shown in FIG. 13, only one transistor Tr1 is connected to the bit line BL for each memory cell. Therefore, compared with the conventional memory circuit shown in FIGS. 16 and 17, the load capacity of the bit line BL can be reduced, and the access time can be shortened and the power consumption can be reduced.
[0093]
When reading low data from the first storage node ND1 by the operation of the transistor Tr21 and the NOR circuit NOR1 as selection means, not only the second path but also the first path can be used for the bit line. Charge is extracted from BL. Therefore, the efficiency of extracting charges from the bit line BL is high, and the time required for the read operation can be shortened, so that a high-speed operation can be realized as a whole.
[0094]
Embodiment 13 FIG.
FIG. 14 is a circuit diagram showing a memory circuit according to Embodiment 13 of the present invention. The storage circuit according to the fourteenth embodiment is an expansion of the single-port storage circuit shown in FIG. 13 into a dual-port configuration. As shown in FIG. 14, bit lines BL1 and BL2 and word lines WL1, WL2, latch circuit 1, transistors Tr1, Tr4, Tr21, Tr22, and NOR circuits NOR1, NOR2.
[0095]
The drain electrode of the transistor Tr22 is connected to the source electrode of the transistor Tr4, the source electrode is connected to the ground potential, and the gate electrode is connected to the output terminal of the NOR circuit NOR2. One input terminal of the NOR circuit NOR2 is connected to the second storage node ND2. A predetermined write signal WR2 is input to the other input terminal of the NOR circuit NOR2. A predetermined write signal WR1 is input to the other input terminal of the NOR circuit NOR1.
[0096]
Hereinafter, an operation of the memory circuit illustrated in FIG. 14 will be described.
[0097]
First, a data write operation will be described. When accessing from the bit line BL1, the transistor Tr21 is turned off by applying the high write signal WR1, and then the transistor Tr1 is turned on by applying a high voltage to the word line WL1. Write desired data from BL1 to the memory cell. By turning off the transistor Tr21, it is possible to prevent a through current from flowing through a path from the transistor Tr1 to the ground potential via the transistor Tr21. Similarly, when accessing from the bit line BL2, the transistor Tr22 is turned off by applying the high write signal WR2, and then the transistor Tr4 is turned on by applying a high voltage to the word line WL2. Then, desired data is written into the memory cell from the bit line BL2. By turning off the transistor Tr22, it is possible to prevent a through current from flowing through a path from the transistor Tr4 to the ground potential via the transistor Tr22.
[0098]
However, the transistors Tr21 and Tr22 may both be turned off in the write state regardless of the access from the bit lines BL1 and BL2. As a result, a through current does not flow through a path that reaches the ground potential via the transistor Tr21 and a path that reaches the ground potential via the transistor Tr22, and a higher-speed write operation is realized.
[0099]
Next, a data read operation will be described. In this case, low write signals WR1 and WR2 are input to the other input terminals of the NOR circuits NOR1 and NOR2, respectively.
[0100]
When accessing from the bit line BL1, the potential of the bit line BL1 is set to High by precharging, and then the transistor Tr1 is turned on by applying a high voltage to the word line WL1. When high data is stored in the first storage node ND1, no charge is extracted from the bit line BL1. Accordingly, by detecting that the potential of the bit line BL1 after the elapse of a predetermined time is high, high data is read from the first storage node ND1. On the other hand, when low data is stored in the first storage node ND1, charges are extracted from the bit line BL1 to the ground potential through the transistors Tr1 and Tr21 in this order, and the transistor Tr1 from the bit line BL1 The charge is extracted to the ground potential through the one storage node ND1 and the transistor Q4 in this order. Therefore, by detecting that the potential of the bit line BL1 after a predetermined time has passed is low, low data is read from the first storage node ND1.
[0101]
When accessing from the bit line BL2, the potential of the bit line BL2 is set to High by precharging, and then the transistor Tr4 is turned on by applying a high voltage to the word line WL2. When high data is stored in the second storage node ND2, no charge is extracted from the bit line BL2. Accordingly, by detecting that the potential of the bit line BL2 after a predetermined time has elapsed is high, high data is read from the second storage node ND2. On the other hand, when low data is stored in the second storage node ND2, charges are extracted from the bit line BL2 to the ground potential through the transistors Tr4 and Tr22 in this order, and from the bit line BL2 to the transistor Tr4. The charge is extracted to the ground potential through the second storage node ND2 and the transistor Q2 in this order. Therefore, by detecting that the potential of the bit line BL2 after the lapse of a predetermined time is low, low data is read from the second storage node ND2.
[0102]
Thus, according to the memory circuit of the thirteenth embodiment, as shown in FIG. 14, only one transistor Tr1, Tr4 is connected to each of the bit lines BL1, BL2 for each memory cell. Absent. Therefore, the load capacity of the bit lines BL1 and BL2 can be reduced, and the access time can be shortened and the power consumption can be reduced.
[0103]
Also, when reading low data from the first storage node ND1 and reading low data from the second storage node ND2 by the operation of the transistors Tr21 and Tr22 and the NOR circuits NOR1 and NOR2 as selection means. , Charges are extracted from the bit lines BL1 and BL2 through two paths. Therefore, the efficiency of extracting charges from the bit lines BL1 and BL2 is high, and the time required for the read operation can be shortened, so that a high-speed operation can be realized as a whole.
[0104]
In the above description, the memory circuit having the dual port configuration is described, but a memory circuit having a 3-port configuration or more may be used.
[0105]
Embodiment 14 FIG.
FIG. 15 is a circuit diagram showing a memory circuit according to Embodiment 14 of the present invention. The storage circuit according to the fourteenth embodiment is an expansion of the single-ended storage circuit shown in FIG. 13 into a dual-ended configuration. As shown in FIG. 15, the bit lines BL and / BL and the word circuit A line WL, a latch circuit 1, transistors Tr1, Tr4, Tr21, Tr22, and NOR circuits NOR1, NOR2 are provided.
[0106]
The drain electrode of the transistor Tr4 is connected to the bit line / BL. The drain electrode of the transistor Tr22 is connected to the source electrode of the transistor Tr4, the source electrode is connected to the ground potential, and the gate electrode is connected to the output terminal of the NOR circuit NOR2. One input terminal of the NOR circuit NOR2 is connected to the second storage node ND2. A predetermined write signal WR is input to the other input terminal of the NOR circuit NOR2. Other configurations are the same as those in FIG.
[0107]
Hereinafter, an operation of the memory circuit illustrated in FIG. 15 will be described.
[0108]
First, a data write operation will be described. In this case, after the transistors Tr21 and Tr22 are turned off by applying the high write signal WR, the transistors Tr1 and Tr4 are turned on by applying a high voltage to the word line WL. In this state, desired data (for example, High) is written from the bit line BL to the first storage node ND1, and data having a reverse polarity (for example, Low) is written from the bit line / BL to the second storage node ND2. Since both the transistors Tr21 and Tr22 are in an off state in the writing state, a through current does not flow through the path reaching the ground potential via the transistor Tr21 and the path reaching the ground potential via the transistor Tr22, and the high-speed writing operation Is realized.
[0109]
Next, a data read operation will be described. In this case, a low write signal WR is input to the other input terminals of the NOR circuits NOR1 and NOR2.
[0110]
When high data is stored in the first storage node ND1 and low data is stored in the second storage node ND2, no charge is extracted from the bit line BL. Accordingly, by detecting that the potential of the bit line BL is high after a predetermined time has elapsed, high data is read from the first storage node ND1. In this case, charges are extracted from the bit line / BL to the ground potential through the transistors Tr4 and Tr22 in this order, and the transistor Tr4, the second storage node ND2, and the transistor Q2 are connected in this order from the bit line / BL. The charge is extracted to the ground potential. Therefore, by detecting that the potential of the bit line / BL is low after a predetermined time has elapsed, low data is read from the second storage node ND2.
[0111]
On the other hand, when low data is stored in the first storage node ND1 and high data is stored in the second storage node ND2, no charge is extracted from the bit line / BL. Accordingly, by detecting that the potential of the bit line / BL is high after a predetermined time has elapsed, high data is read from the second storage node ND2. In this case, the charge is extracted from the bit line BL to the ground potential via the transistors Tr1 and Tr21 in this order, and from the bit line BL via the transistor Tr1, the first storage node ND1, and the transistor Q4 in this order. Charge is drawn to ground potential. Accordingly, by detecting that the potential of the bit line BL is low after a predetermined time has elapsed, low data is read from the first storage node ND1.
[0112]
Thus, according to the memory circuit of the fourteenth embodiment, as shown in FIG. 15, only one transistor Tr1, Tr4 is connected to each of the bit lines BL, / BL for each memory cell. Not. Therefore, the load capacity of the bit lines BL and / BL can be reduced, and the access time can be shortened and the power consumption can be reduced.
[0113]
Also, when reading low data from the first storage node ND1 and reading low data from the second storage node ND2 by the operation of the transistors Tr21 and Tr22 and the NOR circuits NOR1 and NOR2 as selection means. , Charges are extracted from the bit lines BL1 and BL2 through two paths. Therefore, the efficiency of extracting charges from the bit lines BL1 and BL2 is high, and the time required for the read operation can be shortened, so that a high-speed operation can be realized as a whole.
[0114]
【The invention's effect】
  According to the first aspect of the present invention, when reading Low data from the first storage node,N channelWith the other electrode of the transistorFirstConduction is made between the potential and the charge is extracted from the bit line through this path. Accordingly, since the efficiency of extracting charges from the bit line is increased, the time required for the read operation can be shortened.In addition, the load capacity of the bit line can be reduced, and the access time can be shortened and the power consumption can be reduced.
[0115]
  According to the invention according to claim 2,When reading low data from the first storage node, the other electrode of the first N-channel transistor is electrically connected to the first potential, and charge is extracted from the bit line through this path. Accordingly, the efficiency of extracting charges from the bit line is high, and the time required for the read operation can be shortened, so that a high-speed operation can be realized as a whole. In addition, the load capacity of the bit line can be reduced, and the access time can be shortened and the power consumption can be reduced.
[0116]
  According to the invention according to claim 3,When reading low data from the first storage node, the other electrode of the first N-channel transistor is electrically connected to the first potential, and charge is extracted from the bit line through this path. Accordingly, the efficiency of extracting charges from the bit line is high, and the time required for the read operation can be shortened, so that a high-speed operation can be realized as a whole. In addition, the load capacity of the bit line can be reduced, and the access time can be shortened and the power consumption can be reduced.
[0117]
  Further, according to the invention according to claim 4,A control electrode connected to the first storage node; one electrode connected to the second storage node; and the other electrode connected between the second N-channel transistor and the third N-channel transistor. And a fourth N-channel transistor.
[0118]
  According to the invention according to claim 5,When reading low data from the first storage node and reading data from the second storage node, charges are extracted from the first and second bit lines by two paths, respectively. Accordingly, the efficiency of extracting charges from the first and second bit lines is high, and the time required for the read operation can be shortened, so that a high-speed operation can be realized as a whole. Further, the load capacities of the first and second bit lines can be reduced, and the access time can be shortened and the power consumption can be reduced.
[0119]
  Further, according to the invention according to claim 6,The latch circuit includes a first inverter having a first P-channel transistor and a first other N-channel transistor, and a second inverter having a second P-channel transistor and a second other N-channel transistor. The input terminal of the first inverter and the output terminal of the second inverter are connected to the first storage node, and the output terminal of the first inverter and the input terminal of the second inverter are the second Connected to the storage node.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a memory circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a specific configuration of a latch circuit.
FIG. 3 is a circuit diagram showing a configuration of a memory circuit according to a second embodiment of the present invention.
FIG. 4 is a circuit diagram showing a configuration of a memory circuit according to a third embodiment of the present invention.
FIG. 5 is a circuit diagram showing a configuration of a memory circuit according to a fourth embodiment of the present invention.
FIG. 6 is a circuit diagram showing a configuration of a memory circuit according to a fifth embodiment of the present invention.
FIG. 7 is a circuit diagram showing a configuration of a memory circuit according to a sixth embodiment of the present invention.
FIG. 8 is a circuit diagram showing a configuration of a memory circuit according to a seventh embodiment of the present invention.
FIG. 9 is a circuit diagram showing a configuration of a memory circuit according to an eighth embodiment of the present invention.
FIG. 10 is a circuit diagram showing a configuration of a memory circuit according to a ninth embodiment of the present invention.
FIG. 11 is a circuit diagram showing a configuration of a memory circuit according to a tenth embodiment of the present invention.
FIG. 12 is a circuit diagram showing a configuration of a memory circuit according to Embodiment 11 of the present invention.
FIG. 13 is a circuit diagram showing a configuration of a memory circuit according to a twelfth embodiment of the present invention.
FIG. 14 is a circuit diagram showing a configuration of a memory circuit according to a thirteenth embodiment of the present invention.
FIG. 15 is a circuit diagram showing a configuration of a memory circuit according to a fourteenth embodiment of the present invention.
FIG. 16 is a circuit diagram showing a configuration of a conventional memory circuit.
FIG. 17 is a circuit diagram showing a configuration of a conventional memory circuit.
[Explanation of symbols]
1 latch circuit, ND1 first storage node, ND2 second storage node, BL bit line, WL word line, Tr1 to Tr7, Tr11, Tr12, Tr21, Tr22 transistors, AND1, AND2 AND circuit, NOR1, NOR2 NOR circuit .

Claims (6)

Bit lines,
Word line,
A latch circuit having a first storage node to which data is written and a second storage node to which data having a polarity opposite to that of the data written to the first storage node is written;
A first N-channel transistor having a control electrode connected to the word line, one electrode connected to the bit line, and the other electrode connected to the first storage node;
A second N connected in series between one end connected to the first storage node and the other end connected to a first potential lower than the potential set by precharging the bit line. A channel transistor and a third N-channel transistor;
A control electrode of the second N-channel transistor is connected to the second storage node;
A memory circuit in which a signal for conducting between one electrode and the other electrode of the third N-channel transistor is inputted to the control electrode of the third N-channel transistor in a read state. Bit lines,
Word line,
A latch circuit having a first storage node to which data is written and a second storage node to which data having a polarity opposite to that of the data written to the first storage node is written;
A first N-channel transistor having a control electrode connected to the word line, one electrode connected to the bit line, and the other electrode connected to the first storage node;
A logic circuit having one input terminal connected to the second storage node, the other input terminal to which a predetermined signal indicating whether the latch circuit is in a write state or a read state is input, and an output terminal When,
One electrode connected to the other electrode of the first N-channel transistor, the other electrode connected to a first potential lower than a potential set by precharging the bit line, and the logic circuit A second N-channel transistor having a control electrode connected to the output terminal;
The second N-channel transistor receives a signal output from the logic circuit, and when the predetermined signal indicates a read state, the second N-channel transistor is turned on or off according to the state of the second storage node, A memory circuit which becomes non-conductive when the predetermined signal indicates a writing state. Bit lines,
Word line,
A latch circuit having a first storage node to which data is written and a second storage node to which data having a polarity opposite to that of the data written to the first storage node is written;
A first N-channel transistor having a control electrode connected to the word line, one electrode connected to the bit line, and the other electrode connected to the first storage node;
A logic circuit having one input terminal connected to the first storage node, the other input terminal to which a predetermined signal indicating whether the latch circuit is in a write state or a read state is input, and an output terminal When,
One electrode connected to the other electrode of the first N-channel transistor, the other electrode connected to a first potential lower than a potential set by precharging the bit line, and the logic circuit A second N-channel transistor having a control electrode connected to the output terminal;
The second N-channel transistor receives a signal output from the logic circuit, and when the predetermined signal indicates a read state, the second N-channel transistor is turned on or off according to the state of the first storage node, A memory circuit which becomes non-conductive when the predetermined signal indicates a writing state.   A control electrode connected to the first storage node, one electrode connected to the second storage node, and connected between the second N-channel transistor and the third N-channel transistor The memory circuit according to claim 1, further comprising a fourth N-channel transistor having the other electrode. First and second bit lines;
First and second word lines;
A latch circuit having a first storage node to which data is written and a second storage node to which data having a polarity opposite to that of the data written to the first storage node is written;
A first N-channel transistor having a control electrode connected to the first word line, one electrode connected to the first bit line, and the other electrode connected to the first storage node; ,
First connected in series between one end connected to the first storage node and the other end connected to a first potential lower than the potential set by precharging the first bit line. Two N-channel transistors and a third N-channel transistor;
A fourth N-channel transistor having a control electrode connected to the second word line, one electrode connected to the second bit line, and the other electrode connected to the second storage node; ,
A fifth N-channel transistor and a sixth N-channel transistor connected in series between one end connected to the second storage node and the other end connected to the first potential; And
A control electrode of the second N-channel transistor is connected to the second storage node; a control electrode of the fifth N-channel transistor is connected to the first storage node;
The control electrode of the third N-channel transistor receives a signal for conducting between the one electrode and the other electrode of the third N-channel transistor in the read state,
A memory circuit in which a signal for conducting between one electrode and the other electrode of the sixth N-channel transistor is inputted to the control electrode of the sixth N-channel transistor in a read state. The latch circuit includes a first inverter having a first P-channel transistor and a first other N-channel transistor, and a second inverter having a second P-channel transistor and a second other N-channel transistor. It consists of an inverter and
An input terminal of the first inverter and an output terminal of the second inverter are connected to the first storage node;
The memory circuit according to claim 1, wherein an output terminal of the first inverter and an input terminal of the second inverter are connected to the second storage node.

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