CN113362871B - Nonvolatile memory circuit, memory method and reading method thereof - Google Patents

Nonvolatile memory circuit, memory method and reading method thereof Download PDF

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Publication number
CN113362871B
CN113362871B CN202010146444.1A CN202010146444A CN113362871B CN 113362871 B CN113362871 B CN 113362871B CN 202010146444 A CN202010146444 A CN 202010146444A CN 113362871 B CN113362871 B CN 113362871B
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transistor
bit line
tunnel junction
magnetic tunnel
coupled
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CN113362871A (en
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刘盼盼
张海洋
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1655—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1657—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/18—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using Hall-effect devices

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  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
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Abstract

A nonvolatile memory circuit, a memory method and a reading method thereof, the nonvolatile memory circuit includes: a spin-orbit torque moment magnetic memory comprising a spin hall effect layer having opposite first and second faces, a first magnetic tunnel junction on the first face and a second magnetic tunnel junction on the second face, the spin hall effect layer further comprising first and second ends; a first bit line; a second bit line; a third bit line; a fourth bit line; a switch assembly couples the first end with the first bit line, the second end with the second bit line, and the switch assembly couples the first magnetic tunnel junction with the third bit line, the second magnetic tunnel junction with the fourth bit line. Thus, the cost of the memory is reduced and the performance of the memory is improved.

Description

Nonvolatile memory circuit, memory method and reading method thereof
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a nonvolatile memory circuit, a memory method and a reading method thereof.
Background
Memory is widely used in a variety of electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices, and data servers. The memory may include non-volatile memory or volatile memory.
Nonvolatile memory includes magnetic memory (MRAM) and the like, which allows information to be stored and retained when not connected to a power supply, as compared to volatile memory.
However, existing memory circuits are complex, more devices, and memory performance is poor.
Disclosure of Invention
The invention solves the technical problem of providing a nonvolatile memory circuit, a memory method and a reading method thereof, so as to reduce the cost of a memory and improve the performance of the memory.
In order to solve the above technical problems, the technical solution of the present invention provides a nonvolatile memory circuit, which is characterized by comprising: a spin-orbit torque moment magnetic memory comprising a spin hall effect layer having opposite first and second faces, a first magnetic tunnel junction on the first face and a second magnetic tunnel junction on the second face, the spin hall effect layer further comprising first and second ends; a first bit line; a second bit line; a third bit line; a fourth bit line; a switch assembly couples the first end with the first bit line, the second end with the second bit line, and the switch assembly couples the first magnetic tunnel junction with the third bit line, the second magnetic tunnel junction with the fourth bit line.
Optionally, the first magnetic tunnel junction includes a first free layer on the first face, a first tunnel gate layer on the first free layer, and a first fixed layer on the first tunnel gate layer.
Optionally, the second magnetic tunnel junction includes a second free layer on the second face, a second tunnel gate layer on the second free layer, and a second fixed layer on the second tunnel gate layer.
Optionally, the method further comprises: a first word line; the switch assembly comprises a first transistor, wherein a gate electrode of the first transistor is coupled with the first word line, a source electrode of the first transistor is coupled with the first bit line, and a drain electrode of the first transistor is coupled with the first end.
Optionally, the method further comprises: a third word line and a fourth word line; the switch assembly comprises a third transistor and a fourth transistor, wherein the grid electrode of the third transistor is coupled with the third word line, the source electrode of the third transistor is coupled with the third bit line, the drain electrode of the third transistor is coupled with the first magnetic tunnel junction, the grid electrode of the fourth transistor is coupled with the fourth word line, the source electrode of the fourth transistor is coupled with the fourth bit line, and the drain electrode of the fourth transistor is coupled with the second magnetic tunnel junction.
Optionally, the method further comprises: a third word line; the switch assembly comprises a third transistor and a fourth transistor, wherein the grid electrode of the third transistor and the grid electrode of the fourth transistor are respectively coupled with the third word line, the source electrode of the third transistor is coupled with the third bit line, the drain electrode of the third transistor is coupled with the first magnetic tunnel junction, the source electrode of the fourth transistor is coupled with the fourth bit line, and the drain electrode of the fourth transistor is coupled with the second magnetic tunnel junction.
Optionally, the method further comprises: a second word line; the switch assembly further includes a second transistor having a gate coupled to the second word line, a source coupled to the second bit line, and a drain coupled to the second terminal.
Optionally, the method further comprises: a third word line and a fourth word line; the switch assembly comprises a third transistor and a fourth transistor, wherein the grid electrode of the third transistor is coupled with the third word line, the source electrode of the third transistor is coupled with the third bit line, the drain electrode of the third transistor is coupled with the first magnetic tunnel junction, the grid electrode of the fourth transistor is coupled with the fourth word line, the source electrode of the fourth transistor is coupled with the fourth bit line, and the drain electrode of the fourth transistor is coupled with the second magnetic tunnel junction.
Optionally, the method further comprises: a third word line; the switch assembly comprises a third transistor and a fourth transistor, wherein the grid electrode of the third transistor and the grid electrode of the fourth transistor are respectively coupled with the third word line, the source electrode of the third transistor is coupled with the third bit line, the drain electrode of the third transistor is coupled with the first magnetic tunnel junction, the source electrode of the fourth transistor is coupled with the fourth bit line, and the drain electrode of the fourth transistor is coupled with the second magnetic tunnel junction.
Optionally, the material of the spin hall effect layer comprises a heavy metal material.
Optionally, the material of the first free layer includes CoFeB, the material of the first tunnel gate layer includes MgO, and the material of the first fixed layer includes CoFeB.
Optionally, the material of the second free layer includes CoFeB, the material of the second tunnel gate layer includes MgO, and the material of the second fixed layer includes CoFeB.
Correspondingly, the technical scheme of the invention also provides a storage method based on the nonvolatile storage circuit, which comprises the following steps: conducting the first end with the first bit line, the second end with the second bit line, and the switch assembly disconnecting the first magnetic tunnel junction from the third bit line, the second magnetic tunnel junction from the fourth bit line; a first storage signal is written to the first magnetic tunnel junction through the first bit line or the second bit line, and a second storage signal is written to the second magnetic tunnel junction, the first storage signal having a level higher or lower than a level of the second storage signal.
Correspondingly, the technical scheme of the invention also provides a reading method based on the nonvolatile memory circuit, which comprises the following steps: conducting the first magnetic tunnel junction with the third bit line, the second magnetic tunnel junction with the fourth bit line, and the first terminal with the first bit line, or the second terminal with the second bit line through the switch assembly; a first storage signal within the first magnetic tunnel junction is read through the third bit line, and a second storage signal within the second magnetic tunnel junction is read through the fourth bit line, the first storage signal having a level higher or lower than a level of the second storage signal.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the non-volatile memory circuit provided by the technical scheme of the invention, on one hand, the spin orbit moment magnetic memory comprises a spin Hall effect layer, a first magnetic tunnel junction and a second magnetic tunnel junction, and the first magnetic tunnel junction and the second magnetic tunnel junction are respectively positioned on the first surface and the second surface opposite to the spin Hall effect layer, so that when current passes through the Hall effect layer, the resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction are opposite, namely, the second magnetic tunnel junction is in a low resistance state when the first magnetic tunnel junction is in a high resistance state, the second magnetic tunnel junction is in a high resistance state when the first magnetic tunnel junction is in a low resistance state, and complementary data '1' and data '0' can be stored in the first magnetic tunnel junction and the second magnetic tunnel junction in pairs through one spin orbit moment magnetic memory, and the complementary data '1' and the data '0' can be read out through conducting the first magnetic tunnel junction and a third bit line, and the fourth bit line are conducted, and the data '0' and the data 'are read out and the magnetic memory are respectively read, and the data' and 'data' are read out and the magnetic memory 'are further data' are separated from each other 'are realized, and the data' and 'data' are read out from the magnetic memory is also read through the magnetic tunnel junction and the magnetic tunnel junction is read; on the other hand, since one spin-orbit moment magnetic memory is used to store data in pairs, the number of transistors in the switching element for controlling the respective writing of data can be reduced, thereby reducing the number of devices of the memory and the cost of the memory.
Further, in the spin-orbit moment magnetic memory, in order to write data into the first magnetic tunnel junction and the second magnetic tunnel junction, the current flowing through the spin hall effect layer needs to reach a threshold current, that is, the current flowing from the first terminal to the second terminal, and the current flowing from the second terminal to the first terminal need to be greater than or equal to the threshold current, because the switch assembly further comprises a second transistor, and the gate of the second transistor is coupled to the second word line, the source of the second transistor is coupled to the second bit line, and the drain of the second transistor is coupled to the second terminal, therefore, through the second transistor, on one hand, when writing data into the first magnetic tunnel junction and the second magnetic tunnel junction, the current flowing from the second terminal to the first terminal is reduced, so that the difference between the current flowing from the second terminal to the first terminal and the threshold current is reduced, and on the other hand, the device response time of the memory is faster, and on the other hand, the difference between the current flowing from the second terminal to the first terminal and the second terminal and the threshold current flowing from the second terminal is enabled to be equal, and the difference between the current flowing from the first terminal and the second terminal and the threshold current can be accurately improved. In summary, the performance of the memory is improved by the second transistor.
Drawings
FIG. 1 is a schematic diagram of a circuit configuration of a non-volatile memory circuit;
fig. 2 and 3 are circuit configuration diagrams of a nonvolatile memory circuit according to an embodiment of the present invention.
Detailed Description
As described in the background, existing memory circuits are complex and many devices result in high cost and poor performance of the memory.
Fig. 1 is a schematic circuit diagram of a non-volatile memory circuit.
Referring to fig. 1, the non-volatile memory circuit includes: first word line RWL, second word line WWL, first bit line BL, source line SL, magnetic memory cell, first transistor T1, and second transistor T2.
The magnetic memory cell includes: a hall effect layer HM and a magnetic tunnel junction MTJ at a surface of the hall effect layer, the hall effect layer HM having a first end and a second end.
A second end of the hall effect layer HM is coupled to the source line SL.
The drain of the first transistor T1 is coupled to the first end of the hall effect layer HM, the gate of the first transistor T1 is coupled to the first word line RWL, the drain of the second transistor T2 is coupled to the magnetic tunnel junction MTJ, the gate of the second transistor T2 is coupled to the second word line WWL, and the source of the first transistor T1 and the source of the second transistor T2 are coupled to the first bit line BL.
In the nonvolatile memory circuit, a current runs in a plane through the spin hall effect layer HM, and the direction of the current flow can control the resistance state of the magnetic tunnel junction MTJ1.
When a write operation is performed, the first transistor T1 is turned on by inputting an operating voltage to the first word line RWL, and the first bit line BL and the hall effect layer HM are turned on. Meanwhile, data "0" or data "1" is written into the magnetic tunnel junction MTJ by inputting a high level or a low level to the first bit line BL.
Specifically, by inputting a high level to the first bit line BL, a current is caused to flow from the first end to the second end, thereby causing the magnetic tunnel junction MTJ to be in a high resistance state to write data "1" into the magnetic tunnel junction MTJ; by inputting a low level to the first bit line BL, a current is caused to flow from the second terminal to the first terminal, thereby causing the magnetic tunnel junction MTJ to be in a low resistance state to write data "0" into the magnetic tunnel junction MTJ.
When a read operation is performed, the second transistor T2 is turned on by inputting an operating voltage to the second word line WWL, and the first bit line BL and the magnetic tunnel junction MTJ are turned on, so that the first bit line BL reads and writes data "0" or data "1" of the magnetic tunnel junction MTJ by the resistance state of the magnetic tunnel junction MTJ.
In the above scheme, the first bit line BL is turned on with the first terminal through the first transistor T1 and the magnetic tunnel junction MTJ is turned off with the first bit line BL through the second transistor T2 to implement a write operation, and the first bit line BL is turned off with the first terminal through the first transistor T1 and the magnetic tunnel junction MTJ is turned on with the first bit line BL through the second transistor T2 to implement a read operation, so that a circuit path of the write operation and the read operation of the nonvolatile memory circuit is different, and it is implemented that the nonvolatile memory circuit separately performs the write operation and the read operation.
However, the above-described nonvolatile memory circuit cannot store complementary data "0" and data "1" in pairs. In order to store complementary data "0" and data "1" in pairs, a way of using two sets of the above-described nonvolatile memory circuits is proposed. However, the use of two sets of the above-mentioned nonvolatile memory circuits results in more complicated memory circuits and more devices, which not only increases the cost of the memory, but also increases the heat generation amount of the devices of the memory, so that the performance of the memory is deteriorated, and the difficulty in controlling the memory is also increased.
In order to solve the above problems, the present invention provides a nonvolatile memory circuit that realizes pair-wise storage of complementary data "0" and data "1" by a spin-orbit moment magnetic memory having symmetrical 2 magnetic tunnel junctions, a first bit line, a second bit line, a third bit line, a fourth bit line, and a switch assembly, while reducing the cost of the memory and improving the performance of the memory.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 and 3 are circuit configuration diagrams of a nonvolatile memory circuit according to an embodiment of the present invention.
Referring to fig. 2 and 3, fig. 3 is a schematic diagram of the spin-orbit moment magnetic memory of fig. 2, and the nonvolatile memory circuit includes: a spin-orbit moment magnetic memory, a first bit line BL, a second bit line BLB, a third bit line BLC, a fourth bit line BLD, and a switch assembly.
The spin-orbit moment magnetic memory includes a spin hall effect layer HM having opposite first and second faces 101 and 102, a first magnetic tunnel junction MTJ1 on the first face 101, and a second magnetic tunnel junction MTJ2 on the second face 102, the spin hall effect layer HM further including first and second ends 103 and 104.
A switching assembly coupling the first end 103 with the first bit line BL, the second end 104 with the second bit line BLB, and the switching assembly coupling the first magnetic tunnel junction MTJ1 with the third bit line BLC, the second magnetic tunnel junction MTJ2 with the fourth bit line BLD.
When current flows from the first end 103 to the second end 104, the first magnetic tunnel junction MTJ1 is in a low resistance state and the second magnetic tunnel junction MTJ2 is in a high resistance state, so that a first storage signal can be written at the first magnetic tunnel junction MTJ1, a second storage signal can be written at the second magnetic tunnel junction MTJ2, and the level of the first storage signal is lower than the level of the second storage signal, that is, data "0" is written at the first magnetic tunnel junction MTJ1, and data "1" is written at the second magnetic tunnel junction MTJ2.
When current flows from the second end 104 to the first end 103, the first magnetic tunnel junction MTJ1 is in a high resistance state and the second magnetic tunnel junction MTJ2 is in a low resistance state, so that a first storage signal can be written at the first magnetic tunnel junction MTJ1, a second storage signal can be written at the second magnetic tunnel junction MTJ2, and the level of the first storage signal is higher than the level of the second storage signal, that is, data "1" is written at the first magnetic tunnel junction MTJ1 and data "0" is written at the second magnetic tunnel junction MTJ2.
Accordingly, by conducting the first terminal 103 of one of the spin-orbit moment magnetic memories with the first bit line BL, conducting the second terminal 104 with the second bit line BLB to cause a current to flow from the first terminal 103 to the second terminal 104, or causing a current to flow from the second terminal 104 to the first terminal 103, complementary data "1" and data "0" can be stored in the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2, respectively, in a nonvolatile manner as a pair.
Furthermore, by turning on the first magnetic tunnel junction MTJ1 and the third bit line BLC and turning on the second magnetic tunnel junction MTJ2 and the fourth bit line BLD, the third bit line BLC and the fourth bit line BLD can also be capable of reading complementary data "1" and data "0" stored in the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2.
On the other hand, the first terminal 103 is turned on with the first bit line BL, the second terminal 104 is turned on with the second bit line BLB by the switching element, the first magnetic tunnel junction MTJ1 is turned off with the third bit line BLC by the switching element, and the second magnetic tunnel junction MTJ2 is turned off with the fourth bit line BLD by the switching element, so that the spin-orbit moment magnetic memory can be operated.
The read operation of the spin-orbit moment magnetic memory can be achieved by conducting the first magnetic tunnel junction MTJ1 with the third bit line BLC through the switch assembly, conducting the second magnetic tunnel junction MTJ2 with the fourth bit line BLD through the switch assembly, and conducting the first end 103 with the first bit line BL through the switch assembly, disconnecting the second end 104 from the second bit line BLB through the switch assembly, or conducting the first magnetic tunnel junction MTJ1 with the third bit line BLC through the switch assembly, conducting the second magnetic tunnel junction MTJ2 with the fourth bit line BLD through the switch assembly, and disconnecting the first end 103 with the first bit line BL through the switch assembly, and conducting the second end 104 with the second bit line BLB through the switch assembly.
Thus, the circuit paths of the write operation and the read operation of the spin-orbit moment magnetic memory are different, and the separate write operation and the read operation of the spin-orbit moment magnetic memory are realized.
In summary, by the nonvolatile memory circuit, the number of spin-orbit moment magnetic memories in the memory is reduced and the cost is reduced while the separate memory and read are realized. Moreover, since the data is stored and read in pairs, the speed of storing and reading the data is increased, and the performance of the memory is improved. On the other hand, since one spin-orbit moment magnetic memory is used to store data in pairs, the number of transistors in the switching element for controlling the respective writing of data can be reduced, thereby reducing the number of devices of the memory and the cost of the memory.
In this embodiment, the material of the spin hall effect layer HM includes a heavy metal material, such as platinum, tantalum, or tungsten.
In this embodiment, the first magnetic tunnel junction MTJ1 includes a first free layer 201, a first tunnel gate layer 202, and a first fixed layer 203.
The first free layer 201 is located on the first side 101, the first tunnel gate layer 202 is located on the first free layer 201, and the first fixed layer 203 is located on the first tunnel gate layer 202.
In this embodiment, the material of the first free layer 201 includes CoFeB, the material of the first tunnel gate layer 202 includes MgO, and the material of the first fixed layer 203 includes CoFeB.
In this embodiment, the second magnetic tunnel junction MTJ2 includes a second free layer 301, a second tunnel gate layer 302, and a second fixed layer 303.
The second free layer 301 is located on the second side 102, the second tunnel gate layer 302 is located on the second free layer 301, and the second fixed layer 303 is located on the second tunnel gate layer 302.
In this embodiment, the material of the second free layer 301 includes CoFeB, the material of the second tunnel gate layer 302 includes MgO, and the material of the second fixed layer 303 includes CoFeB.
In this embodiment, the nonvolatile memory circuit further includes a first word line WL.
In this embodiment, the switch component includes a first transistor T1, a gate of the first transistor T1 is coupled to the first word line WL, a source of the first transistor T1 is coupled to the first bit line BL, and a drain of the first transistor T1 is coupled to the first end 103.
Thus, when the operating voltage V is applied to the first word line WL wL To turn on the first transistor T1, the first terminal 103 and the first bit line BL can be turned on.
In this embodiment, the nonvolatile memory circuit further includes a third word line WLC and a fourth word line WLD.
In this embodiment, the switch assembly further includes a third transistor T3 and a fourth transistor T4.
In this embodiment, the gate of the third transistor T3 is coupled to the third word line WLC, the source of the third transistor T3 is coupled to the third bit line BLC, and the drain of the third transistor T3 is coupled to the first magnetic tunnel junction MTJ1.
In this embodiment, the gate of the fourth transistor T4 is coupled to the fourth word line WLD, the source of the fourth transistor T4 is coupled to the fourth bit line BLD, and the drain of the fourth transistor T4 is coupled to the second magnetic tunnel junction MTJ2.
Thus, when an operating voltage VDD is applied to the third word line WLC to turn on the third transistor T3, the first magnetic tunnel junction MTJ1 and the third bit line BLC can be turned on; when an operating voltage VDD is applied to the fourth word line WLD to turn on the fourth transistor T4, the second magnetic tunnel junction MTJ2 and the fourth bit line BLD can be turned on. Also, by controlling the third word line WLC and the fourth word line WLD, respectively, it is also possible to read data stored in the first magnetic tunnel junction MTJ1 alone or to read data stored in the second magnetic tunnel junction MTJ2 alone.
In another embodiment, the nonvolatile memory circuit does not include a fourth word line, and the gate of the third transistor and the gate of the fourth transistor are coupled to the third word line, respectively, the source of the third transistor is coupled to the third bit line, the drain of the third transistor is coupled to the first magnetic tunnel junction, the source of the fourth transistor is coupled to the fourth bit line, and the drain of the fourth transistor is coupled to the second magnetic tunnel junction. Accordingly, when an operating voltage is applied to the third word line, the third transistor and the fourth transistor can be turned on simultaneously, thereby simplifying control of the memory and reducing the number of devices in the nonvolatile memory circuit to reduce the cost of the memory.
In this embodiment, the nonvolatile memory circuit further includes a second word line WLB.
In this embodiment, the switch assembly further includes a second transistor T2, a gate of the second transistor T2 is coupled to the second word line WLB, a source of the second transistor T2 is coupled to the second bit line BLB, and a drain of the second transistor T2 is coupled to the second terminal 104.
Thus, the second terminal 104 and the second bit line BLB can be turned on by applying the operating voltage VDD to the second word line WLB to turn on the second transistor T2.
Furthermore, in the spin-orbit moment magnetic memory, in order to write data into the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2, the current flowing through the spin hall effect layer HM needs to reach a threshold current, that is, the current flowing from the first terminal 103 to the second terminal 104, and the current flowing from the second terminal 104 to the first terminal 103 need to be greater than or equal to the threshold current. Since the switching assembly further includes a second transistor T2, and the gate of the second transistor T2 is coupled to the second word line WLB, the source of the second transistor T2 is coupled to the second bit line BLB, and the drain of the second transistor T2 is coupled to the second terminal 104, by the second transistor T2, on the one hand, when writing data into the first and second magnetic tunnel junctions MTJ1 and MTJ2, a current flowing from the second terminal 104 to the first terminal 103 can be reduced, thereby reducing a current difference between a current flowing from the second terminal 104 to the first terminal 103 and a threshold current, so that a device reaction time of the memory is faster; on the other hand, the devices coupled to both ends of the spin hall effect layer HM can be made symmetrical, so that the current difference between the current flowing from the first terminal 103 to the second terminal 104 and the threshold current, and the current difference between the current flowing from the second terminal 104 to the first terminal 103 and the threshold current can be equal, thereby improving the accuracy of the data written in the memory. Meanwhile, since the devices coupled to both ends of the spin hall effect layer HM are symmetrical, when the nonvolatile memory circuit performs a read operation, a read path passes through any one of both ends (the first end 103 or the second end 104) of the spin hall effect layer HM, and the read path needs to pass through one transistor (the first transistor T1 or the second transistor T2), which has the same loss, thereby improving the reliability during the read operation. In summary, the performance of the memory is improved by the second transistor T2.
Correspondingly, the embodiment of the invention further provides a storage method based on the nonvolatile storage circuit, please continue to refer to fig. 2 and fig. 3, which includes:
turning on the first terminal 103 and the first bit line BL, turning on the second terminal 104 and the second bit line BLB, and turning off the first magnetic tunnel junction MTJ1 and the third bit line BLC, and turning off the second magnetic tunnel junction MTJ2 and the fourth bit line BLD, by the switching component;
a first storage signal is written to the first magnetic tunnel junction MTJ1 through the first bit line BL or the second bit line BLB, and a second storage signal is written to the second magnetic tunnel junction MTJ2, the level of the first storage signal being higher or lower than the level of the second storage signal.
Specifically, by inputting a high level to the first bit line BL and a low level to the second bit line BLB, it is possible to control a current to flow from the first end 103 to the second end 104 of the spin hall effect layer HM, thereby making the first magnetic tunnel junction MTJ1 a low resistance state and the MTJ2 a high resistance state, it is achieved that a first storage signal is written at the first magnetic tunnel junction MTJ1, a second storage signal is written at the second magnetic tunnel junction MTJ2, and the level of the first storage signal is lower than the level of the second storage signal, that is, data "0" is written at the first magnetic tunnel junction MTJ1, and data "1" is written at the second magnetic tunnel junction MTJ2.
Accordingly, by inputting a low level to the first bit line BL and a high level to the second bit line BLB, it is possible to control a current to flow from the second end 104 of the spin hall effect layer HM to the first end 103, thereby making the first magnetic tunnel junction MTJ1 in a high resistance state and the MTJ2 in a low resistance state, it is achieved that a first storage signal is written at the first magnetic tunnel junction MTJ1, a second storage signal is written at the second magnetic tunnel junction MTJ2, and the level of the first storage signal is higher than the level of the second storage signal, that is, data "1" is written at the first magnetic tunnel junction MTJ1 and data "0" is written at the second magnetic tunnel junction MTJ2.
Since the first terminal 103 can be turned on with the first bit line BL, the second terminal 104 can be turned on with the second bit line BLB, and the switch assembly can turn off the first magnetic tunnel junction MTJ1 from the third bit line BLC and the second magnetic tunnel junction MTJ2 from the fourth bit line BLD, the write operation and the read operation of the spin-orbit moment magnetic memory are different in circuit paths, and the separate write operation and the read operation of the spin-orbit moment magnetic memory are realized.
Correspondingly, the embodiment of the invention further provides a reading method based on the nonvolatile memory circuit, please continue to refer to fig. 2 and fig. 3, which includes:
conducting the first magnetic tunnel junction MTJ1 with the third bit line BLC, the second magnetic tunnel junction MTJ2 with the fourth bit line BLD, and the first terminal 103 with the first bit line BL, or the second terminal 104 with the second bit line BLB, by the switching component;
a first storage signal within the first magnetic tunnel junction MTJ1 is read through the third bit line BLC, and a second storage signal within the second magnetic tunnel junction MTJ2 is read through the fourth bit line BLD, the first storage signal having a level higher or lower than a level of the second storage signal.
Thus, reading a first storage signal in the first magnetic tunnel junction MTJ1 and a second storage signal in the second magnetic tunnel junction MTJ2, i.e., reading the stored complementary data "1" and data "0", by the spin-orbit moment magnetic memory is achieved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (12)

1. A nonvolatile memory circuit, comprising:
a spin-orbit torque moment magnetic memory comprising a spin hall effect layer having opposite first and second faces, a first magnetic tunnel junction on the first face and a second magnetic tunnel junction on the second face, the spin hall effect layer further comprising first and second ends;
a first bit line;
a second bit line;
a third bit line;
a fourth bit line;
a switch assembly coupling the first end with the first bit line, the second end with the second bit line, and the switch assembly coupling the first magnetic tunnel junction with the third bit line, the second magnetic tunnel junction with the fourth bit line;
conducting the first end with the first bit line, the second end with the second bit line, and the switch assembly disconnecting the first magnetic tunnel junction from the third bit line, the second magnetic tunnel junction from the fourth bit line;
writing a first storage signal to the first magnetic tunnel junction through the first bit line or the second bit line, and writing a second storage signal to the second magnetic tunnel junction, the first storage signal having a level higher or lower than a level of the second storage signal;
conducting the first magnetic tunnel junction with the third bit line, the second magnetic tunnel junction with the fourth bit line, and the first terminal with the first bit line, or the second terminal with the second bit line through the switch assembly;
a first storage signal within the first magnetic tunnel junction is read through the third bit line, and a second storage signal within the second magnetic tunnel junction is read through the fourth bit line, the first storage signal having a level higher or lower than a level of the second storage signal.
2. The non-volatile memory circuit of claim 1, wherein the first magnetic tunnel junction comprises a first free layer on the first face, a first tunnel gate layer on the first free layer, and a first fixed layer on the first tunnel gate layer.
3. The non-volatile memory circuit of claim 1, wherein the second magnetic tunnel junction comprises a second free layer on the second face, a second tunnel gate layer on the second free layer, and a second fixed layer on the second tunnel gate layer.
4. The non-volatile memory circuit of claim 1, further comprising: a first word line; the switch assembly comprises a first transistor, wherein a gate electrode of the first transistor is coupled with the first word line, a source electrode of the first transistor is coupled with the first bit line, and a drain electrode of the first transistor is coupled with the first end.
5. The non-volatile memory circuit of claim 4, further comprising: a third word line and a fourth word line; the switch assembly comprises a third transistor and a fourth transistor, wherein the grid electrode of the third transistor is coupled with the third word line, the source electrode of the third transistor is coupled with the third bit line, the drain electrode of the third transistor is coupled with the first magnetic tunnel junction, the grid electrode of the fourth transistor is coupled with the fourth word line, the source electrode of the fourth transistor is coupled with the fourth bit line, and the drain electrode of the fourth transistor is coupled with the second magnetic tunnel junction.
6. The non-volatile memory circuit of claim 4, further comprising: a third word line; the switch assembly comprises a third transistor and a fourth transistor, wherein the grid electrode of the third transistor and the grid electrode of the fourth transistor are respectively coupled with the third word line, the source electrode of the third transistor is coupled with the third bit line, the drain electrode of the third transistor is coupled with the first magnetic tunnel junction, the source electrode of the fourth transistor is coupled with the fourth bit line, and the drain electrode of the fourth transistor is coupled with the second magnetic tunnel junction.
7. The non-volatile memory circuit of claim 4, further comprising: a second word line; the switch assembly further includes a second transistor having a gate coupled to the second word line, a source coupled to the second bit line, and a drain coupled to the second terminal.
8. The non-volatile memory circuit of claim 7, further comprising: a third word line and a fourth word line; the switch assembly comprises a third transistor and a fourth transistor, wherein the grid electrode of the third transistor is coupled with the third word line, the source electrode of the third transistor is coupled with the third bit line, the drain electrode of the third transistor is coupled with the first magnetic tunnel junction, the grid electrode of the fourth transistor is coupled with the fourth word line, the source electrode of the fourth transistor is coupled with the fourth bit line, and the drain electrode of the fourth transistor is coupled with the second magnetic tunnel junction.
9. The non-volatile memory circuit of claim 7, further comprising: a third word line; the switch assembly comprises a third transistor and a fourth transistor, wherein the grid electrode of the third transistor and the grid electrode of the fourth transistor are respectively coupled with the third word line, the source electrode of the third transistor is coupled with the third bit line, the drain electrode of the third transistor is coupled with the first magnetic tunnel junction, the source electrode of the fourth transistor is coupled with the fourth bit line, and the drain electrode of the fourth transistor is coupled with the second magnetic tunnel junction.
10. The non-volatile memory circuit of claim 1, wherein the material of the spin hall effect layer comprises a heavy metal material.
11. The non-volatile memory circuit of claim 2, wherein the material of the first free layer comprises CoFeB, the material of the first tunnel gate layer comprises MgO, and the material of the first fixed layer comprises CoFeB.
12. The nonvolatile memory circuit of claim 3 wherein the material of the second free layer comprises CoFeB, the material of the second tunnel gate layer comprises MgO, and the material of the second fixed layer comprises CoFeB.
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