JP3256868B2 - Static semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high threshold voltage MO.
A flip-flop formed by cross-connecting inverters using S transistors, and a pair of high threshold voltages connected between a pair of storage nodes of the flip-flop and a pair of bit lines and controlled by the potential of a word line. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static semiconductor memory having a memory cell composed of a selection MOS transistor, and more particularly to a static semiconductor capable of high-speed operation without increasing a leakage current in a standby mode even at a low power supply voltage as in a portable device. It is about memory.

[0002]

2. Description of the Related Art An access time is one of indexes indicating the performance of a semiconductor memory. The access time is the time required to read and write data from and to a memory cell at a specified address. The main factor that determines the access time is the configuration of the memory cell. FIG. 5 shows a configuration of a conventional memory cell and its peripheral portion.

In FIG. 5, 1 'is a memory cell, 2 is a data input / output circuit, WL1 is a word line for transmitting a selection signal of the memory cell 1', and BL1, * BL1 transmit data in the form of a differential signal. A pair of bit lines, Cb1 and * Cb1, are parasitic capacitances of the bit lines BL1 and * BL1. The memory cell 1 ′ includes two high threshold voltage inverters 3 and 4 and two high threshold voltage N-type field effect transistors (hereinafter, MOS transistors) functioning as a pair of select MOS transistors.
Called a transistor. ) Q1 and Q2.

[0004] The two inverters 3 and 4 form a flip-flop by a cross connection (anti-parallel connection) connecting one input to the other output. In this flip-flop, one of two storage nodes where the input terminals and the output terminals of the inverters 3 and 4 are commonly connected becomes "H" (high-level voltage) and the other becomes "L" (low-level voltage). It has a property, and stores 1-bit information depending on the difference in the circuit state.

Although a large number of memory cells are usually connected to the pair of bit lines BL1 and * BL1, they are omitted in FIG. 5 and only one memory cell 1 'close to the data input / output circuit 2 is shown. are doing. The parasitic capacitances Cb1 and * Cb1 increase according to the number of memory cells connected to the bit lines BL1 and * BL1.

The data reading from the memory cell 1 'is as follows. First, all word lines WL1 are controlled to a non-selected state ("L"), and the bit lines BL1 are
1, * BL1 is precharged equally to a constant level. Thereafter, only the word line WL1 of the memory 1 ′ to be read is controlled to the selected state (“H”).

As a result, the MOS transistor Q1 or Q2 is turned on in accordance with the stored contents of the memory cell 1 ', and the charge on the bit line BL1 or * BL1 is transferred to the memory cell 1' via the turned on MOS transistor Q1 or Q2. Flow into As a result, the potential of the bit line BL1 or * BL1 connected to the conductive MOS transistor side gradually decreases. Usually, the change in the potential of the bit line is extremely slow. Since the other of the bit lines BL1 and * BL1 maintains the potential at the time of precharging, the bit line BL forming the pair
1, * 1 is detected by a highly sensitive sense circuit provided in the data input / output circuit 2 to increase the speed.

The signal detected by the sense circuit is output from the data input / output circuit 2 to the outside as read data. The data input / output circuit 2 also includes a write circuit for writing input data to the memory cell 1 '. However, since a memory access time is determined by a read operation, a description thereof will be omitted.

[0009]

However, in portable equipment, there has been a demand for smaller and lighter portable devices, so that one NiCad battery (1.2%) is required.
It is necessary to operate the memory at a low voltage of V). However, the memory is designed with a power supply voltage of 5 to 3 V as a standard, and when this is reduced to 1.2 V, the access time is significantly increased.

On the other hand, it is possible to improve by lowering the threshold voltage of the MOS transistor in accordance with the power supply voltage. However, according to this, the sub-threshold current of the MOS transistor (the source / source current when the MOS transistor is non-conductive) is improved. The leakage current flowing between the drains increases exponentially. Since this sub-threshold current becomes the current consumption of the memory in the standby state, when it is necessary to minimize the consumption of the battery during the standby time as in a portable device, simply lowering the threshold voltage of the MOS transistor is a problem. is there.

An object of the present invention is to provide a static semiconductor memory capable of solving the above-mentioned problem and speeding up data reading from a memory cell without increasing power consumption in a standby state. Is what you do.

[0012]

According to a first aspect of the present invention, there is provided a flip-flop formed by cross-connecting inverters using MOS transistors having a high threshold voltage, a pair of storage nodes of the flip-flop, and a first pair of memory nodes. A static semiconductor memory including a memory cell including a pair of first selection MOS transistors having a high threshold voltage and controlled by the potential of a first word line and connected between the bit line and a first word line. Two pairs of selection MOS transistors and a pair of low threshold voltage drive MOS transistors are added to the memory cell, and a pseudo power supply line and a high threshold voltage switch MOS transistor connected between the pseudo power supply line and ground are provided. , The second pair of selections M
Each of the OS transistors is connected between each of the first pair of bit lines and each of the pair of drive MOS transistors, and is controlled by the potential of the first word line; Are connected between each of the second pair of select MOS transistors and the pseudo ground line, and are controlled by the potential of each storage node of the flip-flop, and the high threshold voltage switch MOS transistor is When the memory cell is selected, it is made conductive, so that the memory cell is configured as a static semiconductor memory.

In a second aspect based on the first aspect, each of the second pair of select MOS transistors is connected to a second pair of bits in place of the first pair of bit lines, and The semiconductor memory is configured to be controlled by a second word line instead of the first word line.

In a third aspect based on the first aspect, each of the second pair of select MOS transistors is connected to the first pair of the select MOS transistors.
Instead of the pair of bit lines, one of them is connected to a third bit line, the other is connected to a fourth bit line, and one of the second pair of select MOS transistors is connected to a third word line. This is configured as a static semiconductor memory characterized in that it is controlled and the other is controlled by a fourth word line.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a circuit diagram showing a static semiconductor memory according to a first embodiment of the present invention. The same components as those shown in FIG. 5 are denoted by the same reference numerals. Reference numeral 1 denotes a memory cell which is different from the configuration of the memory cell 1 'shown in FIG. 5 in that a second pair of low threshold voltage selection N-type MOS transistors Q4 and Q5 and a pair of low threshold voltage N-type drive MOS transistors Q5, Q6
And a pseudo ground line 5 is provided so as to run in parallel with the pair of bit lines BL1 and * BL1.

The sources of the MOS transistors Q5 and Q6 are connected to the pseudo ground line 5, and the sub-threshold leakage current when the connection between the pseudo ground line 5 and the ground is not a problem does not matter. They are connected by an N-type MOS transistor Q7 having a high threshold voltage. This transistor Q7 is provided at the peripheral portion of the memory cell array, and unlike the memory cell 1, there is little restriction on the transistor size. That is, although a MOS transistor having a high threshold voltage is applied, the resistance during conduction can be sufficiently reduced by setting the channel width to be large.

Reading of data from the memory cell 1 is as follows. For convenience of explanation, the output of the inverter 3 is “H” and the output of the inverter 4 is “L”. First, all the word lines WL1 are controlled to be in a non-selected state ("L"), and the bit lines BL1, * BL1 are precharged equally to a constant level using appropriate means.

After that, only the word line WL1 of the memory cell 1 to be read is controlled to the selected state ("H"). Since the storage contents of the memory cell 1 are as described above,
The transistor Q1 is turned on, and the charge of the bit line BL1 flows into the memory cell 1 via the transistor Q1. At the same time, the transistors Q3 and Q5 are also turned on. By controlling the transistor Q7 to be turned on, a discharge path to the ground is opened, and the discharging operation of the bit line BL1 can be speeded up.

The other bit line * BL1 keeps the potential at the time of precharge. Detecting the potential difference between the bit lines BL and * BL with a high-sensitivity sense circuit provided in the data input / output circuit 2 to increase the speed is the same as described in the related art.

To write data to the memory cell 1,
The write circuit of the data input / output circuit 2 is used. That is, in a state where the word line WL1 of the memory cell 1 to be written is selected (“H”), one of the pair of bit lines BL1 and * BL1 is set to “L” and the other is set to “H” according to the input data. Control. By this operation, the state of the flip-flop is forcibly set to one of the states. Regardless of the state of the flip-flop, any of the transistors Q5 and Q6 is always in a non-conductive state, so that the addition of the MOS transistors Q3 to Q6 does not hinder the write operation.

As described above, by controlling the MOS transistor Q7 to be conductive, the operation (discharge) of the bit line can be accelerated when data is read from the memory cell 1. There is no particular restriction on the timing of activation of the MOS transistor Q7, but from the viewpoint of shortening the access time, it is sufficient if the memory cell 1 can be activated before being selected by the word line WL1. As a method for activating the MOS transistor Q7, for example, a chip select signal supplied from the outside can be used. When multiplexing the bit lines BL1 and * BL1,
The column signal specifying bit lines BL1 and * BL1 is
It can be used for controlling the S transistor Q7.

In the standby state, the pair of bit lines BL1 and * BL1 are normally controlled to the precharge state unless otherwise specified. That is, the bit lines BL1, * B
L1 is connected to the power supply. At this time, a transistor Q7 realized by a high threshold voltage MOS transistor
, The leakage current path to the ground can be interrupted. This makes it possible to realize a high-speed memory even at a low voltage without a leak current at the time of standby.

[Second Embodiment] FIG. 2 shows a second embodiment of the present invention.
FIG. 2 is a circuit diagram showing a static semiconductor memory according to an embodiment. The basic configuration is the same as that shown in FIG. 1, except that pseudo ground line 5 is provided so as to run in parallel with word line WL1. Q7 'is an N-type MOS transistor having a threshold voltage high enough to ignore the sub-threshold leakage current at the time of interruption. A chip select signal can be used for controlling the conduction / interruption of the MOS transistor Q7 '. It is also possible to apply the word line selection signal to the control signal for the MOS transistor Q7 '. The ability to speed up the read operation without increasing the leakage current during standby is similar to the circuit of FIG. 1 and has the same effect.

[Third Embodiment] FIG. 3 shows a third embodiment of the present invention.
FIG. 4 is a diagram showing a memory according to the embodiment. Here, an example in which the present invention is applied to a two-port memory is shown. Figure 1 shows the basic configuration
And a second pair of selecting MOSs.
The difference is that the gate electrodes of the transistors Q3 and Q4 are connected to a word line WL2 of another port, and the drains are connected to a pair of bit lines BL2 and * BL2 of another port. By applying a pair of bit lines BL1 and * BL1 to a write port and a pair of bit lines BL2 and * BL2 capable of high-speed operation to a read port, data can be written and read at the same time. is there. Cb2, *
Cb2 is a parasitic capacitance of the bit lines BL2, * BL2.

[Fourth Embodiment] FIG. 4 shows a fourth embodiment of the present invention.
FIG. 4 is a diagram showing a memory according to the embodiment. Here, an example in which the present invention is applied to a three-port memory is shown. The configuration of the two-port memory shown in FIG. 3 is different from that of the two-port memory in that the gate electrodes of the second selection MOS transistors Q3 and Q4
3 is different in that it is connected to WL4. Cb3, Cb
Reference numeral 4 denotes a parasitic capacitance of the bit lines BL3 and BL4. By using a pair of bit lines BL1 and * BL1 as a write port and using single bit lines BL3 and BL4 capable of high-speed operation as a read port, a three-port memory for simultaneously writing data and reading two data can be provided. realizable.

In the memory shown in FIG. 4, since the read port has a single bit line configuration, it is disadvantageous in terms of speed performance as compared with the memory of FIG. 3 using a pair bit line configuration. However, as is well known, the speed performance can be improved by forming a pseudo differential signal in which the signal of the single bit line and the reference voltage are combined.

[Other Embodiments] In the third and fourth embodiments, as described in the embodiment of FIG. 2, the pseudo ground line 5 may be provided side by side with the word line WL. It is possible and has a similar effect.

[0028]

As described above, according to the present invention, a high-speed operation can be realized without increasing the leakage current during standby even with a low-voltage power supply. For this reason, there is a great advantage that high-speed operation can be performed while suppressing battery consumption during a standby period, for use in an application such as a portable device in which current consumption in a standby state poses a problem.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a static semiconductor memory according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a static semiconductor memory according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a static semiconductor memory according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a static semiconductor memory according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a conventional static semiconductor memory.

[Explanation of symbols]

1, 1 ': memory cell, 2, 2', 2 ": data input / output circuit, 3, 4: inverter constituted by MOS transistor with high threshold voltage, 5: pseudo ground line, Q1, Q2, Q
7, Q7 ': high threshold voltage N-type MOS transistor, Q
3-Q6: N-type MOS transistor with low threshold voltage.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/41-11/4197

Claims (3)

(57) [Claims] A first flip-flop connected between a pair of storage nodes of the flip-flop and a first pair of bit lines; In a static semiconductor memory including a memory cell including a pair of first selection MOS transistors having a high threshold voltage controlled by the potential of the word line, a second pair of selection MOS transistors having a low threshold voltage and a low threshold voltage A pair of drive MOS transistors having a high voltage and a high threshold voltage switch M connected between the pseudo power supply line and the ground.
An OS transistor is provided, and each of the second pair of select MOS transistors is connected to each of the first pair of bit lines and the pair of drives M.
Connected between each of the OS transistors and controlled by the potential of the first word line, and each of the pair of drive MOS transistors is connected to each of the second pair of select MOS transistors and the pseudo ground line. Wherein the high-threshold voltage switch MOS transistor is turned on when the memory cell is selected, and is controlled by the potential of each storage node of the flip-flop. Semiconductor memory. 2. A method according to claim 1, wherein each of said second pair of select MOS transistors is connected to a second pair of bits in place of said first pair of bit lines, and said second pair of select MOS transistors is connected in place of said first word line. 2. The static semiconductor memory according to claim 1, wherein said static semiconductor memory is controlled by two word lines. 3. Each of said second pair of select MOS transistors is replaced with said first pair of bit lines, one of which is connected to a third bit line and the other is connected to a fourth bit line. 2. The static semiconductor according to claim 1, wherein one of said second pair of select MOS transistors is controlled by a third word line and the other is controlled by a fourth word line. memory.