JP4449264B2 - Interface circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an interface circuit having a function of protecting a circuit from a surge voltage such as static electricity.
[0002]
[Prior art]
FIG. 2 shows an example of a conventional interface circuit 1, which is connected between an input-side NOT gate 2 and an output-side NOT gate 3. The interface circuit 1 includes a CMOS inverter 4 fed from a power supply terminal Vc1, a CMOS inverter 5 fed from a power supply terminal Vc2, and a diode 6 connected between the output terminal 4a and the power supply terminal Vc2 of the inverter circuit 4. It is composed of
[0003]
With such a configuration, even if a surge voltage such as static electricity is applied to the power supply terminal Vc1 for some reason, the current due to the surge voltage is guided from the power supply terminal Vc1 side to the power supply terminal Vc2 to protect the gate of the CMOS inverter 5. Can do.
[0004]
[Problems to be solved by the invention]
By the way, in the above-described circuit, when a power source connected to each of the power source terminals Vc1 and Vc2 is shared, the power source must be turned off in order to reduce current consumption. At this time, both CMOS inverters 4 and 5 are not supplied with power, but there is a desire to maintain the standby state described below.
[0005]
In the standby state, the power supply terminals Vc1 and Vc2 of the CMOS inverters 4 and 5 are supplied with power from different power sources, the CMOS inverter 4 is supplied with power, and the CMOS inverter 5 is not supplied with power. It shows that it saves electricity. However, when the standby state is set in this way, the following problems occur in the circuit configuration described above.
[0006]
The power supply Vcc1 supplied from the power supply terminal Vc1 supplies power to the power supply terminal Vc2 via the diode 6 when the level of the input signal of the CMOS inverter 5 is high. Therefore, a voltage of Vcc1-Vf [V] is generated between the power supply terminals Vc2-GND. The NOT gate 3 is driven by the voltage Vcc1-Vf [V] generated between the power supply terminals Vc2 and GND, and current is consumed even in the standby state, so that the current consumption cannot be reduced. Occurs.
[0007]
The present invention has been made in view of the above circumstances, and an object thereof is to provide an interface circuit capable of reducing current consumption while preventing destruction of internal elements due to surge voltage such as static electricity.
[0008]
[Means for Solving the Problems]
According to the interface circuit of the first aspect, power is supplied to the first power supply terminal, and the second power supply terminal is set to a non-power supply state, thereby supplying power only to the first CMOS inverter and maintaining the standby state. If the power supply voltage is applied to the input terminal of the second CMOS inverter, the voltage between the second power supply terminal and the second power supply terminal is set so as not to exceed a predetermined level. pin unpowered state is maintained, power is not supplied to other circuits connected to the second power supply pin, the current consumption can be reduced while maintaining the standby state.
[0009]
When a surge voltage such as static electricity is applied from the first power supply terminal, the voltage limiting means becomes conductive when the surge voltage exceeds a predetermined level, and the current caused by the surge voltage is supplied from the first power supply terminal to the second power supply terminal. Guided to the power terminal. Thereby, destruction of internal elements such as the second CMOS inverter due to the surge voltage can be prevented.
[0010]
According to the interface circuit of the second aspect, by providing two Zener diodes as voltage limiting means, when a voltage higher than the second power supply terminal is applied to the input terminal of the second CMOS inverter, the Zener The voltage is summed with the sum of the voltage and the forward voltage, and the effect of the invention of claim 1 can be obtained without complicating the configuration.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIG.
FIG. 1 shows the electrical configuration of the interface circuit 11. The interface circuit 11 includes a CMOS inverter 13 connected to the output terminal 12 a of the NOT gate 12, a CMOS inverter 14 to which the input terminal 14 a is connected to the output terminal of the CMOS inverter 13, and the like. The output terminal of the CMOS inverter 14 is connected to the input terminal of the NOT gate 15.
[0012]
In the CMOS inverter 13, for example, a P-channel MOS transistor 13b and an N-channel MOS transistor 13c are connected in series between a power supply terminal Vc1 (first power supply terminal) to which a power supply voltage Vcc1 of 3 V is applied and the ground. The gates of the MOS transistors 13b and 13c are connected in common to serve as an input terminal, and the common drain is used as an output terminal and is connected to the input terminal 14a of the CMOS inverter 14.
[0013]
Similarly, the CMOS inverter 14 includes a P-channel MOS transistor 14b and an N-channel MOS transistor 14c connected in series between a power supply terminal Vc2 (second power supply terminal) and the ground. The gates of the MOS transistors 14b and 14c are connected in common to serve as the input terminal 14a, and the common drain serves as the output terminal 14d. A Zener diode 16 and a Zener diode 17 are connected in series in the opposite direction between the power supply terminal Vc2 and the input terminal 14a. The Zener diodes 16 and 17 constitute the voltage limiting means 18 in the present invention. In the following description, it is assumed that the forward voltage Vf of each of the Zener diodes 16 and 17 is 0.6 V, for example, and the Zener voltage Vz is 6 V. At this time, the predetermined level is (Zener voltage Vz of Zener diode 17) + (Forward voltage Vf of Zener diode 16) = 6.6V. Different power supply circuits (not shown) are connected to the power supply terminal Vc1 and the power supply terminal Vc2, and supply power supply voltages Vcc1 and Vcc2, respectively.
[0014]
The operation of the above configuration will be described.
When power supply voltages Vcc1 and Vcc2 are applied between power supply terminal Vc1 and ground and between power supply terminal Vc2 and ground, NOT gates 12 and 15 and CMOS inverters 13 and 14 operate.
[0015]
When the standby state is set, power is not supplied to the power supply terminal Vc2 while the power supply voltage Vcc1 (= 3V) is supplied to the power supply terminal Vc1.
[0016]
At this time, when a ground level (voltage 0 V) is input as an input to the NOT gate 12, the voltage at the output terminal 12a becomes Vcc1 [V] by the NOT gate 12, and the input terminal 14a of the CMOS inverter 14 matches the ground level. . At this time, since the power supply voltage Vcc2 is not supplied to the power supply terminal Vc2, the CMOS inverter 14 does not operate.
[0017]
When the voltage Vcc1 [V] is input as the input of the NOT gate 12, the output terminal 12a becomes the ground level by the NOT gate 12, and the voltage of the input terminal 14a of the CMOS inverter 14 becomes approximately Vcc1 [V].
[0018]
At this time, since the potential difference (= 3V) between the potential of the input terminal 14a of the CMOS inverter 14 and the potential of the second power supply terminal Vc2 does not exceed 6.6V, the input terminal 14a of the CMOS inverter 14 is connected to the power supply terminal. No power is supplied to Vc2. That is, since power is not supplied to the NOT gate 15 connected to the power supply terminal Vc2, the standby state is maintained.
[0019]
On the other hand, when a surge voltage such as static electricity is applied from the power supply terminal Vc1, when the surge voltage becomes 6.6 V or more, the voltage is clamped by this voltage, and the current due to the surge voltage is applied to a power supply circuit (not shown) on the power supply terminal Vc2 side. Guided surge voltage can be released. At this time, the gates of the MOS transistors 14b and 14c are protected.
[0020]
According to such an embodiment, when the input terminal 14a of the CMOS inverter 14 becomes Vcc1 (= 3V), the voltage to the power supply terminal Vc2 is 6.6V (Zener voltage Vz + forward voltage Vf) or more. Therefore, the voltage is not supplied from the input terminal 14a of the CMOS inverter 14 to the power supply terminal Vc2, and the current consumption can be reduced while maintaining the standby state.
[0021]
Further, when a surge voltage such as static electricity is applied from the power supply terminal Vc1, the conductive state is established when the surge voltage becomes 6.6 V or more, and the current due to the surge voltage is guided from the power supply terminal Vc1 to the power supply terminal Vc2. Therefore, it is possible to prevent the gate of the CMOS inverter 14 from being destroyed by the surge voltage. Further, since the two Zener diodes 16 and 17 are used, the configuration is not complicated.
[0022]
The power supply voltages applied to the power supply terminal Vc1 and the power supply terminal Vc2 may be the same or different.
[Brief description of the drawings]
FIG. 1 is an electrical configuration diagram showing an embodiment of the present invention. FIG. 2 is a diagram corresponding to FIG. 1 showing a conventional example.
11 is an interface circuit, 12 and 13 are NOT gates, 14 is a CMOS inverter (first CMOS inverter), 15 is a CMOS inverter (second CMOS inverter), 16 and 17 are zener diodes, 18 is voltage limiting means, and Vc1 Is a first power supply terminal, and Vc2 is a second power supply terminal.

Claims (2)

A first CMOS inverter to which power is supplied from a first power supply terminal;
A power supply different from the power supply of the first power supply terminal is fed from a second power supply terminal which is a terminal different from the first power supply terminal, and an input terminal is connected to the output terminal of the first CMOS inverter. A second CMOS inverter;
Between the second input terminal and said second power supply terminal of the CMOS inverter, the said voltage of said input terminal to the second power supply terminal Ri Do a conducting state and a predetermined level or higher than the first power supply terminal A voltage limiting means connected so that a current flows from the first power supply terminal to the second power supply terminal side . 2. The interface circuit according to claim 1, wherein the voltage limiting means is two Zener diodes connected in series in opposite directions.

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