JP4102277B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a protection circuit for protecting an internal circuit from electrostatic discharge.

  FIG. 13 shows a known example of a protection circuit for protecting an internal circuit from electrostatic discharge (hereinafter referred to as ESD), particularly a power supply terminal protection circuit using a MOSFET connected between a power supply terminal and a ground terminal.

  As shown in FIG. 13, the power supply terminal protection circuit includes an RC delay circuit 101, an inverter circuit 102, and a driver N-channel MOSFET (hereinafter referred to as NMOS) 103. The RC delay circuit 101 is connected between the power supply terminal VDD and the ground terminal GND. When a certain time elapses after the power is turned on, its output is set to “High” level, and the driver NMOS 103 is connected via the inverter circuit 102. Turn off. That is, during energization, the driver NMOS 103 is turned off to suppress a short circuit between the power supply terminal VDD and the ground terminal GND, thereby preventing malfunction of the semiconductor integrated circuit device.

  On the other hand, when a high voltage is applied to the power supply terminal VDD for a short time, for example, when ESD occurs, the RC delay circuit 101 does not react, and its output is set to “Low” level via the inverter circuit 102. Then, the driver NMOS 103 is turned on. When the driver NMOS 103 is turned on, for example, a high voltage applied to the power supply terminal VDD is discharged, and the semiconductor integrated circuit device is protected from destruction.

  The potential transition at power-on of the power supply terminal VDD is slower than the potential transition at the time of ESD occurrence. If the time constant of the RC delay circuit 101 is set to a value that does not react to a short-time voltage application waveform such as ESD, the driver NMOS 103 is turned on only when a short-time voltage is applied. Can function. This type of protection circuit is described in Non-Patent Documents 1, 2, 3, and 4, for example.

  Furthermore, as shown in FIG. 14, in addition to the RC delay circuit 101-1, the output of the NAND circuit 102 'is fed back to its own input via the RC delay circuits 101-2 and 101-3. There is also a protection circuit that more reliably prevents the malfunction of the driver NMOS 103. This type of protection circuit is described in Patent Document 1, for example.

  Since the protection circuit shown in FIGS. 13 and 14 uses the RC delay circuit 103 to turn off the driver NMOS 103, for example, a terminal that maintains a stable potential when energized, such as a power supply terminal. Can be applied. However, it is difficult to apply to a terminal that repeats “High” level and “Low” level at a high frequency, for example, a terminal such as an input / output terminal, that is, a signal terminal. This is because the RC delay circuit 103 is difficult to react to the application of a high-frequency potential and it is difficult to reliably turn off the driver NMOS 103. In particular, in a semiconductor integrated circuit device that requires high-speed operation, the I / O signal propagation transition time may be shorter than the ESD application time. In the protection circuits shown in FIGS. 13 and 14, it is practically impossible to apply such a signal to a terminal to which signals are input / output.

  In addition, as shown in FIG. 15, there is a protection circuit in which the protection operation of the protection element is controlled by a potential from another terminal. This type of protection circuit is described in Non-Patent Document 5, for example.

  The protection circuit shown in FIG. 15 is an I / O terminal protection circuit, and a source and a drain are connected between the gate of the driver NMOS 103 and the input / output terminal I / O for supplying the gate potential of the driver NMOS 103. A connected P-channel MOSFET (hereinafter referred to as PMOS) 104 is provided. The gate potential of the PMOS 104 is supplied from a terminal different from the input / output terminal I / O, for example, the power supply terminal VDD. In the normal operation state, the power supply terminal VDD is energized to the power supply potential VDD, and a “High” level potential is applied to the gate of the PMOS 104. As a result, when energized, the PMOS 104 is turned off, the gate potential is not supplied to the driver NMOS 103, and the driver NMOS 103 can be turned off. Therefore, it can also be used for the input / output terminal I / O.

  Further, in Non-Patent Document 5, as shown in FIG. 16, the control of the driver NMOS 103-1 connected between the power supply terminal VDD1 and the ground terminal GND is controlled by the potential of the power supply terminal VDD2, and the power supply terminal VDD2 A configuration is also described in which the control of the driver NMOS 103-2 connected between the power supply terminal VDD 1 and the ground terminal GND is controlled by the potential of the power supply terminal VDD 1.

  In the power supply terminal protection circuit shown in FIG. 16, the PMOS 104-1 or 104-2 is turned on / off using the potential of the power supply terminal other than its own power supply terminal, and the driver NMOS 103-1 or 103-2 is turned on. Turn on / off. For this reason, it is possible to discharge the high potential applied to its own power supply terminal without using the RC delay circuit 101 shown in FIGS. However, in the protection circuit shown in FIG. 16, when the power supply VDD1 is energized while the power supply VDD2 is not energized, the driver NMOS 103-1 is turned on, and the semiconductor integrated circuit device malfunctions. Similarly, when the power supply VDD2 is energized while the power supply VDD1 is not energized, the driver NMOS 103-2 is turned on and the semiconductor integrated circuit device malfunctions.

  In Non-Patent Document 6, as shown in FIG. 17, the control of the driver NMOS 103-1 connected between the power supply terminal VDD1 and the ground terminal GND is controlled by an inverter 102-1 that inverts the potential of the power supply terminal VDD2. The configuration in which the control of the driver NMOS 103-2 connected between the power supply terminal VDD2 and the ground terminal GND is controlled by the inverter circuit 102-2 that inverts the potential of the power supply terminal VDD1 is described.

  The power supply terminal protection circuit shown in FIG. 17 performs the same operation as that of the power supply terminal protection circuit shown in FIG. 16. However, as with the power supply terminal protection circuit shown in FIG. Is turned on, and the driver NMOS 103-1 is turned on when the power supply VDD2 is turned on while the power supply VDD1 is not turned on.

The current semiconductor integrated circuit device includes a multi-power supply semiconductor integrated circuit device. Furthermore, semiconductor integrated circuit devices with a so-called partial power shutdown function that cuts off the power supply itself, except for some circuits, have been developed for multi-power semiconductor integrated circuit devices. However, the protection circuit shown in FIGS. 16 and 17 cannot be applied to the power supply terminal of the semiconductor integrated circuit device with a partial power supply shutdown function. For example, assuming that the power supply VDD2 is shut down, the driver NMOS 103-1 is turned on, and the power supply terminal VDD1 and the ground terminal GND are short-circuited. For this reason, the semiconductor integrated circuit device malfunctions.
R. Merrill “ESD Design Methodology” EOS / ESD Symp1993, p233-p237. IBM MicroNews Second Quarter 2002 SHVoldman “An Automated ESD CAD System for BiCMOS SiGe Technology: A New Millennium for ESD Design” p29-p32. MD. Ker “ESD Protection Design on Analog Pin with Very Low Input Capacitance for High-Frequency or Current-Mode Applications” IEEE J.SC, Vol35, No8, Aug.2000, p1194-p1199. Intel Technology Journul Q3'98 K. Sechan “The Quality and Reliability of Intel's Quarter Micron Process” p1-p11. J. Zhiliang “Design Methodology for Otptimizing Gate Driven ESD Protection Circuits in Submicron CMOS Processes” EOS / ESD Symp 1997, p230-p239. WR Anderson “Cross-Referenced ESD Protection for Power Supplies” EOS / ESD Symp 1998, p86-p95. US Pat. No. 5,255,146

The invention that provide a semiconductor integrated circuit device having a protection circuit with a power supply terminal dated partial power shutdown function, and any to which also can be applied the configuration of the signal terminals.

The semiconductor integrated circuit device according to one embodiment of this invention, a first terminal the first potential is applied, a second terminal a second potential is applied, and a third terminal of the third potential is applied, a fourth potential A fourth terminal, a protective element connected between the first terminal and the second terminal, a first voltage detection circuit connected between the third terminal and the second terminal, The protection operation of the protection element is permitted based on the second voltage detection circuit connected between the first terminal and the second terminal, the fourth potential, and the output of the first voltage detection circuit. And when the second voltage detection circuit detects that the potential difference between the first potential and the second potential exceeds a predetermined potential difference, the fourth potential and the output of the first voltage detection circuit Regardless of the protection element operation control circuit which permits the protection operation of the protection element It includes a.

  According to the present invention, it is possible to provide a semiconductor integrated circuit device including a protection circuit having a configuration that can be applied to both a power supply terminal with a partial power supply shutdown function and a signal terminal.

  Several embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

(First embodiment)
FIG. 1 is a circuit diagram showing one circuit example of the semiconductor integrated circuit device according to the first embodiment of the present invention.

  As shown in FIG. 1, the semiconductor integrated circuit device according to the first embodiment includes a power supply terminal protection circuit 10. The power supply terminal protection circuit 10 is connected to the first terminal 11, the second terminal 12, and the third terminal 13. In the present embodiment, the first terminal 11 is a power supply terminal to which a first power supply potential VDD1 is applied, the second terminal 12 is a low potential power supply potential, for example, a ground terminal to which a ground potential GND1 is applied, and a third terminal 13 Is a power supply terminal to which the second power supply potential VDD2 is applied.

  The protection element 14 is connected between the first terminal 11 and the second terminal 12.

  A voltage detection circuit 15 is further connected between the first terminal 11 and the second terminal 12.

  The voltage detection circuit 15 detects the voltage between the first terminal 11 and the second terminal 12. In the present embodiment, the voltage detection circuit 15 is, so to speak, an energization stability detection circuit, and after a predetermined time has elapsed since the first power supply potential VDD1 was turned on, a potential for prohibiting the protection operation of the protection element 14 is This is given to the protection element operation control circuit 16. An example of such a circuit is an RC delay circuit 21. The RC delay circuit 21 of the present embodiment includes a resistor R that receives the first power supply potential VDD1 at one end of the current path, and a capacitor C that receives the ground potential GND1 at one electrode. Then, the potential of the connection node 22 between the other end of the current path of the resistor R and the other electrode of the capacitor is applied to the protection element operation control circuit 16.

  The protection element operation control circuit 16 performs control to permit and prohibit the protection operation of the protection element 14 based on the potential of the second power supply potential VDD2 and the output of the voltage detection circuit 15. An example of the protection element operation control circuit 16 is a logic circuit that uses the potential difference between the first power supply potential VDD1 and the ground potential GND1 as an operation power supply voltage, for example. In the present embodiment, the logic circuit receives the potential of the second power supply potential VDD2 and the output of the voltage detection circuit 15 as input logic values. Then, when the logical value of at least one of the second power supply potential VDD2 and the output of the voltage detection circuit 15 is in one state, for example, “High” level, a logical value for prohibiting the protective operation of the protective element 14 is output. . Further, when the logical values of both the potential of the second power supply potential VDD2 and the output of the voltage detection circuit 15 are in the 0 state, for example, “Low” level, a logical value permitting the protection operation of the protection element 14 is output. That is, the logic circuit outputs a logical value that prohibits the protection operation of the protection element 14 when either the first power supply potential VDD1 or the second power supply potential VDD2 is energized, and when both are not energized, By applying ESD to VDD1, a logical value permitting the protection operation of the protection element 14 is output. An example of a logic circuit that outputs such logic is a NOR gate circuit 23.

  The protective element 14 is a circuit element (not shown) connected between the first terminal 11 and the second terminal 12 due to a high potential difference generated between the first terminal 11 and the second terminal 12, for example, ESD. And an integrated circuit (not shown). The protective element 14 may be any element that can perform such a protective operation, and an example thereof is an insulated gate FET. In the present embodiment, the protection element 14 is a MOSFET having a gate as a control input, receiving the first power supply potential VDD1 at one of the source and the drain and receiving the ground potential GND1 at the other of the source and the drain. As the MOSFET, either an N-channel MOSFET (NMOS) or a P-channel MOSFET (PMOS) can be used. In this embodiment, an example using NMOS is shown. Hereinafter, the NMOS that performs the protection operation is referred to as a driver NMOS 24. In the present embodiment, the output of the NOR gate circuit 22 is directly input to the gate of the driver NMOS 24.

  Next, the operation of the semiconductor integrated circuit device according to the first embodiment will be described.

  The driver NMOS 24 is turned on when a high potential difference occurs between the first terminal 11 and the second terminal 12 in a state where the protection operation is permitted by the output of the NOR gate circuit 23, for example, when ESD occurs. To do. Thereby, a circuit element (not shown) and an integrated circuit (not shown) connected between the first terminal 11 and the second terminal 12 are protected.

  The driver NMOS 24 is turned off in a state where the protection operation is prohibited by the output of the NOR gate circuit 23. Thereby, an inadvertent short circuit between the first terminal 11 and the second terminal 12 is suppressed, and malfunction of the integrated circuit is suppressed.

  Hereinafter, in the first embodiment, a state where the protection operation is permitted and a state where the protection operation is prohibited will be described.

(First power supply potential VDD1 = energized, second power supply potential VDD2 = energized)
When both the first power supply potential VDD1 and the second power supply potential VDD2 are energized, the input logic of both the first input IN1 and the second input IN2 of the protection element operation control circuit 16, for example, the NOR gate circuit 23 The level becomes “High”. Therefore, the NOR gate circuit 23 sets its output logic level to “Low”. As a result, the gate potential of the protection element 14, for example, the driver NMOS 24 becomes “Low”, and the driver NMOS 24 is turned off. Therefore, the protection operation of the protection element 14 is prohibited, and malfunction of the semiconductor integrated circuit device is suppressed.

  In the present embodiment, the output of the RC delay circuit 21 is given to the first input IN1. Therefore, precisely, the state of “first power supply potential VDD1 = energized” is determined after a predetermined delay time determined by the time constant of the RC delay circuit 21 has elapsed since the first power supply potential VDD1 is energized, that is, This means a state where the first power supply potential VDD1 is stably energized.

(First power supply potential VDD1 = energized, second power supply potential VDD2 = not energized)
When the first power supply potential VDD1 is energized and the second power supply potential VDD2 is not energized, the input logic level of the second input IN2 of the NOR gate circuit 23 becomes “Low”. However, since the input logic level of the first input IN1 of the NOR gate circuit 23 is “High”, the NOR gate circuit 23 sets its output logic level to “Low” as in the case where both are energized. As a result, the driver NMOS 24 is turned off. Therefore, the protection operation of the protection element 14 is prohibited, and malfunction of the semiconductor integrated circuit device is suppressed.

(First power supply potential VDD1 = not energized, second power supply potential VDD2 = energized)
When the first power supply potential VDD1 is not energized and the second power supply potential VDD2 is energized, the input logic level of the second input IN2 of the NOR gate circuit 23 becomes “High”, but the power supply of the NOR gate circuit 23 Since VDD1 is not energized, its output logic level is equivalent to “Low”, as in the case of bi-energization.

  An example of a state in which at least one of the first power supply potential VDD1 and the second power supply potential VDD2 is energized is, for example, a state in which the semiconductor integrated circuit device is incorporated in an electronic device and the power is turned on.

  In the present embodiment, the protection operation control circuit 16 prohibits the protection operation of the protection element 14 when at least one of the first power supply potential VDD1 and the second power supply potential VDD2 is energized. That is, in the semiconductor integrated circuit device according to the present embodiment, even if one of the first power supply potential VDD1 and the second power supply potential VDD2 is shut down, the protection element 14 does not operate and the semiconductor integrated circuit device malfunctions. Is suppressed. Therefore, the semiconductor integrated circuit device according to this embodiment can be applied to a semiconductor integrated circuit device with a partial shutdown function that partially shuts down the power supply potential.

(First power supply potential VDD1 = not energized, second power supply potential VDD2 = not energized)
When both the first power supply potential VDD1 and the second power supply potential VDD2 are not energized, the input logic levels of both the first input IN1 and the second input IN2 of the NOR gate circuit 23 become “Low”. In this state, for example, it is assumed that a high potential is instantaneously applied to the first terminal 11. Here, “instantaneous” means, for example, a time shorter than or less than the delay time of the RC delay circuit 21. In a state where a high potential is instantaneously applied to the first terminal 11, the input logic levels of both the first input IN1 and the second input IN2 of the NOR gate circuit 23 remain “Low”. The NOR gate circuit 23 sets its output logic level to “High”. As a result, the gate potential of the protection element 14, for example, the driver NMOS 24 becomes “High”, and the driver NMOS 24 is turned on. That is, the protection operation of the protection element 14 is permitted, and the protection element 14 performs the protection operation. As a result, a circuit element (not shown) or an integrated circuit (not shown) connected between the first terminal 11 and the second terminal 12 is instantaneously applied to the first terminal 11. Protected from potential, eg, ESD.

  An example of a state in which both the first power supply potential VDD1 and the second power supply potential VDD2 are not energized is, for example, a state before assembly in a manufacturing factory. The semiconductor integrated circuit device before assembly is not mounted on the circuit board. For this reason, none of the first terminal 11, the second terminal 12, and the third terminal 13 of the semiconductor integrated circuit device is connected to the electrical contact. The semiconductor integrated circuit device in such a state may be accidentally charged to either a positive potential or a negative potential. It is assumed that a transport device that transports the semiconductor integrated circuit device, such as a handler, approaches the charged semiconductor integrated circuit device. The handler is usually grounded. For this reason, when the handler approaches the charged semiconductor integrated circuit device, ESD may occur between the handler and the semiconductor integrated circuit device. Even when such ESD occurs, the protection operation of the protection element 14 is permitted in the semiconductor integrated circuit device according to the present embodiment, so that the circuit elements and the integrated circuit in the semiconductor integrated circuit device are Can be protected from.

  FIG. 2 shows the operation logic of the power supply terminal protection circuit 10 in this embodiment.

  According to the semiconductor integrated circuit device of the first embodiment, the protection operation of its own power supply terminal with reference to the current supply state of its own power supply potential and the current supply state of other power supply potentials other than its own power supply potential The power supply terminal protection circuit 10 can be permitted or prohibited. For this reason, the protection operation of the protection element 14 can be permitted when both its own power supply potential and other power supply potentials are not energized. Therefore, for example, even when an unexpectedly high potential is applied, for example, ESD occurs in a state before the semiconductor integrated circuit device is assembled, internal circuit elements and integrated circuits can be protected from electrostatic breakdown.

  Further, the power supply terminal protection circuit 10 can inhibit the protection operation of the protection element 14 as long as at least one of its own power supply potential and another power supply potential is energized. Therefore, the power supply terminal protection circuit 10 can also be applied to a power supply terminal of a multi-power supply semiconductor integrated circuit device, for example, a power supply terminal with a partial power supply shutdown function that partially shuts down a power supply potential.

  Further, in this embodiment, the protection element operation control circuit 16 needs to be added to the conventional protection circuit, but the protection element operation control circuit 16 can be configured by a logic circuit. However, since the circuit elements such as MOSFETs constituting the logic circuit may be small, the increase in the area can be minimized. Further, since the logic circuit can be formed by the same manufacturing process as the logic circuit included in the internal integrated circuit, the power supply terminal protection circuit 10 according to the present embodiment does not need to change the manufacturing process.

  As described above, according to the first embodiment, it is possible to obtain a semiconductor integrated circuit device including a protection circuit having a configuration that can be applied to a power supply terminal with a partial power supply shutdown function.

(Second Embodiment)
The protection circuit having the configuration shown in the first embodiment can be applied not only to a power supply terminal but also to a signal terminal protection circuit.

  Hereinafter, an example in which the protection circuit having the configuration shown in the first embodiment is applied to a signal terminal, for example, an input / output terminal will be described as a second embodiment of the present invention.

  FIG. 3 is a circuit diagram showing a circuit example of a semiconductor integrated circuit device according to the second embodiment of the present invention.

As shown in FIG. 3, the signal terminal protection circuit 30 provided in the semiconductor integrated circuit device according to the second embodiment has the same configuration as the power supply terminal protection circuit 10 shown in the first embodiment. The difference is
(1) The protection element 14 is connected between the I / O terminal 31 and the second terminal 12 (2) The voltage detection circuit 15 is connected between the I / O terminal 31 and the second terminal 12. (3) The protection element operation control circuit 16 performs control for permitting and prohibiting the protection operation of the protection element 14 based on the potential of the first power supply potential VDD and the output of the voltage detection circuit 15. ,
It is.

  Hereinafter, in the second embodiment, a state where the protection operation is permitted and a state where the protection operation is prohibited will be described.

(First power supply potential VDD1 = energized)
When the first power supply potential VDD1 is energized, the input logic level of the first input IN1 of the protection element operation control circuit 16, for example, the NOR gate circuit 23, becomes “High”. Therefore, the NOR gate circuit 23 fixes its output logic level to “Low” regardless of the input logic level of the second input INI / O. As a result, the driver NMOS 24 is turned off and the protection operation of the protection element 14 is prohibited. Therefore, malfunction of the semiconductor integrated circuit device is suppressed.

(First power supply potential VDD1 = not energized)
When the first power supply potential VDD1 is not energized, for example, the input logic level of the first input IN1 of the NOR gate circuit 23 becomes “Low”. Therefore, the NOR gate circuit 23 sets the output logic level to “Low” or “High” according to the input logic level of the second input INI / O.

  In the present embodiment, the voltage detection circuit 15 is the same RC delay circuit 21 as in the first embodiment. For this reason, when a high potential is instantaneously applied to the I / O terminal 31, that is, when a high potential is applied within a time shorter than or less than the delay time of the RC delay circuit 21, The output logic level of the 2-input INI / O does not change and remains “Low”. Therefore, the NOR gate circuit 23 sets its output logic level to “High”. As a result, the gate potential of the driver NMOS 24 becomes “High”, and the driver NMOS 24 is turned on. That is, the protection operation of the protection element 14 is permitted, and the protection element 14 performs the protection operation. Therefore, a circuit element or an integrated circuit connected to the I / O terminal 31, for example, the I / O buffer 32, is protected from a high potential applied to the I / O terminal 31 instantaneously, for example, ESD. .

  FIG. 4 shows the operation logic of the signal terminal protection circuit 30 in this embodiment.

  According to the semiconductor integrated circuit device according to the second embodiment, the signal terminal protection that allows or prohibits the protection operation of its own I / O terminal with reference to the energization state of its own power supply potential. A circuit 30 is included. For this reason, the protection operation of the protection element 14 can be permitted when its own power supply potential is not energized. Accordingly, as in the first embodiment, for example, even when an unexpected high potential is applied, for example, ESD occurs in a state before the semiconductor integrated circuit device is assembled, an internal circuit element or integrated circuit, for example, I The / O buffer 32 can be protected from electrostatic breakdown.

  Furthermore, the signal terminal protection circuit 30 can inhibit the protection operation of the protection element 14 as long as its power supply potential is energized. For this reason, even if the potential of the I / O terminal 31 fluctuates with the signal logic amplitude voltage, the driver NMOS 24 does not operate.

  As described above, according to the second embodiment, when the power supply potential is energized, the signal logic amplitude voltage, for example, a terminal that repeats the “High” level and the “Low” level, for example, an I / O terminal, etc. It is possible to obtain a signal terminal protection circuit that can be applied to various signal terminals.

  In the multi-power supply semiconductor integrated circuit device, when the first power supply potential VDD1 is not energized, the potential of the I / O terminal 31 becomes the first power supply potential VDD1 level, for example, the signal logic level “High”. There is also a possibility.

  However, in this case, in the semiconductor integrated circuit device, the P + type drain diffusion layer connected to the I / O terminal 31 of the PMOS constituting the I / O buffer 32 and the first power supply potential VDD1 shut down are set. A diode formed between the N-type well and the connected N-type well is forward-biased to break down. In addition, there is no problem because there is a restriction on circuit design that the “low” level is supplied to the I / O buffer 32 whose power supply is shut down.

  In the present embodiment, an example in which the signal terminal protection circuit 30 is applied to the I / O terminal 31 has been described. However, the signal terminal protection circuit 30 is not limited to an I / O terminal that handles input signals and output signals, but handles command signals. The present invention can be applied to various signal terminals such as a command signal terminal and a clock signal terminal that handles a clock signal.

(Third embodiment)
The third embodiment relates to a specific circuit example when the protection circuit described in the first and second embodiments is applied to a multi-power supply semiconductor integrated circuit device.

  FIG. 5 is a circuit diagram showing a circuit example of a semiconductor integrated circuit device according to the third embodiment of the present invention.

  As shown in FIG. 5, the semiconductor integrated circuit device according to the third embodiment includes a first power supply terminal protection circuit 10-1, a second power supply terminal protection circuit 10-2, and a signal terminal protection circuit 30. In the present embodiment, the first power supply terminal protection circuit 10-1 is the same as that of the first embodiment, and the signal terminal protection circuit 30 is the same as that of the second embodiment.

The second power supply terminal protection circuit 10-2 has the same configuration as the power supply terminal protection circuit 10 shown in the first embodiment. The difference is
(1) the protective element 14 is connected between the third terminal 13 and the fourth terminal 33;
(2) The voltage detection circuit 15 is connected between the third terminal 13 and the fourth terminal 33,
(3) the protection element operation control circuit 16 performs control to permit and prohibit the protection operation of the protection element 14 based on the potential of the first power supply potential VDD and the output of the voltage detection circuit 15;
It is. Here, the fourth terminal 33 is a ground terminal to which a ground potential GND2 is applied. In the present embodiment, the terminal to which the ground potential is applied is divided into the second terminal 12 and the fourth terminal 33, but the fourth terminal 33 may be the second terminal 12.

  The state where the protection operation of the second power supply terminal protection circuit 10-2 is permitted and the state where the protection operation is prohibited are the same as those of the power supply terminal protection circuit 10 shown in the first embodiment. If at least one of the two power supply potentials VDD2 is energized, the protection operation of the protection element 14 is prohibited and the malfunction of the semiconductor integrated circuit device is suppressed. Further, when both the first power supply potential VDD1 and the second power supply potential VDD2 are not energized, the protection operation of the protection element 14 is permitted, and the semiconductor integrated circuit device can be protected from, for example, electrostatic breakdown.

  According to the third embodiment, in a multi-power supply semiconductor integrated circuit device, for example, a semiconductor integrated circuit device to which a plurality of power supplies are provided such as a first power supply potential VDD1 and a second power supply potential VDD2, the first power supply (VDD1). If both the terminal protection circuit 10-1 and the second power supply (VDD2) terminal protection circuit are energized at least one of their own power supply potential and the other power supply potential, the protection operation of the protection element 14 is performed. Can be prohibited. Therefore, the circuit elements and the integrated circuits connected to the respective power supply terminals of the multi-power supply semiconductor integrated circuit device can be protected from, for example, electrostatic breakdown while suppressing malfunction.

(Fourth embodiment)
The fourth embodiment is an example in which a PMOS is used for the protection element 14.

  FIG. 6 is a circuit diagram showing a circuit example of a semiconductor integrated circuit device according to the fourth embodiment of the present invention.

  As shown in FIG. 6, not only the NMOS 24 but also a PMOS 24 ′ can be used for the protection element 14. In this case, the output logic of the logic circuit of the protection element operation control circuit 16 may be inverted. In the present embodiment, an OR gate circuit 23 'in which an inverter circuit is connected to the output of the NOR gate circuit 23 and its logic logic is inverted is used as the logic circuit.

  According to the fourth embodiment, it is possible to obtain a protection circuit using the PMOS 24 ′ as the protection element 14 that can obtain the same effects as those of the first to third embodiments.

(Fifth embodiment)
The voltage detection circuit 15 shown in the first to fourth embodiments is configured to prohibit the protection operation of the protection element 14 when a predetermined delay time elapses after power is supplied, for example. .

  In addition to handling voltage application between any two terminals before assembly, the ESD is assembled and energized as in EMS (Electromagnetic Interference Susceptibility) standard IEC16000-4-2 However, there are cases in which the external device is examined for the presence of malfunctions and damage by applying static electricity to test its toughness.

  In this case, for example, in the voltage detection circuit 15 such as the RC delay circuit 21, since the protection operation of the driver NMOS 24 is prohibited in the energized state, the charge generated by static electricity cannot be effectively discharged. Even in an energized state, the detection circuit is preferably a high threshold level detection type for a semiconductor integrated circuit device that needs to perform or needs to perform effective discharge. By making the detection circuit a high threshold level detection type, it is possible to obtain a protection circuit that reacts to a high potential difference generated by ESD, for example, even when power is supplied.

  FIG. 7 is a circuit diagram showing a first example of a high threshold level detection type detection circuit according to a fifth embodiment of the present invention.

  As shown in FIG. 7, the high threshold level detection type detection circuit 21 ′ according to the first example includes a resistor R and a diode circuit D connected in series to the resistor R. The diode circuit D of this example includes a plurality of diodes, and the plurality of diodes are connected to each other in series. The number of diodes D connected in series is appropriately adjusted according to the voltage value to be detected, for example. A first potential, for example, a high potential side power supply potential VDD is applied to one end of the current path of the resistor R. A second potential, for example, a low-potential-side power supply potential VSS (hereinafter referred to as a ground potential) is applied to the cathode of the diode circuit D. The other end of the current path of the resistor R is connected to the anode of the diode circuit D, and the potential of the connection node 22 is given to one input of the protection element operation control circuit 16, for example, one input of the NOR gate circuit 23. .

  The detection circuit 21 ′ is a circuit in which a resistor R and a diode D are connected in series, and the potential of the node 22 is constant at {diode forward voltage VF × number of diodes connected in series}. The constant potential of the node 22 is given to the input of the protection element operation control circuit 16. In this state, when the potential of the high potential side power supply potential VDD rises, the voltage drop of the resistor R increases, and the potential difference between the input potential of the protection element operation control circuit 16 and the power supply potential VDD increases. If the ESD is detected when the potential difference exceeds a predetermined potential difference, the protection operation of the protection element 14 can be permitted.

  According to the detection circuit 21 ′ according to the first example, in the state where the potential difference between the power supply potential VDD and the ground potential VSS reaches the predetermined potential difference VDD, it is further detected that a potential difference exceeding the predetermined potential difference VDD has occurred. can do. Then, by providing this detection result to the protection element operation control circuit 16, it is possible to permit the protection operation of the protection element 14 even in the energized state.

  FIG. 8 is a circuit diagram showing a second example of the high threshold level detection type detection circuit.

  As shown in FIG. 8, the high threshold level detection type detection circuit 21 ″ according to the second example includes a resistor R, a diode circuit D connected in series to the resistor R, and a connection between the resistor R and the diode circuit D. And an inverter circuit 34 having an input connected to the node 22. For example, a power supply potential VDD is applied to the anode of the diode circuit D. For example, a ground potential VSS is applied to one end of the current path of the resistor R. The cathode of the diode circuit D is connected to the other end of the current path of the resistor R, and the potential of the connection node 22 is applied to the input of the inverter circuit 34. The output of the inverter circuit 34 is given to one input of the protection element control circuit 16, for example, one input of the NOR gate circuit 23.

  In a state where the potential difference between the power supply potential VDD and the ground potential VSS reaches a predetermined potential difference, that is, VDD, the detection circuit 21 ″ sets the potential of the node 22 to a low potential, that is, the output logic level is “Low”. A potential of a logical value “Low” is applied to the input of the inverter circuit 34. Upon receiving this input, the inverter circuit 34 sets its output logical level to “High”. For example, when the output of the logical value “High” is given to one of the inputs of the NOR gate circuit 23, the protection operation of the protection element 14 is prohibited.

  Further, as the potential difference between the power supply potential VDD and the ground potential VSS becomes higher than a predetermined potential difference, the potential of the node 22 increases. When the potential of the node 22 exceeds the circuit threshold value of the inverter circuit 34, the inverter circuit 34 changes its output logic level from “High” to “Low”. For example, when the output of the logical value “Low” is given to one input of the NOR gate circuit 23, the protection operation of the protection element 14 is permitted.

  Also in the detection circuit 21 ″ according to the second example, in the state where the potential difference between the power supply potential VDD and the ground potential VSS reaches the predetermined potential difference VDD, it is further detected that a potential difference exceeding the predetermined potential difference VDD has occurred. As in the first example, the protection operation of the protection element 14 can be permitted even in the energized state. The circuit threshold value of the detection circuit 21 ″ only needs to be higher than the power supply voltage and lower than the hold voltage of the protection element 14.

  In the detection circuit 21 ″ according to the second example, the inverter circuit 34 can be omitted. That is, the potential of the node 22 is directly input to the protection element operation control circuit 16, and the protection element operation control circuit 16 prohibits or permits the protection operation of the protection element 14 according to the potential of the connection node 22. It is also possible to do.

  In addition, the detection circuits 21 ′ and 21 ″ have the following advantages compared to the RC delay circuit 21. The RC delay circuit 21 has a capacitor C for adjusting / setting the time constant, that is, adjusting / setting the delay time. The capacitor C requires a large area on the semiconductor chip. On the other hand, since the detection circuits 21 ′ and 21 ″ do not require the capacitor C, the size of the voltage detection circuit 15 can be further reduced.

(Sixth embodiment)
The sixth embodiment is another example of a protection circuit operable even when energized.

  FIG. 9 is a circuit diagram showing one circuit example of a semiconductor integrated circuit device according to the sixth embodiment of the present invention.

  As shown in FIG. 9, the semiconductor integrated circuit device according to the sixth embodiment includes a signal terminal protection circuit 30 ′. The signal terminal protection circuit 30 ′ includes a protection element 14, a first voltage detection circuit 15-1 connected between the first terminal 11 and the second terminal 12, an I / O terminal 31, a second terminal 12, and the like. A second voltage detection circuit 15-2 connected between the first protection element operation control circuit 16-1 and a second protection having an input connected to the output of the first protection element operation control circuit 16-1. And an element operation control circuit 16-2.

  In the present embodiment, the protection element 14 is a driver NMOS 24, the first voltage detection circuit 15-1 is an RC delay circuit 21, and the second voltage detection circuit 15-2 is a high threshold level detection type detection circuit 21 ″. It is. Further, the first protection element operation control circuit 16-1 and the second protection element operation control circuit 16-2 constitute one protection element operation control circuit in terms of the circuit, and the first power supply potential VDD2 and the first protection element operation control circuit 16-2. Based on the output of the voltage detection circuit 15-1 and the output of the second voltage detection circuit 15-2, control for permitting or prohibiting the protection operation of the protection element 14 is performed.

  In the present embodiment, the first protection element operation control circuit 16-1 is a logic circuit that uses the potential difference between the first power supply potential VDD1 and the ground potential GND1 as an operation power supply voltage, for example, a NOR gate circuit 23. The NOR gate circuit 23 receives the potential of the second power supply potential VDD2 and the output of the first voltage detection circuit 15-1 as input logic values. The operation is similar to, for example, the NOR gate circuit 23 of the protection element operation control circuit 16 of the power supply terminal protection circuit 10 shown in the first embodiment.

  The second protection element operation control circuit 16-2 is a logic circuit that uses the potential difference between the potential of the I / O terminal 31 and the ground potential GND1 as an operation power supply voltage, for example, an OR gate circuit 23 ′. The OR gate circuit 23 'receives the output of the first protection element operation control circuit 16-1 and the second voltage detection circuit 15-2 as input logic values. The OR gate circuit 23 ′ has a low output logic level of the second voltage detection circuit 15-2. For example, when the potential difference between the potential of the I / O terminal 31 and the ground potential GND1 is equal to or less than a predetermined potential difference, 1 The protection operation of the protection element 14 is permitted or prohibited according to the output logic value of the protection element operation control circuit 16-1.

  For example, in the OR gate circuit 23 ′, when the output logic level of the second voltage detection circuit 15-2 is “Low” and the output logic level of the first protection element operation control circuit 16-1 is “Low”. The output logic level is set to “Low”, and the protection operation of the protection element 14 is prohibited. Conversely, when the output logic level of the second voltage detection circuit 15-2 is “Low” and the output logic level of the first protection element operation control circuit 16-1 is “High”, the output logic level is “High” is set, and the protection operation of the protection element 14 is permitted.

  Further, when the output logic level of 15-2 of the second voltage detection circuit becomes “High”, that is, when the potential difference between the potential of the I / O terminal 31 and the ground potential GND2 exceeds a predetermined potential difference (overvoltage) Detection), the OR gate circuit 23 ′ sets the output logic level to “High” regardless of the output logic level of the first protection element operation control circuit 16-1, and permits the protection operation of the protection element 14.

  FIG. 10 shows the operation logic of the signal terminal protection circuit 10 in this embodiment.

  According to the semiconductor integrated circuit device of the sixth embodiment, during energization, for example, when a potential difference exceeding a predetermined potential difference is applied to the I / O terminal, the protection operation of the protection element 14, for example, the driver NMOS 24 is permitted. To do. For this reason, the semiconductor integrated circuit device can be protected from an excessive voltage during energization.

(Seventh embodiment)
The seventh embodiment is an example in which a PMOS is used for the protection element 14 of the sixth embodiment.

  FIG. 11 is a circuit diagram showing one circuit example of a semiconductor integrated circuit device according to the seventh embodiment of the present invention.

  As shown in FIG. 11, when the PMOS 24 'is used as the protection element 14, the output logic of the logic circuit of the second protection element operation control circuit 16-2 may be inverted. In the present embodiment, a NOR gate circuit 23 is used instead of the OR gate circuit 23 '.

  According to the seventh embodiment, it is possible to obtain a protection circuit using the PMOS 24 ′ as the protection element 14 that can obtain the same effect as that of the sixth embodiment.

(Eighth embodiment)
FIG. 12 is a circuit diagram showing an example of a semiconductor integrated circuit device according to the eighth embodiment of the present invention.

  When a strong ESD tolerance is required, it is necessary to increase the size of the driver NMOS 24. In this case, it may take more time than necessary to turn on the driver NMOS 24 due to the balance between the drive capability of the NOR gate circuit 23 and the gate load capacity of the driver NMOS 24.

  In such a case, as shown in FIG. 12, between the output of the protection element operation control circuit 16, for example, the output of the NOR gate circuit 23, and the control input of the protection element 14, for example, the gate of the driver NMOS 24 A pre-driver circuit 40 may be inserted so that the gate of the driver NMOS 24 is driven via the pre-driver circuit 40.

  The pre-driver circuit 40 is configured by, for example, connecting a plurality of inverter circuits 41 in series. Each inverter circuit 41 is gradually increased in size from the output of the protection element operation control circuit 16 toward the control input of the protection element 14, and the driving capability is gradually increased.

  According to the eighth embodiment, since the pre-driver circuit 41 is provided, the protection element 14 having a large load capacity of the control input of the protection element 14 is driven by, for example, a logic circuit having a small size, that is, a logic circuit having a small driving capability. It becomes possible.

  As described above, according to the first to eighth embodiments, even in a multi-power supply semiconductor integrated circuit device using a complicated power supply system having a large number of power supply terminals and performing a partial power supply shutdown, it is possible to reliably perform ESD. It is possible to provide a protection circuit that ensures protection and transparency to normal system operation (does not affect the operation), and a protection circuit that can also be applied to signal terminals such as I / O terminals.

  As mentioned above, although this invention was demonstrated by 1st-8th embodiment, this invention is not limited to these embodiment, In the implementation, it changes variously in the range which does not deviate from the summary of invention. Is possible.

  In addition, each of the above embodiments can be carried out independently, but it is of course possible to carry out a combination as appropriate.

  The above embodiments include inventions at various stages, and the inventions at various stages can be extracted by appropriately combining a plurality of constituent elements disclosed in the embodiments.

FIG. 1 is a circuit diagram showing a circuit example of a semiconductor integrated circuit device according to a first embodiment of the present invention. 2 is a diagram showing the operation logic of the power supply terminal protection circuit shown in FIG. FIG. 3 is a circuit diagram showing a circuit example of a semiconductor integrated circuit device according to the second embodiment of the present invention. 4 is a diagram showing the operation logic of the signal terminal protection circuit shown in FIG. FIG. 5 is a circuit diagram showing a circuit example of a semiconductor integrated circuit device according to the third embodiment of the present invention. FIG. 6 is a circuit diagram showing a circuit example of a semiconductor integrated circuit device according to the fourth embodiment of the present invention. FIG. 7 is a circuit diagram showing a first example of a voltage detection circuit provided in a semiconductor integrated circuit device according to the fifth embodiment of the present invention. FIG. 8 is a circuit diagram showing a second example of the voltage detection circuit provided in the semiconductor integrated circuit device according to the fifth embodiment of the present invention. FIG. 9 is a circuit diagram showing a circuit example of a semiconductor integrated circuit device according to the sixth embodiment of the present invention. 10 is a diagram showing the operation logic of the signal terminal protection circuit shown in FIG. FIG. 11 is a circuit diagram showing a circuit example of a semiconductor integrated circuit device according to the seventh embodiment of the present invention. FIG. 12 is a circuit diagram showing a circuit example of a semiconductor integrated circuit device according to the eighth embodiment of the present invention. FIG. 13 is a circuit diagram showing a conventional power protection circuit. FIG. 14 is a circuit diagram showing a conventional power protection circuit. FIG. 15 is a circuit diagram showing a conventional power protection circuit. FIG. 16 is a circuit diagram showing a conventional power protection circuit. FIG. 17 is a circuit diagram showing a conventional power protection circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10, 10-1, 10-2 ... Power supply terminal protection circuit 11, 12, 13, 31, 33 ... Terminal, 14 ... Protection element, 15 ... Voltage detection circuit, 16 ... Protection element operation control circuit, 21 ... RC delay Circuit, 21 ', 21 "... High threshold level detection type detection circuit, 22 ... Node, 23 ... NOR gate circuit, 23' ... OR gate circuit, 24 ... Driver NMOS, 24 '... Driver PMOS, 32 ... I / O Buffers 34, 41... Inverter circuit, 40.

Claims (2)

A first terminal to which a first potential is applied;
A second terminal to which a second potential is applied;
A third terminal to which a third potential is applied;
A fourth terminal to which a fourth potential is applied;
A protective element connected between the first terminal and the second terminal;
A first voltage detection circuit connected between the third terminal and the second terminal;
A second voltage detection circuit connected between the first terminal and the second terminal;
Based on the fourth potential and the output of the first voltage detection circuit, the protection operation of the protection element is permitted and prohibited, and the second voltage detection circuit detects a potential difference between the first potential and the second potential. A protection element operation control circuit that permits a protection operation of the protection element regardless of the fourth potential and the output of the first voltage detection circuit when it is detected that the voltage difference exceeds a predetermined potential difference. A semiconductor integrated circuit device. The first voltage detection circuit provides the protection element operation control circuit with a potential for prohibiting the protection operation of the protection element after a predetermined time has elapsed since the third potential was applied. The semiconductor integrated circuit device according to claim 1 .

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