JP4445708B2 - マップテーブルを使用して入出力モジュールにアクセスする方法 - Google Patents

マップテーブルを使用して入出力モジュールにアクセスする方法 Download PDF

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Publication number
JP4445708B2
JP4445708B2 JP2003043570A JP2003043570A JP4445708B2 JP 4445708 B2 JP4445708 B2 JP 4445708B2 JP 2003043570 A JP2003043570 A JP 2003043570A JP 2003043570 A JP2003043570 A JP 2003043570A JP 4445708 B2 JP4445708 B2 JP 4445708B2
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entry
address
memory
cell
type
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Japanese (ja)
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JP2003280984A5 (enExample
JP2003280984A (ja
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アシシュ・ガプタ
デベンドラ・ダス・シャーマ
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HP Inc
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Hewlett Packard Co
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2003043570A 2002-02-22 2003-02-21 マップテーブルを使用して入出力モジュールにアクセスする方法 Expired - Fee Related JP4445708B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/080,739 2002-02-22
US10/080,739 US6807603B2 (en) 2002-02-22 2002-02-22 System and method for input/output module virtualization and memory interleaving using cell map

Publications (3)

Publication Number Publication Date
JP2003280984A JP2003280984A (ja) 2003-10-03
JP2003280984A5 JP2003280984A5 (enExample) 2006-04-06
JP4445708B2 true JP4445708B2 (ja) 2010-04-07

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US (1) US6807603B2 (enExample)
JP (1) JP4445708B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060015589A1 (en) * 2004-07-16 2006-01-19 Ang Boon S Generating a service configuration
US20060015772A1 (en) * 2004-07-16 2006-01-19 Ang Boon S Reconfigurable memory system
US8190809B2 (en) * 2004-11-23 2012-05-29 Efficient Memory Technology Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines
CN101069211A (zh) * 2004-11-23 2007-11-07 高效存储技术公司 分页存储器及其智能存储器区段的交错寻址的多次缩略的方法和装置
US20130232304A1 (en) * 2012-03-05 2013-09-05 Qualcomm Incorporated Accelerated interleaved memory data transfers in microprocessor-based systems, and related devices, methods, and computer-readable media
US10140223B2 (en) * 2016-06-27 2018-11-27 Qualcomm Incorporated System and method for odd modulus memory channel interleaving
US11562101B2 (en) * 2017-11-13 2023-01-24 Intel Corporation On-device bitstream validation

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5293607A (en) 1991-04-03 1994-03-08 Hewlett-Packard Company Flexible N-way memory interleaving
US5530837A (en) 1994-03-28 1996-06-25 Hewlett-Packard Co. Methods and apparatus for interleaving memory transactions into an arbitrary number of banks
US5655113A (en) * 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
EP0931290A1 (en) 1997-03-21 1999-07-28 International Business Machines Corporation Address mapping for system memory
EP1050819A1 (en) 1999-05-03 2000-11-08 Sgs Thomson Microelectronics Sa Computer memory access
US6526459B1 (en) * 1999-11-10 2003-02-25 Ati International Srl Allocation of input/output bus address space to native input/output devices
US6480943B1 (en) 2000-04-29 2002-11-12 Hewlett-Packard Company Memory address interleaving and offset bits for cell interleaving of memory

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Publication number Publication date
US6807603B2 (en) 2004-10-19
JP2003280984A (ja) 2003-10-03
US20030163657A1 (en) 2003-08-28

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