JP4442948B2 - Constant voltage output circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a constant voltage output circuit that outputs a constant voltage, and more particularly to a constant voltage output circuit that reduces power consumption by sampling a feedback circuit.
[0002]
[Prior art]
As a conventional constant voltage output circuit, for example, there is a “constant voltage output circuit” disclosed in JP-A-6-59756. This circuit uses the constant voltage output of the constant voltage circuit as the power supply of the oscillation circuit, and the output voltage of the constant voltage circuit exhibits a change rate characteristic equal to the oscillation start voltage or the oscillation sustain voltage of the oscillation circuit. It is a thing. Therefore, in the manufacturing process, even if the threshold voltage of the transistors constituting each circuit changes, the voltage difference between the oscillation start voltage or oscillation sustain voltage of the oscillation circuit and the output voltage of the constant voltage circuit becomes substantially constant, and the output voltage Can be lowered to near the absolute value of the oscillation start voltage or the oscillation sustain voltage, and the power consumption of the oscillation circuit can be reduced.
[0003]
Further, in “Oscillation circuit, constant voltage generation circuit, semiconductor device, and portable electronic device and watch including these circuits” disclosed in Japanese Patent Application Laid-Open No. 10-213686, a transistor that constitutes an oscillation inverter of the oscillation circuit It is described that the power consumption of the oscillation circuit is reduced by adjusting the threshold voltage of the transistor and the threshold voltage of the transistor connected to the input portion of the operational amplifier of the constant voltage generation circuit.
[0004]
However, in the constant voltage output circuits disclosed in the above-mentioned Japanese Patent Application Laid-Open Nos. 6-59756 and 10-213686, the power consumption of the oscillation circuit to which power is supplied can be reduced. There was a problem that the power consumption of the output circuit itself remained large.
[0005]
As a conventional constant voltage output circuit that solves this problem, a constant voltage output circuit that supplies power to an oscillation circuit of a wrist watch, etc., an output circuit that supplies power to the oscillation circuit of a wrist watch, and the output of the output circuit There is provided a constant voltage output circuit including a feedback circuit that inputs feedback and outputs a control signal for controlling the output of the output circuit, and a sampling circuit that continuously turns on and off the feedback circuit. This constant voltage output circuit does not keep the feedback circuit in the on state, but continuously turns on and off, so that the power consumed by the feedback circuit can be reduced and the power consumption of the constant voltage output circuit itself can be reduced. it can.
[0006]
[Problems to be solved by the invention]
However, according to the conventional constant voltage output circuit in which the feedback circuit is continuously turned on and off, when the feedback circuit is turned off, the control signal is input due to the influence of the turned off feedback circuit. Since the voltage at the input terminal of the output circuit changes, the output of the output circuit changes greatly, and the output voltage changes greatly.
[0007]
Also, because the output voltage of the output circuit changes when the feedback circuit is turned off, the absolute value of the output voltage changes in a wave shape in accordance with the ON / OFF cycle of the feedback circuit. There is also a problem in that a voltage having an absolute value higher than necessary is supplied to the target circuit, and power consumption in the target circuit increases. Note that the voltage level of the absolute value of the output voltage takes into account the wavy change so that the absolute value of the output voltage does not fall below the absolute value of the stop voltage of the oscillation circuit etc. even in the valley portion of the wave. Must be set.
[0008]
The present invention has been made in view of the above, and an object thereof is to reduce the power consumption of the constant voltage output circuit itself and to reduce the change in the output voltage.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a constant voltage output circuit according to claim 1 is a constant voltage output circuit that supplies power to a target circuit to which power is supplied, and an output circuit that supplies power to the target circuit. A feedback circuit that feeds back the output of the output circuit and outputs a control signal for controlling the output of the output circuit, a sampling circuit that continuously turns on and off the feedback circuit, and an output from the feedback circuit A switch provided on a signal line for inputting a control signal to the output circuit, and provided between the switch and the output circuit, and a switch for turning on / off the signal line based on on / off of the sampling circuit. When the signal line is turned off by the switch, the input terminal of the output circuit for inputting the control signal is held at the signal level before the signal line is turned off. A holding circuit, is intended to include a.
[0010]
In the constant voltage output circuit according to claim 1, the sampling circuit continuously turns on and off the feedback circuit, and the signal line for inputting the control signal output from the feedback circuit to the output circuit is provided in the sampling circuit. When the signal line is turned off based on the on / off state, the input terminal of the output circuit for inputting the control signal is held at the signal level before the signal line is turned off. The change in voltage at the input terminal of the output circuit is eliminated.
[0011]
The constant voltage output circuit according to claim 2 is the constant voltage output circuit according to claim 1, wherein the feedback circuit includes a reference voltage generation circuit for generating a reference voltage, a load circuit for the feedback input, A differential circuit that inputs a reference voltage generated by the reference voltage generation circuit and an output of the load circuit corresponding to the feedback input, and outputs the control signal, and the sampling circuit includes the differential circuit Is to turn on and off.
[0012]
In the constant voltage output circuit according to the second aspect, the sampling circuit continuously turns on and off the differential circuit.
[0013]
The constant voltage output circuit according to claim 3 is the constant voltage output circuit according to claim 1, wherein the feedback circuit includes a reference voltage generating circuit for generating a reference voltage, a load circuit for the feedback input, A differential circuit that inputs a reference voltage generated by the reference voltage generation circuit and an output of the load circuit corresponding to the feedback input, and outputs a control signal, and the sampling circuit includes the differential circuit The load circuit is turned on and off.
[0014]
In the constant voltage output circuit according to the third aspect, the sampling circuit continuously turns on and off the differential circuit and the load circuit.
[0015]
According to a fourth aspect of the present invention, in the constant voltage output circuit according to the first, second, or third aspect, the holding circuit includes a phase compensation capacitor.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below in detail in the order of Embodiments 1 and 2, with reference to the accompanying drawings.
[0017]
Embodiment 1 FIG.
The constant voltage output circuit of the first embodiment will be described with reference to FIGS. 1 to 3 by taking as an example a constant voltage output circuit that is used in a wristwatch or a portable device and serves as a power source for an oscillation circuit or the like. FIG. 1 is a block diagram showing a configuration of the constant voltage output circuit according to the first embodiment.
[0018]
The constant voltage output circuit according to the first embodiment is a constant voltage output circuit that supplies power to a target circuit (not shown) that is a power supply target, and includes an output circuit 101 that supplies power to a target circuit (not shown), A feedback circuit 102 that outputs the feedback and outputs a control signal for controlling the output of the output circuit 101; a sampling circuit 103 that continuously turns on and off the feedback circuit 102; and a control signal output from the feedback circuit 102 A switch 104 is provided on a signal line for inputting to the output circuit 101, is provided between the switch 104 and the output circuit 101, and is provided between the switch 104 and the output circuit 101. When the signal line is turned off, the input level of the output circuit 101 for inputting the control signal is set to the signal level before being turned off. A holding circuit 105 for lifting, and a.
[0019]
The feedback circuit 102 feedbacks the output of the output circuit 101 and outputs a control signal. The sampling circuit 103 continuously turns on and off the feedback circuit 102, and the switch 104 turns on and off the signal line based on this on and off. When the signal line is turned off by the switch 104, the holding circuit 105 holds the input terminal of the output circuit 101 at the signal level before being turned off.
[0020]
FIG. 2 is a schematic circuit diagram illustrating a configuration of the constant voltage output circuit according to the first embodiment. In the constant voltage output circuit of the first embodiment, the transistor QN13 constitutes the output circuit 101, the load circuit including the resistors R1 and R2, the differential circuit OP1, and the constant voltage source 201 that generates the reference voltage Vref is the feedback circuit 102. The phase compensation capacitor CC constitutes a holding circuit 105. Here, the output voltage VREG is obtained by the following equation.
VREG = Vref × (R1 + R2) / R1
[0021]
FIG. 3 is a circuit diagram showing a configuration of the constant voltage output circuit of the first embodiment. In the constant voltage output circuit of the first embodiment, transistor QP11, constant current source 301, and transistors QP2, QP1, QN1, QP15, QP16, QN11, QP17, and QN12 constitute a differential circuit OP1, and transistors QP3 and QN2 are switches. 104 is configured. SP and SPX are signals having opposite logics, and are output from the sampling circuit 103.
[0022]
With the above configuration, the operation of the first embodiment will be described. FIG. 4 is a timing chart of the signals SP and SPX output from the sampling circuit 103 according to the first embodiment. The SP is at a high level while the feedback circuit 102 is turned on (when enabled (EN)) and is at a low level while the feedback circuit 102 is turned off (when held (HOLD)). SPX has reverse logic to SP.
[0023]
When enabled, SP is high and SPX is low, transistors QP1 and QN1 are turned on, and transistors QP11 and QP15 constitute a current mirror circuit. A current determined by the characteristics of the transistor QP11 flows through the transistor QP15 and branches into a current flowing through the transistor QP16 and a current flowing through the transistor QP17.
[0024]
Here, the operation of the differential circuit OP1 is stabilized when the current flowing through the transistor QP16 is equal to the current flowing through the transistor QP17. In order for these currents to be equal, the gate voltage of the transistor QP16 and the gate voltage of the transistor QP17 must be equal. In other words, the gate voltage of the transistor QP17 must be equal to the reference voltage Vref. In order to control the current flowing through the transistor QN13 so that the gate voltage of the transistor QP17 becomes equal to the reference voltage Vref, the drain voltage of the transistor QP16 is applied to the gate terminal of the transistor QN13 via the transistors QP3 and QN2.
[0025]
At the time of holding, SP is at a low level and SPX is at a high level, the transistors QP1 and QN1 are turned off, and the transistor QP2 is turned on instead. The gate voltage of the transistor QP15 becomes high level via the transistor QP2, the transistor QP15 is turned off, and the current flowing through the transistor QP15 is stopped. Thereby, the power consumption of the constant voltage output circuit of Embodiment 1 is reduced.
[0026]
Further, since the transistors QP3 and QN2 are turned off and the gate terminal of the transistor QN13 and the differential circuit OP1 are disconnected, the gate terminal of the transistor QN13 is not affected by the turned off differential circuit OP1. The gate terminal of the transistor QN13 is held at the voltage at the time of enable by the phase compensation capacitor CC, and a current having the same magnitude as that at the time of enable flows through QN13. As long as the load on the target circuit does not change significantly, a constant voltage output similar to that at the time of enable can be obtained even during the hold.
[0027]
As described above, according to the first embodiment, the sampling circuit 103 continuously turns on and off the differential circuit OP1, and outputs a control signal output by the differential circuit based on the on and off of the sampling circuit 103. When the signal line input to the circuit 101 is turned on and off, and the signal line is turned off, the input terminal of the output circuit 101 for inputting the control signal is held at the signal level before the signal line is turned off. Thus, since the change in the voltage at the input terminal of the output circuit 101 is eliminated, the power consumption of the constant voltage output circuit itself can be reduced, and the change in the output voltage can be reduced. Furthermore, since the change in the output voltage can be reduced, the output voltage can be brought close to the vicinity of the stop voltage of the target circuit to which power is supplied, and the power consumption of the target circuit can be reduced.
[0028]
In addition, since the holding circuit 105 includes a phase compensation capacitor, the number of components can be reduced by using a phase compensation capacitor generally provided in the constant voltage output circuit.
[0029]
Embodiment 2. FIG.
A constant voltage output circuit according to the second embodiment will be described with reference to FIGS. Since the configuration of the constant voltage output circuit of the second embodiment is the same as the configuration of the constant voltage output circuit of the first embodiment, the same parts as those in FIGS. 2 and 3 are denoted by the same reference numerals. The description will be omitted, and only different parts will be described.
[0030]
FIG. 5 is a schematic circuit diagram showing the configuration of the constant voltage output circuit of the second embodiment. The constant voltage output circuit according to the second embodiment includes a constant current source 501 as a load circuit instead of the resistors R1 and R2. The constant current source 501 is connected to the sampling circuit 103, and the sampling circuit 103 turns on and off the constant current source 501 that is a load circuit together with the differential circuit. Here, the output voltage VREG is obtained by the following equation.
VREG = Vref
[0031]
FIG. 6 is a circuit diagram showing a configuration of the constant voltage output circuit according to the second embodiment. In the constant voltage output circuit of the second embodiment, transistors QP22, QP21, QN21 and QP25 constitute a constant current source 501.
[0032]
In the above configuration, the operation of the second embodiment will be described. Since the operation of the second embodiment is the same as that of the first embodiment, the description of the same part is omitted, and only the different part will be described.
[0033]
When enabled, SP is high and SPX is low, transistors QP21 and QN21 are turned on, and transistors QP11 and QP25 constitute a current mirror circuit. A current determined by the characteristics of the transistor QP11 flows through the transistor QP25.
[0034]
At the time of holding, SP is at a low level and SPX is at a high level, the transistors QP21 and QN21 are turned off, and the transistor QP22 is turned on instead. The gate voltage of the transistor QP25 becomes high level via the transistor QP22, the transistor QP25 is turned off, and the current flowing through the transistor QP25 is stopped. Thereby, the power consumption of the constant voltage output circuit of Embodiment 2 is further reduced.
[0035]
As described above, according to the second embodiment, since the sampling circuit 103 turns on and off the load circuit together with the differential circuit, the power consumption of the constant voltage output circuit itself can be further reduced.
[0036]
Note that the feedback circuit 102 may be any type, for example, as shown in FIGS. 7 and 8, and the sampling circuit 103 may further include a circuit that generates the reference voltage Vref. You may make it turn on and off.
[0037]
【The invention's effect】
As described above, the constant voltage output circuit according to the present invention (claim 1) is for the sampling circuit to continuously turn on and off the feedback circuit and to input the control signal output from the feedback circuit to the output circuit. When the signal line is turned on / off based on the on / off of the sampling circuit, and the signal line is turned off, the input terminal of the output circuit for inputting the control signal is the signal before the signal line is turned off. Since the voltage at the input terminal of the output circuit is not changed by being held at the level, the power consumption of the constant voltage output circuit itself can be reduced and the change in the output voltage can be reduced.
[0038]
In the constant voltage output circuit of the present invention (claim 2), since the sampling circuit continuously turns on and off the differential circuit, the power consumption of the constant voltage output circuit itself can be reduced.
[0039]
The constant voltage output circuit according to the present invention (claim 3) has a constant voltage output because the sampling circuit continuously turns on and off the differential circuit, and further turns on and off the load circuit continuously. The power consumption of the circuit itself can be further reduced.
[0040]
The constant voltage output circuit of the present invention (claim 4) uses a phase compensation capacitor generally provided in the constant voltage output circuit because the holding circuit is composed of a phase compensation capacitor. As a result, the number of parts can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a constant voltage output circuit according to a first embodiment.
FIG. 2 is a schematic circuit diagram showing a configuration of a constant voltage output circuit according to the first embodiment.
FIG. 3 is a circuit diagram illustrating a configuration of a constant voltage output circuit according to the first embodiment;
FIG. 4 is a timing chart of signals SP and SPX output from the sampling circuit of the first embodiment.
FIG. 5 is a schematic circuit diagram showing a configuration of a constant voltage output circuit according to a second embodiment.
6 is a circuit diagram showing a configuration of a constant voltage output circuit according to a second embodiment; FIG.
FIG. 7 is a schematic circuit diagram showing another configuration of the constant voltage output circuit of the second embodiment.
FIG. 8 is a circuit diagram showing another configuration of the constant voltage output circuit of the second embodiment.
[Explanation of symbols]
101 Output Circuit 102 Feedback Circuit 103 Sampling Circuit 104 Switch 105 Holding Circuit

Claims (4)

In the constant voltage output circuit that supplies a constant voltage to the output terminal,
An output circuit connected to the output terminal;
A feedback circuit that feedback-inputs the output of the output circuit and outputs a control signal for controlling the output of the output circuit to an input terminal of the output circuit via a signal line ;
A sampling circuit for continuously turning on and off the feedback circuit;
A switch that is provided between the feedback circuit and the input terminal of the output circuit, and that turns on and off the signal line based on on and off of the sampling circuit;
A holding circuit provided between the output terminal and the input terminal of the output circuit;
With
Even if the feedback circuit is turned off, the holding circuit holds the input terminal of the output circuit at the signal level before the signal line is turned off when the signal line is turned off by the switch. A constant voltage output circuit, wherein a constant voltage is supplied to the output terminal. The feedback circuit is
A reference voltage generating circuit for generating a reference voltage;
A load circuit for the feedback input;
A differential circuit that inputs an output of the load circuit according to the reference voltage and the feedback input, and outputs the control signal;
The constant voltage output circuit according to claim 1, wherein the sampling circuit turns on and off the differential circuit. The feedback circuit is
A reference voltage generating circuit for generating a reference voltage;
A load circuit for the feedback input;
A differential circuit that inputs an output of the load circuit according to the reference voltage and the feedback input, and outputs the control signal;
The constant voltage output circuit according to claim 1, wherein the sampling circuit turns on and off the differential circuit and the load circuit.   The constant voltage output circuit according to claim 1, wherein the holding circuit includes a phase compensation capacitor.

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