JP2009123172A - Constant voltage circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a constant voltage circuit capable of suppressing variance in output voltage that is caused when the operation of an error amplifier circuit for high-speed operation is stopped to switch to an operation of only an error amplifier circuit for low-speed operation. <P>SOLUTION: In a bias current control circuit 7, a bias current ib of a second error amplifier circuit 4 is made large while a first error amplifier circuit 3 that can perform a high-speed operation is operated and the bias current ib of the second error amplifier circuit 4 is kept in a large state in the period when the variance in output voltage Vout is anticipated after the first error amplifier circuit 3 stops the operation, and the bias current ib of the second error amplifier circuit 4 is gradually switched taking time. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a constant voltage circuit for supplying power to a portable electronic device, and more particularly, to a constant voltage circuit having a low speed operation mode that operates with a low current consumption and a high speed operation mode that allows a high speed operation with a large current consumption. .

The conventional constant voltage circuit has an error amplifier circuit that consumes a large amount of current to improve ripple rejection ratio (PSRR) and load transient response, and an error that suppresses current consumption because high-speed response is not required. Some have an amplifier circuit.
For devices that have an operating state that operates with normal current consumption, such as a cellular phone, and a standby state that has a low current consumption, such as sleep mode, the use of a voltage regulator that has high-speed response results in high-speed response. In a standby state that does not require performance, the current consumption by the voltage regulator is larger than necessary.

In order to solve such problems, there has been a constant voltage circuit including an error amplifier circuit for high speed operation having a large current consumption but high speed response and an error amplifier circuit for low speed operation with reduced current consumption. (For example, refer to Patent Document 1). In such a constant voltage circuit, under conditions where the load current is small and high speed operation is not required, the output transistor is controlled only by the error amplifier circuit for low speed operation to perform constant voltage control, the load current is large, and high speed operation is possible. When required, an error amplifying circuit for high speed operation is operated in addition to an error amplifying circuit for low speed operation.
Japanese Patent No. 3710468

However, in such a constant voltage circuit, when the load current decreases and the operation of the error amplifying circuit for high speed operation is stopped and the operation is switched to the operation of only the error amplifying circuit for low speed operation, a large noise is generated in the output voltage. There was a problem that occurred. This is because it takes time to adjust the difference in output voltage caused by the difference between the offsets of the two error amplifier circuits.
If the output transistor controlled by the error amplifier circuit for high-speed operation is different from the output transistor controlled by the error amplifier circuit for low-speed operation, after stopping the error amplifier circuit for high-speed operation, It was necessary to greatly change the gate voltage of the output transistor controlled by the error amplifier circuit for low speed operation. However, since the drive capability of the error amplifier circuit for low-speed operation is small, the gate capacity of the output transistor controlled by the error amplifier circuit for low-speed operation cannot be instantaneously charged, and the time is further increased. There was a problem.

  The present invention has been made to solve such a problem, and an output generated when the operation of the error amplifying circuit for high speed operation is stopped and the operation is switched to the operation of only the error amplifying circuit for low speed operation. It is an object of the present invention to obtain a constant voltage circuit capable of suppressing voltage fluctuation.

In the constant voltage circuit according to the present invention, a current corresponding to a signal input to the control electrode is supplied from the input terminal to the output terminal so that a proportional voltage proportional to the output voltage output from the output terminal becomes a predetermined reference voltage. In a constant voltage circuit that performs operation control of at least one output transistor that outputs, converts an input voltage input to the input terminal into a predetermined constant voltage, and outputs the voltage from the output terminal.
The operation of the output transistor is controlled so that the proportional voltage proportional to the output voltage output from the output terminal becomes a predetermined reference voltage, and the operation or operation is stopped according to the input control signal. Error amplification circuit section of
A second error amplifying circuit section that is always operated to control the operation of the output transistor so that a proportional voltage proportional to the output voltage output from the output terminal becomes a predetermined reference voltage;
A bias current control circuit unit that controls a bias current of the second error amplification circuit unit in response to the control signal;
With
The bias current control circuit unit is configured such that the second error amplification circuit unit is more active when the first error amplification circuit unit is operating than when the first error amplification circuit unit is not operating. The bias current is increased.

  Specifically, the bias current control circuit unit has a predetermined first bias current with respect to the second error amplification circuit unit while the operation of the first error amplification circuit unit is stopped. The current value is controlled so that the bias current becomes a second current value larger than the first current value while the first error amplifying circuit unit is operating.

  In this case, when the first error amplification circuit unit stops operating in response to the control signal, the bias current control circuit unit performs the second current until the first predetermined time elapses after the operation is stopped. The bias current of the error amplifying circuit section is held at the second current value.

  In addition, when the first error amplification circuit unit stops operating in response to the control signal, the bias current control circuit unit applies the bias current of the second error amplification circuit unit over a second predetermined time to the first error amplification circuit unit. The current value is decreased from 2 current values to the first current value.

  In addition, when the first error amplification circuit unit starts to operate in response to the control signal, the bias current control circuit unit applies the bias current of the second error amplification circuit unit over a third predetermined time to the first error amplification circuit unit. The current value is increased from the current value to the second current value.

  In addition, an output current detection circuit unit that generates and outputs the control signal according to the current value of the output current output from the output terminal, and the output current detection circuit unit outputs output from the output terminal When the current exceeds a predetermined value, the first error amplification circuit unit is activated, and when the output current output from the output terminal is less than the predetermined value, the operation of the first error amplification circuit unit is stopped. I made it.

Specifically, the bias current control circuit unit includes:
A capacitor,
A first constant current circuit unit that charges the capacitor in response to the control signal;
A second constant current circuit section for discharging the capacitor in response to the control signal;
A voltage clamping circuit section for clamping the charging voltage of the capacitor to a predetermined voltage;
A third constant current circuit unit for additionally supplying a bias current to the second error amplification circuit unit;
A MOS transistor that controls supply of a constant current from the third constant current circuit unit to the second error amplification circuit unit in accordance with a charging voltage of the capacitor;
With
The voltage clamping circuit section clamps the charging voltage of the capacitor when the charging voltage of the capacitor becomes a voltage larger by a predetermined voltage value than a gate voltage value at which the MOS transistor is saturated.

  According to the constant voltage circuit of the present invention, the current consumption is smaller than that of the first error amplification circuit unit that can perform high-speed operation that stops or operates according to the control signal, and the first error amplification circuit unit. A second error amplification circuit unit that is always operated, and the bias current control circuit unit stops the operation of the first error amplification circuit unit while the first error amplification circuit unit is operating. The bias current of the second error amplification circuit unit is increased more than when the first error amplification circuit unit is operating. Specifically, when the operation of the first error amplification circuit unit is stopped, the second error amplification circuit unit When the bias current of the circuit unit is set to the first current value and the first error amplifier circuit unit is operating, the bias current of the second error amplifier circuit unit is set to a second current value larger than the first current value. It was made to become. This suppresses fluctuations in the output voltage that occur when the operation of the first error amplification circuit unit for high speed operation is stopped and the operation is switched to the operation of only the second error amplification circuit unit for low speed operation. Can do.

  In addition, since the bias current is gradually switched with respect to the second error amplifier circuit unit, it is possible to suppress fluctuations in the output voltage due to fluctuations in the bias current. For this reason, high-speed response is possible, and the fluctuation of the output voltage can be reduced with high efficiency.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram showing a circuit example of a constant voltage circuit according to the first embodiment of the present invention.
In FIG. 1, a constant voltage circuit 1 generates a predetermined constant voltage from an input voltage Vdd input to an input terminal IN, and outputs it from an output terminal OUT as an output voltage Vout.
The constant voltage circuit 1 includes a reference voltage generation circuit 2 that generates and outputs a predetermined reference voltage Vref, and output voltage detection resistors R1 and R2 that divide the output voltage Vout to generate and output a divided voltage Vfb. The first output transistor M1 composed of a PMOS transistor that controls the current iout output to the output terminal OUT according to the signal input to the gate, and the current output to the output terminal OUT according to the signal input to the gate and a second output transistor M2 composed of a PMOS transistor for controlling iout.

  The constant voltage circuit 1 includes a first error amplification circuit 3 that controls the operation of the first output transistor M1 so that the divided voltage Vfb becomes the reference voltage Vref, and the divided voltage Vfb becomes the reference voltage Vref. As described above, the second error amplification circuit 4 that controls the operation of the second output transistor M2 is provided. Further, the constant voltage circuit 1 includes a reference voltage generation circuit 5 that generates and outputs a predetermined reference voltage Vs, a comparator 6, and a bias current control circuit 7 that controls the bias current ib of the second error amplification circuit 4. And an inverter 8, PMOS transistors M3 and M4, switches SW1 and SW2, and a resistor R3. The first error amplifying circuit 3 is a first error amplifying circuit, the second error amplifying circuit 4 is a second error amplifying circuit, and the bias current control circuit 7 is a bias current control circuit. The reference voltage generation circuit 5, the comparator 6, the PMOS transistors M3 and M4, and the resistor R3 form an output current detection circuit unit.

  A first output transistor M1 and a second output transistor M2 are connected in parallel between the input terminal IN and the output terminal OUT, and the output terminal of the first error amplifier circuit 3 is connected to the gate of the first output transistor M1. The output terminal of the second error amplifier circuit 4 is connected to the gate of the second output transistor M2. Further, a series circuit of resistors R1 and R2 is connected between the output terminal OUT and the ground voltage GND, and the divided voltage Vfb is output from a connection portion between the resistors R1 and R2. A reference voltage Vref is input to each inverting input terminal of the first error amplifying circuit 3 and the second error amplifying circuit 4, and each of the first error amplifying circuit 3 and the second error amplifying circuit 4 is not connected. The divided voltage Vfb is input to each inverting input terminal.

  PMOS transistors M3 and M4 are connected in parallel between the input voltage Vdd and the non-inverting input terminal of the comparator 6, and a resistor R3 is connected between the non-inverting input terminal of the comparator 6 and the ground voltage GND. ing. The gate of the PMOS transistor M3 is connected to the output terminal of the first error amplification circuit 3 and is connected to the input voltage Vdd via the switch SW1, and the gate of the PMOS transistor M4 is the output of the second error amplification circuit 4. Connected to the end. The reference voltage Vs is input to the inverting input terminal of the comparator 6, and the control signal Sc output from the comparator 6 is input to the bias current control circuit 7 and the control electrode of the switch SW 2, and is switched via the inverter 8. Input to the control electrode of SW1. The switch SW2 is connected between the output terminal of the first error amplifier circuit 3 and the output terminal of the second error amplifier circuit 4, and the bias current control circuit 7 is connected to the bias of the second error amplifier circuit 4. The current ib is controlled.

  In such a configuration, the first error amplification circuit 3 is designed so that the bias current is as large as possible so that high-speed operation can be performed. On the other hand, the second error amplifier circuit 4 is designed so that the bias current is as small as possible so that the direct current gain is as large as possible and the direct current characteristics are excellent. The second error amplifying circuit 4 is always operating, and the first error amplifying circuit 3 operates only when the control signal Sc output from the comparator 6 is at a high level, and operates when the control signal Sc is at a low level. When the operation is stopped, almost no current is consumed. In addition, when the input control signal Sc is at a low level, the bias current control circuit 7 causes the bias current ib having a predetermined first current value ib1 to flow through the second error amplification circuit 4, and the control signal Sc Becomes a high level, the bias current ib of the second error amplifier circuit 4 is increased from the first current value ib1 to a predetermined second current value (ib1 + ib2).

  On the other hand, the PMOS transistor M3 outputs a drain current proportional to the drain current of the first output transistor M1, and the PMOS transistor M4 outputs a drain current proportional to the drain current of the second output transistor M2. . Since the sum of the drain currents of the first output transistor M1 and the second output transistor M2 is substantially equal to the output current iout, the sum of the drain currents of the PMOS transistors M3 and M4 is a current proportional to the output current iout. become. Since the drain currents of the PMOS transistors M3 and M4 are respectively supplied to the resistor R3, a voltage V3 is generated at both ends of the resistor R3, and the voltage V3 becomes a voltage proportional to the output current iout.

  When the voltage V3 is lower than the reference voltage Vs, the comparator 6 outputs a low level control signal Sc, and when the voltage V3 is equal to or higher than the reference voltage Vs, the comparator 6 outputs a high level control signal Sc. However, the comparator 6 may have a hysteresis voltage in order to stabilize the operation. In this case, the control signal Sc output from the comparator 6 changes from low level to high level and from high level to low level. The voltage V3 when reaching the level is not the same. The switch SW1 is turned on and conductive when the control signal Sc is at a low level, and is turned off and blocked when the control signal Sc is at a high level. On the other hand, the switch SW2 is turned off when the control signal Sc is at a low level and is turned off, and is turned on when the control signal Sc is at a high level and is turned on.

  When the control signal Sc is at a low level, the first error amplifier circuit 3 stops operating, and the first output transistor M1 and the PMOS transistor M3 have their gates connected to the input voltage Vdd by the switch SW1, respectively. Turn off and shut off. At this time, since the switch SW2 is turned off and in the cut-off state, the second error amplification circuit 4 controls only the second output transistor M2 so that the divided voltage Vfb becomes the reference voltage Vref, and outputs the output voltage. Vout is stabilized. Further, since the bias current ib is reduced to the first current value ib1 in the second error amplifier circuit 4, the consumption current of the constant voltage circuit 1 becomes a very small value.

When the output current iout increases and the voltage V3 becomes equal to or higher than the reference voltage Vs, the comparator 6 inverts the signal level of the control signal Sc to a high level. That is, the comparator 6 sets the control signal Sc to a high level when the output current iout becomes larger than a predetermined value.
When the control signal Sc becomes a high level, the switch SW1 is turned off to be in a cut-off state, and the switch SW2 is turned on to be in a conductive state. Therefore, the gates of the first output transistor M1 and the PMOS transistor M3 are each disconnected from the input voltage Vdd and connected to the gate of the second output transistor M2.

Further, since the first error amplifier circuit 3 starts operation, the first output transistor M1 and the second output transistor M2 are connected to the first error amplifier circuit 3 so that the divided voltage Vfb becomes the reference voltage Vref. And controlled by each output signal of the second error amplifier circuit 4. Further, the bias current ib of the second error amplifier circuit 4 increases from the first current value ib1 to the second current value (ib1 + ib2).
As described above, when the output current iout is large, the bias current ib of the second error amplifier circuit 4 is increased. However, the increased bias current ib is much larger than the consumption current of the first error amplifier circuit 3. Therefore, the power efficiency is hardly affected.

Next, FIG. 2 is a timing chart showing an operation example of the constant voltage circuit 1 of FIG. 1, and the operation of the constant voltage circuit 1 of FIG. 1 will be described in a little more detail with reference to FIG. The time Td is a first predetermined time, the time Tf is a second predetermined time, and the time Tr is a third predetermined time.
In FIG. 2, when the control signal Sc becomes high level at time T0, the first error amplifier circuit 3 starts operation. At the same time, the bias current control circuit 7 increases the bias current ib of the second error amplifier circuit 4 from the first current value ib1 to the second current value (ib1 + ib2). However, the bias current control circuit 7 does not increase the bias current ib instantaneously, but increases it over time Tr as shown in FIG. For this reason, the output voltage Vout hardly fluctuates as the bias current of the second error amplifier circuit 4 is changed.

Next, when the control signal Sc falls to a low level at time T1, the first error amplification circuit 3 stops operating, but the bias current control circuit 7 uses the bias current ib of the second error amplification circuit 4 as a result. It is still held at the second current value (ib1 + ib2). Accordingly, the response speed of the second error amplifier circuit 4 maintains high speed performance, and the gate voltage of the second output transistor M2 can be immediately controlled with respect to the fluctuation of the output voltage Vout, and the output voltage Vout Can be suppressed.
Next, at time T2 when a predetermined time Td has elapsed from time T1, the bias current control circuit 7 gradually decreases the bias current ib of the second error amplifier circuit 4 from the second current value (ib1 + ib2), The bias current ib is returned to the first current value ib1 at a time T3 after a predetermined time Tf has elapsed since the start of the decrease. As described above, by gradually decreasing the bias current ib of the second error amplifier circuit 4, it is possible to suppress the fluctuation of the output voltage Vout based on the fluctuation of the bias current ib.

Next, FIG. 3 is a diagram showing a circuit example of the bias current control circuit 7. In FIG. 3, the second error amplification circuit 4 shows only the first-stage differential amplification circuit section necessary for explaining the operation of the bias current control circuit 7, and the next-stage amplification circuit section is omitted. is doing.
In FIG. 3, the differential amplifier circuit portion of the second error amplifier circuit 4 is composed of PMOS transistors M11 and M12 and NMOS transistors M13 to M15.
The NMOS transistors M13 and M14 form a differential pair, with the gate of the NMOS transistor M13 serving as the inverting input terminal of the second error amplifier circuit 4, and the gate of the NMOS transistor M14 being non-inverted of the second error amplifier circuit 4. It is the input end.

  The PMOS transistors M11 and M12 form a current mirror circuit and form a load on the differential pair. In the PMOS transistors M11 and M12, the sources are connected to the input voltage Vdd, the gates are connected, and the connection is connected to the drain of the PMOS transistor M11. The drain of the PMOS transistor M11 is connected to the drain of the NMOS transistor M13. The drain of the PMOS transistor M12 is connected to the drain of the NMOS transistor M14, and this connection portion forms the output terminal of the differential amplifier circuit portion of the second error amplifier circuit 4, and is connected to a subsequent amplifier circuit portion (not shown). . The sources of the NMOS transistors M13 and M14 are connected, and the NMOS transistor M15 is connected between the connection portion and the ground voltage GND. A predetermined bias voltage Vb is input to the gate of the NMOS transistor M15, and the NMOS transistor M15 forms a constant current source that supplies a bias current ib having a first current value ib1 to the differential pair.

Next, the bias current control circuit 7 includes a PMOS transistor M21, NMOS transistors M22 to M28, a capacitor Ct, an inverter 21, and constant current sources 22 to 24. The PMOS transistor M21 and the constant current source 22 are the first constant current circuit unit, the NMOS transistor M22 and the constant current source 23 are the second constant current circuit unit, and the constant current source 24 is the third constant current circuit unit. The NMOS transistors M23 to M25 form a voltage clamp circuit unit.
In the PMOS transistor M21 and the NMOS transistor M22, each drain is connected and each gate is connected, and a control signal Sc is input to each gate via the inverter 21. A current source 22 is connected between the input voltage Vdd and the source of the PMOS transistor M21, and a current source 23 is connected between the source of the NMOS transistor M22 and the ground voltage GND.

  The connection portion of each drain of the PMOS transistor M21 and the NMOS transistor M22 is connected to the gate of the NMOS transistor M26. Between the gate of the NMOS transistor M26 and the ground voltage GND, a series circuit of NMOS transistors M23 to M25 and a capacitor are connected. Ct is connected in parallel. The gate and drain of the NMOS transistor M23 are connected to form a diode. Similarly, the gate and drain of the NMOS transistor N24 are connected to form a diode. The control signal Sc is input to the gate of the NMOS transistor M25.

  A current source 24 is connected between the input voltage Vdd and the drain of the NMOS transistor M26, and the source of the NMOS transistor M26 is connected to the drain of the NMOS transistor M27. The NMOS transistors M27 and M28 form a current mirror circuit. In the NMOS transistors M27 and M28, the sources are connected to the ground voltage GND, the gates are connected, and the connection is connected to the drain of the NMOS transistor M27. Has been. The drain of the NMOS transistor M28 is connected to the drain of the NMOS transistor M15.

  When the control signal Sc is at a low level, the output signal of the inverter 21 is at a high level, the PMOS transistor M21 is turned off and turned off, and the NMOS transistor M22 is turned on and turned on. At the same time, the NMOS transistor M25 is turned off and is turned off. Since the NMOS transistor M22 is on, the charge of the capacitor Ct is discharged by the current source 23. For this reason, the gate voltage of the NMOS transistor M26 is substantially equal to the ground voltage GND, and the NMOS transistor M26 is turned off to be cut off. When the NMOS transistor M26 is turned off, the drain current of the NMOS transistor M27 does not flow, and the drain current of the NMOS transistor M28 becomes zero. That is, when the control signal Sc is at a low level, the bias current ib of the differential amplifier circuit portion of the second error amplifier circuit 4 is only the first current value ib1 that is the drain current of the NMOS transistor M15.

  When the control signal Sc changes from low level to high level at time T0, the output signal of the inverter 21 becomes low level. For this reason, since the PMOS transistor M21 is turned on and the NMOS transistor M22 is turned off, the capacitor Ct is charged by the constant current source 22 and the voltage of the capacitor Ct rises. Since the voltage of the capacitor Ct is applied to the gate of the NMOS transistor M26, the drain current of the NMOS transistor M26 increases over time determined by the capacitance of the capacitor Ct and the constant current i1 from the constant current source 22. To do. The drain current of the NMOS transistor M26 becomes the drain current of the NMOS transistor M27 and the drain current of the NMOS transistor M28.

  The drain current of the NMOS transistor M28 becomes the bias current of the differential amplifier circuit section of the second error amplifier circuit 4, and the bias current ib of the differential amplifier circuit section of the second error amplifier circuit 4 increases. When the NMOS transistor M26 is completely turned on, the drain current of the NMOS transistor M26 has the same current value as the constant current i3 from the constant current source 24, and the current proportional to the constant current i3 is the drain current value ib2 of the NMOS transistor M28. become. That is, the bias current ib of the second error amplifier circuit 4 increases from the first current value ib1 to the second current value (ib1 + ib2). As described above, since the bias current ib is increased over time, fluctuations in the output voltage Vout accompanying fluctuations in the bias current ib can be suppressed.

  Note that when the control signal Sc is at a high level, the NMOS transistor M25 is turned on, so that a series circuit of diode-connected NMOS transistors M23 and M24 is connected in parallel to the capacitor Ct. The sum of the gate threshold voltages of the NMOS transistors M23 and M24 is set to be slightly larger than the sum of the gate threshold voltages of the NMOS transistors M26 and M27. For this reason, the charging voltage of the capacitor Ct further rises after the NMOS transistor M26 is completely turned on, and is clamped at the sum of the gate threshold voltages of the NMOS transistors M23 and M24. That is, the NMOS transistors M23 and M24 form a voltage clamp circuit that clamps the charging voltage of the capacitor Ct.

  Next, when the control signal Sc falls from the high level to the low level at time T1, the output signal of the inverter 21 becomes the high level. For this reason, the PMOS transistor M21 is turned off to stop charging the capacitor Ct, and the NMOS transistor M22 is turned on to discharge the charge of the capacitor Ct with the constant current i2 from the constant current source 23. At this time, since the NMOS transistor M25 is off, the voltage clamp circuit does not operate.

  Since the charging voltage of the capacitor Ct at time T1 is set to a voltage slightly higher than the voltage at which the NMOS transistor M26 is turned on as described above, the NMOS transistor until time T2 even if discharge by the constant current source 23 is started. The drain current of M26 maintains the current value of the constant current i3. That is, the bias current ib maintains the second current value (ib1 + ib2) during the time Td from time T1 to T2. For this reason, as described above, even after the operation of the first error amplifier circuit 3 is stopped, the second error amplifier circuit 4 can perform a high-speed operation, and a large fluctuation in the output voltage Vout can be suppressed. it can.

After the time T2, since the drain current of the NMOS transistor M26 becomes smaller than the constant current i3, the bias current ib of the second error amplifier circuit 4 gradually decreases.
At time T3, the voltage of the capacitor Ct becomes equal to or lower than the sum of the gate threshold voltages of the NMOS transistors M26 and M27, and the NMOS transistor M26 is turned off. Therefore, the drain current of the NMOS transistor M28 is also 0, and the bias current ib of the second error amplifier circuit 4 is only the first current value ib1. By changing the bias current ib of the second error amplifier circuit 4 from the second current value (ib1 + ib2) to the first current value ib1 over time, the fluctuation of the output voltage Vout due to the fluctuation of the bias current is suppressed. can do.

  As described above, the constant voltage circuit according to the first embodiment increases the bias current ib of the second error amplifier circuit 4 while the first error amplifier circuit 3 capable of high-speed operation is operating. Since the bias current ib of the second error amplifying circuit 4 is kept large during a period in which the fluctuation of the output voltage Vout is expected after the operation of the first error amplifying circuit 3 is stopped, the output voltage Vout Can be suppressed. Furthermore, since the switching of the bias current ib is gradually performed over time, the fluctuation of the output voltage Vout due to the fluctuation of the bias current ib can be suppressed. In this way, a constant voltage circuit capable of high-speed response, high efficiency and small output fluctuation can be realized.

In FIG. 3, the first-stage differential amplifier circuit portion is shown as a portion for controlling the bias current ib of the second error amplifier circuit 4. However, the present invention is not limited to this and is shown in the figure. The constant current value of the load circuit composed of the constant current source used for the load of the amplifier circuit unit after the next stage may be controlled by the same method.
In the above description, the control signal Sc is generated according to the current value of the output current iout. However, the present invention is not limited to this, and is output from a control circuit such as a CPU. Also good.

  In the above description, the first and second output transistors M1 and M2 are provided as an example. However, the present invention is not limited to this, and at least one output transistor is provided as the first output transistor. It can also be applied to the case where the operation is controlled by the second error amplifying circuits 3 and 4.

It is the figure which showed the circuit example of the constant voltage circuit in the 1st Embodiment of this invention. 2 is a timing chart showing an operation example of the constant voltage circuit 1 of FIG. 1. It is the figure which showed the circuit example of the bias current control circuit 7 of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Constant voltage circuit 2 Reference voltage generation circuit 3 1st error amplification circuit 4 2nd error amplification circuit 5 Reference voltage generation circuit 6 Comparator 7 Bias current control circuit 8 Inverter M1 1st output transistor M2 2nd output transistor M3 , M4 PMOS transistor SW1, SW2 switch R1-R3 resistance

Claims (7)

Operation of at least one output transistor that outputs a current corresponding to a signal input to the control electrode from the input terminal to the output terminal so that a proportional voltage proportional to the output voltage output from the output terminal becomes a predetermined reference voltage In a constant voltage circuit that performs control and converts the input voltage input to the input terminal to a predetermined constant voltage and outputs the voltage from the output terminal,
The operation of the output transistor is controlled so that the proportional voltage proportional to the output voltage output from the output terminal becomes a predetermined reference voltage, and the operation or operation is stopped according to the input control signal. Error amplification circuit section of
A second error amplifying circuit section that is always operated to control the operation of the output transistor so that a proportional voltage proportional to the output voltage output from the output terminal becomes a predetermined reference voltage;
A bias current control circuit unit that controls a bias current of the second error amplification circuit unit in response to the control signal;
With
The bias current control circuit unit is configured such that the second error amplification circuit unit is more active when the first error amplification circuit unit is operating than when the first error amplification circuit unit is not operating. A constant voltage circuit characterized by increasing the bias current.   The bias current control circuit unit is configured such that the bias current becomes a predetermined first current value with respect to the second error amplification circuit unit while the operation of the first error amplification circuit unit is stopped. The bias current is controlled to be a second current value larger than the first current value while the first error amplification circuit unit is operating. Constant voltage circuit.   When the first error amplification circuit unit stops operating by the control signal, the bias current control circuit unit performs the second error amplification until a first predetermined time elapses after the operation is stopped. 3. The constant voltage circuit according to claim 2, wherein the bias current of the circuit unit is held at the second current value.   When the first error amplification circuit unit stops operating in response to the control signal, the bias current control circuit unit sets the bias current of the second error amplification circuit unit to the second current over a second predetermined time. 4. The constant voltage circuit according to claim 2, wherein the constant voltage circuit is reduced from a value to the first current value.   When the first error amplification circuit unit starts to operate in response to the control signal, the bias current control circuit unit applies the bias current of the second error amplification circuit unit over the third predetermined time to the first current. 5. The constant voltage circuit according to claim 2, wherein the constant voltage circuit is increased from a value to the second current value.   An output current detection circuit unit that generates and outputs the control signal according to the current value of the output current output from the output terminal, and the output current detection circuit unit outputs an output current output from the output terminal; The first error amplification circuit unit is activated when the value exceeds a predetermined value, and the operation of the first error amplification circuit unit is stopped when the output current output from the output terminal becomes less than a predetermined value. The constant voltage circuit according to claim 1, 2, 3, 4, or 5. The bias current control circuit unit includes:
A capacitor,
A first constant current circuit unit that charges the capacitor in response to the control signal;
A second constant current circuit section for discharging the capacitor in response to the control signal;
A voltage clamping circuit section for clamping the charging voltage of the capacitor to a predetermined voltage;
A third constant current circuit unit for additionally supplying a bias current to the second error amplification circuit unit;
A MOS transistor that controls supply of a constant current from the third constant current circuit unit to the second error amplification circuit unit in accordance with a charging voltage of the capacitor;
With
The voltage clamp circuit unit clamps the charge voltage of the capacitor when the charge voltage of the capacitor becomes a voltage larger by a predetermined voltage value than a gate voltage value at which the MOS transistor is saturated. The constant voltage circuit according to claim 1, 2, 3, 4, 5 or 6.

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