JP2007310521A - Constant voltage circuit and electronic apparatus equipped therewith - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-power consumption constant voltage circuit for responding to a small variation in an output voltage and an electronic apparatus equipped therewith. <P>SOLUTION: The constant voltage circuit is provided with an output transistor M1 connected between an input voltage Vdd and an output voltage Vo; and an error amplifying circuit 11 receiving an input of a voltage obtained by dividing a reference voltage Vref and an output voltage Vo, amplifying the difference of them, and outputting the input, and controls the output transistor M1 by the output of the error amplifying circuit 11; an output voltage variation detection circuit 12 for detecting the variation of the output voltage Vo; and a bias current amplifying circuit 13 for increasing a bias current of the error amplifying circuit 11. The bias current amplifying circuit 13 is operated by the output of the output voltage variation detection circuit 12 during the variation of the output voltage Vo, and the bias current of the error amplifying circuit 11 is increased to achieve high speed operation. The output voltage variation detection circuit 12 may be provided with both or either of a comparator 21 useful in a voltage rise and/or a comparator 22 useful in a voltage fall. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a constant voltage circuit technique, and more particularly, to a constant voltage circuit excellent in output voltage response characteristics and an electronic device incorporating the constant voltage circuit.

  In recent years, portable electronic devices using battery operation such as mobile phones, mobile computers, digital cameras, and portable music devices have become widespread. These portable electronic devices are strongly required to extend battery life and improve usability, and to reduce current consumption (power saving) from environmental considerations. Power saving is no exception in power circuits.

  When the power supply circuit is reduced in power consumption, the response speed of the power supply generally decreases, the rise of the power supply becomes slow, and fluctuations in the output voltage due to power supply fluctuations and load fluctuations increase. Conversely, if the characteristics such as response speed and rise speed are to be improved, the current consumption of the power supply circuit increases.

  Therefore, a method has been conventionally proposed in which the current consumption of the power supply circuit is increased only when necessary to improve response characteristics, and when the output voltage is stable, the current consumption is reduced.

  FIG. 7 shows an example of a constant voltage circuit disclosed in FIG. 2 of Japanese Patent Application Laid-Open No. 2004-164411 (Patent Document 1).

  As shown in the figure, the constant voltage circuit includes a reference voltage circuit 31, an error amplifying circuit 32, a current adding circuit 33, an output transistor M1, and resistors R1 and R2. Further, the input voltage VE is applied to the constant voltage circuit.

  The output transistor M1 is composed of a PMOS transistor, and is connected between the input voltage VE and the output terminal Vo.

  The output voltage Vo is divided by resistors R1 and R2, and the divided voltage Vfb is connected to the gate of an NMOS transistor M14 which is a non-inverting input of the error amplifier circuit 32.

  The error amplifier circuit 32 is a differential amplifier circuit composed of MOS transistors M11 to M15. The gate of the NMOS transistor M13 is an inverting input, and the gate of the NMOS transistor M14 is a non-inverting input.

  The PMOS transistors M11 and M12 constitute a current mirror circuit, which is a load of the differential amplifier circuit. A bias voltage Vb is applied to the gate of the NMOS transistor M15, and a constant bias current is supplied to the differential amplifier circuit.

  The output voltage Vref of the reference voltage circuit 31 is applied to the inverting input of the error amplifier circuit 32, and the voltage Vfb obtained by dividing the output voltage Vo as described above is applied to the non-inverting input, and the output is the output transistor. Since it is connected to the gate of M1, the error amplification circuit 32 controls the output transistor M1 so that the voltage Vfb becomes equal to the reference voltage Vref.

  The current adding circuit 33 includes NMOS transistors M16 to M18, an inverter 34, a bias power supply Vb, and resistors R3 to R5. Since the resistors R3 and R4 are connected in series and connected between the output terminal Vo and the ground potential, the voltage V1 at the intersection of the resistors R3 and R4 is a voltage proportional to the output voltage Vo.

  The source of the NMOS transistor M17 is grounded (GND), the drain of the NMOS transistor M17 is connected to the input voltage VE through the resistor R5, and the voltage V1 at the intersection of the resistors R3 and R4 is applied to the gate of the NMOS transistor M17. Yes.

  The input of the inverter 34 is connected to the drain of the NMOS transistor M17, and the output of the inverter 34 is connected to the gate of the NMOS transistor M18.

  The drain of the MOS transistor M18 is connected to the common source of the input transistors M13 and M14 of the differential amplifier circuit, and the source of the MOS transistor M18 is connected to the drain of the NMOS transistor M16.

  Since the source of the NMOS transistor M16 is grounded (GND) and the bias voltage Vb is applied to the gate of the NMOS transistor M16, the drain current of the NMOS transistor M16 is a constant current source.

  When the output voltage Vo is the rated output voltage, the resistance values of the resistors R3 and R4 are set so that the voltage V1 at the intersection of the resistors R3 and R4 is slightly lower than the threshold voltage of the NMOS transistor M17.

  In this state, the NMOS transistor M17 is off, so the drain voltage of the NMOS transistor M17 is at a high level, and the inverter 34 outputs a low level.

  As a result, the NMOS transistor M18 is turned off, so that the constant current source constituted by the NMOS transistor M16 is not applied to the error amplifier circuit 32.

  However, if the output voltage Vo rises for some reason and the voltage V1 exceeds the threshold voltage of the NMOS transistor M17, the NMOS transistor M17 is turned on, so that the drain voltage of the NMOS transistor M17 becomes low level and the inverter 34 becomes high. Output level. As a result, the NMOS transistor M18 is turned on, and the constant current source formed by the NMOS transistor M16 is added to the error amplifier circuit 32 as a bias current.

  When the bias current of the error amplifier circuit 32 increases, the operation speed of the error amplifier circuit 32 increases, so that the increase in the output voltage Vo can be quickly returned to the original rated output voltage.

JP 2004-164411 A

  However, the above prior art can only cope with overshoot of the output voltage Vo, and occurs when the rise time of the constant voltage circuit is shortened, the load current suddenly increases, or the input voltage suddenly decreases. The problem is that it cannot cope with the undershoot of the output voltage Vo.

  Also, the voltage V1 at the intersection of the resistors R3 and R4 must be set to a voltage that is exactly slightly lower than the threshold value of the NMOS transistor M17. In general, the threshold value of a MOS transistor varies depending on the manufacturing process. Considering this fact, since at least one of the resistors R3 and R4 needs to be adjusted by trimming, there is a problem that an increase in chip area and an increase in cost are inevitable.

  Further, even if the voltage V1 is adjusted to a voltage slightly lower than the threshold value of the NMOS transistor M17 by trimming, the MOS transistor threshold value has temperature characteristics. Therefore, considering the temperature characteristics, the voltage V1 at normal temperature is equal to the threshold value of the NMOS transistor M17. Since the voltage must be much lower, there is a problem that only a considerably large overshoot voltage can be handled at room temperature.

  Furthermore, since current always flows through the resistors R3 and R4, there is a problem that power saving is hindered.

  The present invention has been made in consideration of the above-described circumstances, solves the above-described problems, can respond quickly to small output voltage fluctuations, and has a low power consumption, and the constant voltage circuit. It is an object to provide an electronic device with a built-in.

  The present invention has the following configuration in order to solve the above problems. Hereinafter, the constitution for each claim and the effect thereof will be described.

a) In claim 1, an output transistor connected between an input terminal for applying an input voltage and an output terminal for outputting an output voltage, a reference voltage and a voltage obtained by dividing the output voltage are input, and A constant voltage circuit for generating a constant output voltage by controlling the output transistor according to an output of the error amplifier circuit, wherein the change of the output voltage is detected. An output voltage fluctuation detecting circuit for detecting; and a bias current increasing circuit for increasing a bias current of the error amplifying circuit, and during the fluctuation of the output voltage, the bias current increasing circuit according to the output of the output voltage fluctuation detecting circuit. Since the bias current of the error amplifier circuit is increased, a quick response to a small output voltage fluctuation is possible.

  According to a second aspect of the present invention, the output voltage fluctuation detection circuit operates the bias current increasing circuit while the output voltage is increasing. In the third aspect of the invention, the output voltage fluctuation detection circuit The fluctuation detection circuit operates the bias current increasing circuit while the output voltage is decreasing. Which method is selected may be determined according to the characteristics of the constant voltage circuit.

  According to a fourth aspect of the present invention, the output voltage fluctuation detecting circuit operates the bias current increasing circuit while the output voltage is rising and falling, so that it responds to any constant voltage circuit. You can increase the speed.

  In the fifth aspect of the invention, the output voltage fluctuation detection circuit detects the AC component of the output voltage, so that it is possible to eliminate the current that was always flowing through the resistor that detects the output voltage. Electricity can be achieved.

  In the invention according to claim 6, the output voltage fluctuation detection circuit includes a comparator in which a capacitor and one or more resistors are connected in series between the output voltage and a ground potential, and a voltage at both ends of the resistor is input. Since the bias current increasing circuit is operated by the output of the comparator, even a small fluctuation in the output voltage can cope with an increase in the bias current, and the response speed can be increased.

  According to a seventh aspect of the present invention, there is provided a first comparator that operates the bias current increasing circuit while the output voltage is increasing, and a second comparator that operates the bias current increasing circuit while the output voltage is decreasing. Therefore, even a small fluctuation in both the rising and falling directions of the output voltage can cope with the increase of the bias current, and the response speed can be increased.

  In the invention according to claim 8, since the offset voltage is given to the input of the comparator, the bias current can be surely reduced when the output voltage is stable.

  In the invention according to claim 9, since the hysteresis voltage is given to the input of the comparator, a stable operation is possible.

  According to a tenth aspect of the present invention, by incorporating the constant voltage circuit according to any one of the first to ninth aspects, an electronic apparatus having a built-in constant voltage circuit having the effects of the inventions according to the respective claims. Can be realized.

  According to the present invention, since the fluctuation of the output voltage is a voltage drop of the resistor via the capacitor and the voltage is detected by the comparator, the bias current of the error amplifier circuit can be increased even with a small fluctuation of the output voltage. I can do it now.

  Further, unlike the conventional example, current does not always flow through the resistor, and power saving can be achieved.

  Furthermore, since two comparators are provided and the bias current of the error amplifier circuit can be increased in both the rising and falling directions of the output voltage, the response speed can be increased both in rising and falling.

  Furthermore, since an offset voltage is provided at the input of the comparator, the bias current can be reliably reduced when the output voltage is stable. Furthermore, since a hysteresis voltage is provided at the input of the comparator, stable operation is possible.

  Further, by incorporating the constant voltage circuit according to the present invention into an electronic device, an electronic device incorporating the constant voltage circuit having the above-described effects can be obtained.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a configuration diagram of a constant voltage circuit according to a first embodiment of the present invention.

  As shown in the figure, the constant voltage circuit according to this embodiment includes a reference voltage Vref, an error amplifier circuit 11, an output transistor M1, a bias current source I1, resistors R1 and R2, an output voltage fluctuation detection circuit 12, and a bias current increase. The circuit 13 is configured.

  Further, the reference voltage Vref is applied to the inverting input of the error amplifier circuit 11, and the voltage Vfb obtained by dividing the output voltage Vo by the resistors R1 and R2 is applied to the non-inverting input. The output of the error amplifier circuit 11 is connected to the gate of the output transistor M1. Further, the bias current of the error amplifier circuit 11 is normally supplied from the current source I1.

  In this example, the output transistor M1 is a PMOS transistor. The source of the output transistor M1 is connected to the power supply Vdd, and the drain is connected to the output terminal Vo.

  The output voltage fluctuation detection circuit 12 includes a comparator 21, a capacitor C1, and resistors R3 and R4.

  The capacitor C1 and the resistors R3 and R4 are connected in series, and are connected between the output terminal Vo and the ground potential (GND).

  Of both terminals of the resistor R3, the output terminal Vo side is connected to the non-inverting input of the comparator 21, and the ground potential (GND) side is connected to the inverting input. The output of the comparator 21 is connected to the gate of an NMOS transistor M2 of a bias current increasing circuit 13 described later.

  The bias current increasing circuit 13 includes an NMOS transistor M2 and a current source I2. The NMOS transistor M2 is on / off controlled by the output of the comparator 21. The current source I2 is a bias current source for the error amplifier circuit 11.

  The bias current value of the current source I2 is a current value far larger than the current value of the bias current source I1. When the NMOS transistor M2 is on, the current source I2 serves as a bias current source for the error amplifier circuit 11, and is added to the bias current source I1. When the NMOS transistor M2 is turned off, the current source I2 is disconnected from the error amplifier circuit 11, and the bias current source of the error amplifier circuit 11 is only I1.

  FIG. 2 is a timing chart showing the relationship between the output voltage Vo, the output of the comparator 21 (CMP1), and the bias current of the error amplifier circuit 11 in the first embodiment of the present invention.

Next, the circuit operation of the constant voltage circuit in the first embodiment will be described with reference to FIG.
When the power supply Vdd is applied or the operation of the constant voltage circuit is started by an enable signal (not shown), the output voltage Vo starts to rise from the ground potential toward the rated output voltage. Then, since a charging current flows through the capacitor C1, a voltage drop occurs at both ends of the resistor R3. At this time, the voltage across the resistor R3 has a higher potential on the output terminal Vo side than on the ground potential side. For this reason, the output of the comparator 21 becomes a high level as shown by the CMP1 output in FIG.

  When the output of the comparator 21 becomes high level, the NMOS transistor M2 of the bias current increasing circuit 13 is turned on, so that the bias current source I2 is connected to the error amplifying circuit 11. As a result, the bias current of the error amplifying circuit 11 greatly increases as the current source I1 + current source I2, so that the rise of the output voltage Vo can be made faster.

  When the output voltage Vo reaches the rated output voltage and stabilizes, the charging current to the capacitor C1 disappears, so the voltage drop of the resistor R3 becomes 0V. For this reason, the output of the comparator 21 becomes a low level.

  When the output of the comparator 21 becomes low level, the NMOS transistor M2 is turned off, so that the bias current source I2 is disconnected from the error amplifier circuit 11. As a result, the bias current of the error amplifier circuit 11 is only the current source I1, and the current consumption can be extremely reduced.

  Even if the output voltage Vo is the rated output voltage, if the power supply voltage Vdd rises or the load current decreases and the output voltage Vo rises, a charging current flows through the capacitor C1, and the error amplification circuit as described above. 11, the bias current from the current source I1 is added to the bias current from the current source I1, and the overall bias current greatly increases, so that the original rated output voltage can be quickly restored.

  In this constant voltage circuit, since the discharge current flows through the capacitor C1 while the output voltage Vo is decreasing, the output of the comparator 21 remains at a low level, so that the bias current of the error amplifier circuit 11 cannot be increased. .

FIG. 3 is a configuration diagram of a constant voltage circuit showing a second embodiment of the present invention.
The second embodiment of the present invention shown in FIG. 3 is different from the first embodiment shown in FIG. 1 in that the comparator 21 is replaced with the comparator 22 and the inverting input of the comparator 22 is connected to the output terminal Vo side of the resistor R3. The non-inverting input is connected to the ground potential (GND) side of the resistor R3.

  In the bias current increasing circuit 13, an NMOS transistor M3 is used instead of the NMOS transistor M2. The rest is the same as the first embodiment of FIG.

  FIG. 4 is a timing chart showing the relationship between the output voltage Vo, the output of the comparator 22 (CMP2), and the bias current of the error amplifier circuit 11 in the second embodiment.

  In this constant voltage circuit, the comparator 22 outputs a high level only while the output voltage Vo is decreasing, the NMOS transistor M3 is turned on, and the bias current of the error amplifier circuit 11 is used as the bias current of the current source I1. Since the bias current by the source I2 is added and the overall bias current is greatly increased, the original rated output voltage can be quickly restored.

  That is, the voltage drop of the resistor R3 due to the discharge current of the capacitor C1 generated when the power supply voltage Vdd decreases or the load current increases to decrease the output voltage Vo is detected. The current can be increased (I1 + I2) to quickly return to the original rated output voltage.

  In this circuit, while the output voltage Vo is increasing, the output of the comparator 22 remains at a low level, so the bias current of the error amplifier circuit 11 cannot be increased.

FIG. 5 is a configuration diagram of a constant voltage circuit according to a third embodiment of the present invention.
This embodiment is a combination of the configurations of the first embodiment and the second embodiment, and the error amplifying circuit 11 is in both cases while the output voltage Vo is rising and falling. The bias current is increased to enable high-speed response.

  The constant voltage circuit of FIG. 5 according to this embodiment is different from the constant voltage circuit (FIG. 1) of the first embodiment in that a comparator 22 is added, and the inverting input of the comparator 22 is on the output terminal Vo side of the resistor R3. The non-inverting input is connected to the ground potential side of the resistor R3, and the NMOS transistor M3 of the bias current increasing circuit 13 is additionally connected in parallel to the NMOS transistor M2.

  The output of the comparator 22 is connected to the gate of the NMOS transistor M3.

  FIG. 6 is a timing chart showing the relationship between the output voltage Vo, the outputs of the comparators 21 (CMP1) and 22 (CMP2), and the bias current of the error amplifier circuit 11 in the third embodiment.

  According to this embodiment, the output of the comparator 21 (CMP1) is at a high level while the output voltage Vo is increasing, the NMOS transistor M2 is turned on, and the output of the comparator 22 (CMP2) is at a high level while the output voltage Vo is decreasing. Since the NMOS transistor M3 is turned on, the bias current from the current source I2 is added to the bias current from the current source I1 as the bias current of the error amplifying circuit 11 while the output voltage Vo is fluctuating (during rising and falling). Since the overall bias current greatly increases (I1 + I2), it becomes possible to respond to fluctuations (increase and decrease) in the output voltage Vo at high speed.

  In the above description, the comparators 21 and 22 have been described as ordinary comparators. However, by giving a slightly positive offset voltage to the non-inverting inputs of these comparators, the output voltage is stabilized at the rated output voltage. When the voltage drop of the resistor R3 becomes 0V, the output of the comparator can be surely returned to the low level.

  Further, by providing a slight hysteresis voltage to the inputs of these comparators, the comparator does not respond to minute output voltage fluctuations, and a more stable operation is possible.

  Needless to say, the value of the offset voltage and the voltage width of the hysteresis are set to be smaller than the allowable voltage range of the output voltage Vo.

  In addition, although the voltage drop of the resistor R3 is input to the inputs of the comparators 21 and 22, this is not limited to R3, and the voltage drop of the resistor R4 may be input. The drop may be input, and the comparator 22 may input the voltage drop of the resistor R4. Of course, the combination of the resistor and the comparator may be reversed.

  As described above, in the present invention, the fluctuation of the output voltage Vo is the voltage drop of the resistor R3 or the resistor R4 via the capacitor C1, and the voltage is detected by the comparators 21 and 22, so that the output voltage Vo Since the bias current of the error amplifier circuit 11 can be increased in both the rising and falling periods, the response speed can be increased in both rising and falling directions.

  Further, since the capacitor C1 is connected in series with the resistors R3 and R4, current does not always flow through the resistor as in the conventional example, and power saving can be achieved.

  By incorporating the constant voltage circuit according to each of the embodiments described above into a portable electronic device that operates on a battery such as a mobile phone, a mobile computer, a digital camera, or a portable music device, both periods when the output voltage rises and falls Thus, an electronic device can be obtained that has a high response speed and can save power.

1 is a constant voltage circuit diagram showing a first embodiment of the present invention. It is a timing chart for demonstrating operation | movement of the 1st Example of this invention. It is a constant voltage circuit diagram which shows the 2nd Example of this invention. It is a timing chart for demonstrating operation | movement of the 2nd Example of this invention. It is a constant voltage circuit diagram which shows the 3rd Example of this invention. It is a timing chart for demonstrating operation | movement of the 3rd Example of this invention. It is a constant voltage circuit diagram for demonstrating a prior art.

Explanation of symbols

11: Error amplification circuit 12: Output voltage fluctuation detection circuit 13: Bias current increasing circuit 21, 22: Comparator I1, I2: Bias current source Vref: Reference voltage M1: Output transistor M2, M3: NMOS transistor C1: Capacitor R1 R4: Resistance

Claims (10)

An input transistor that is connected between an input terminal that applies an input voltage and an output terminal that outputs an output voltage, and a reference voltage and a voltage obtained by dividing the output voltage are input, and the difference between the voltages is amplified and output. A constant voltage circuit that generates an output voltage of a constant voltage by controlling the output transistor according to an output of the error amplification circuit,
An output voltage fluctuation detection circuit for detecting a change in the output voltage;
A bias current increasing circuit for increasing the bias current of the error amplifier circuit;
A constant voltage circuit, wherein the bias current increasing circuit is operated by the output of the output voltage fluctuation detecting circuit during the output voltage fluctuation to increase the bias current of the error amplifying circuit. The constant voltage circuit according to claim 1,
The constant voltage circuit, wherein the output voltage fluctuation detection circuit operates the bias current increasing circuit while the output voltage is rising. The constant voltage circuit according to claim 1,
The constant voltage circuit, wherein the output voltage fluctuation detection circuit operates the bias current increasing circuit while the output voltage is decreasing. The constant voltage circuit according to claim 1,
The constant voltage circuit, wherein the output voltage fluctuation detection circuit operates the bias current increasing circuit while the output voltage is rising and falling. In the constant voltage circuit according to any one of claims 1 to 4,
The constant voltage circuit, wherein the output voltage fluctuation detection circuit detects an AC component of the output voltage. The constant voltage circuit according to claim 5,
The output voltage fluctuation detection circuit includes a capacitor and one or more resistors connected in series between the output voltage and a ground potential,
Comparing with the voltage across the resistor as input,
A constant voltage circuit, wherein the bias current increasing circuit is operated by an output of the comparator. The constant voltage circuit according to claim 6,
A first comparator that activates the bias current increase circuit while the output voltage is rising;
A constant voltage circuit comprising: a second comparator that operates the bias current increasing circuit while the output voltage is decreasing. In the constant voltage circuit according to claim 6 or 7,
A constant voltage circuit having an offset voltage at an input of the comparator. The constant voltage circuit according to any one of claims 6 to 8,
A constant voltage circuit characterized in that a hysteresis voltage is given to an input of the comparator.   An electronic apparatus comprising the constant voltage circuit according to claim 1.

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