JP2010226028A - Device for driving of inductive load - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent abnormal conditions from being erroneously detected when at least an instruction DUTY is 0%, without spoiling any abnormal condition detection performance by a microcomputer, in an inductive load driving device which controls an energizing to an inductive load by a current feedback circuit with a hardware and detects the abnormal conditions of a drive system based on a drive signal to a switching element for controlling the energizing. <P>SOLUTION: An edge detection circuit 26 detects an edge change of an upstream side driving instruction SDH output from a microcomputer 4. Based on the detection results, a counter 27 clocks a duration after the upstream side driving instruction SDH turns to an H level. If the duration exceeds a predetermined time threshold, a detection signal of an L level showing that the instruction DUTY is 0% is output to an AND gate 22. Thereby, a drive signal from a driving circuit 8 is fixed to the H level, and an upstream side MOS 10 is certainly turned off. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an inductive load driving device that feedback-controls an energization current to an inductive load such as an electromagnetic solenoid.

  Conventionally, for example, in a vehicle, in order to control the common rail pressure of a diesel engine, the amount of auxiliary air to the intake system of the engine, and the like, a linear solenoid type electromagnetic whose valve opening amount changes in accordance with a current supplied to a coil. A valve is used.

  In an apparatus for driving such an electromagnetic valve, the physical quantity such as the common rail pressure and the auxiliary intake air amount is adjusted by controlling the current flowing through the coil (linear solenoid) of the electromagnetic valve. As a control method, generally, the current actually flowing through the linear solenoid (hereinafter also referred to as “actual current”) is detected, and the linear solenoid is made to eliminate the difference between the actual current and the target current to be passed through the linear solenoid. Current feedback control is performed such that the power supply to the power supply is interrupted.

As an inductive load driving device that performs current feedback control of an inductive load such as a linear solenoid, a pulse signal output at a duty ratio corresponding to a target current from a microcomputer, a detected value of a current actually flowing through the inductive load, The charging and discharging of the integrating circuit consisting of a resistor and a capacitor based on the above, the polarity of the capacitor of the integrating circuit is changed in the same cycle as the above pulse signal, and the polarity change is used to apply the inductive load energization path. A configuration in which the energization current to the inductive load is feedback-controlled to the target current indicated by the duty ratio of the pulse signal by turning on and off the switching element provided in the circuit and intermittently energizing the inductive load. Are known (for example, see Patent Document 1).
Further, in this type of inductive load driving device, disconnection of the current path of the inductive load, a short circuit of the terminal connected to the inductive load to the load driving power supply voltage or the ground potential, and a rare short of the inductive load itself ( That is, it is necessary to detect a drive system abnormality such as a short circuit of the inductive load) and perform fail-safe such as protecting the switching element and the inductive load itself.

  Therefore, as an inductive load drive device configured to perform current feedback control as described above, the microcomputer further captures a drive signal for turning on / off the switching element, and the microcomputer performs the operation based on the captured drive signal. One having an abnormality detection function for detecting an abnormality in a drive system is known.

  FIG. 5 shows a specific configuration example. This inductive load driving apparatus 100 mainly includes a switching element (in this example, a P-channel MOSFET, hereinafter referred to as “P-channel MOSFET”) that intermittently passes a current flowing through the linear solenoid Lo that constitutes the electromagnetic valve 2. "Upstream side MOS".) 10 and a switching element (in this example) that is always turned on during the energization control of the linear solenoid Lo, but is turned off when the above-described drive system abnormality occurs and is fail-safe. N channel MOSFET (hereinafter abbreviated as “downstream MOS”) 20, current detection circuit 3 for detecting the current (actual current) flowing through the linear solenoid Lo, and driving the upstream MOS 10 (and thus driving the linear solenoid Lo) This is a pulse signal to indicate, and the duty corresponding to the target value (target current) of the current that should flow through the linear solenoid Lo. The upstream drive command SDH (see FIG. 6) having the same ratio is output, the presence / absence of an abnormality in the drive system is determined based on the monitor signal SM input from the drive circuit 8 to be described later, and the determination result is determined. The microcomputer 4 that outputs a downstream drive command SDL for turning on / off the downstream MOS 20 and the operation of the microcomputer 4 are monitored, and when the abnormality of the microcomputer 4 is detected, the upstream MOS 10 is forcibly turned off. A monitoring IC 5 that outputs an abnormal stop signal SE, a receiving circuit 6 that receives an upstream drive command SDH from the microcomputer 4, a resistor R1 and a capacitor C1 are connected in series, and are detected by the current detection circuit 3. Charge / discharge based on the actual current and the upstream drive command SDH received by the receiving circuit 6, and the deviation integral whose time constant is larger than the cycle of the upstream drive command SDH A comparator CMP1 that outputs a comparison signal according to the polarity of the charging voltage of the capacitor C1 that changes in the same cycle as the path 7 and the upstream drive command SDH, and the upstream side MOS 10 according to the comparison signal from the comparator CMP1 A drive circuit 8 for outputting a drive signal for turning on / off the MOS 10, and a current limiter circuit 9 for forcibly turning off the upstream MOS 10 when the actual current of the linear solenoid Lo becomes an overcurrent state equal to or greater than a predetermined current value; A radio noise reduction circuit 11 for reducing noise (radio noise) generated when the upstream side MOS 10 is turned on and off, and the upstream side MOS 10 are forcibly detected when an abnormality of the microcomputer 4 is detected by the monitoring IC 5. And an abnormal time forced stop circuit 12 for turning it off.

  In the configuration of FIG. 5, the source of the upstream side MOS 10 is connected to a battery voltage + B (for example, 12 V), which is a load driving power supply voltage, via an overcurrent detection resistor R18 that forms part of the current limiter circuit 9. The gate is connected to the drive circuit 8 and the drain is connected to one end (PCV +) of the linear solenoid Lo. Therefore, the upstream MOS 10 is turned on when the drive signal input from the drive circuit 8 to the gate of the upstream MOS 10 is at the L (Low) level (details will be described later), and a current is supplied to the linear solenoid Lo so that the above drive is performed. The signal is turned off when the signal is at the H (High) level (battery voltage + B), and the current supply to the linear solenoid Lo is cut off. The current flowing through the linear solenoid Lo is intermittently turned on / off by the upstream side MOS 10. .

  The current limiter circuit 9 includes the resistor R18, a PNP transistor T3 having an emitter connected to the battery voltage + B and a collector connected to the gate of the upstream MOS 10, and the base of the transistor T3 and the upstream MOS 10 The resistor R19 is connected between the source and the resistor R20 connected between the base of the transistor T3 and the battery voltage + B.

  In the current limiter circuit 9, when the current flowing through the upstream MOS 10 becomes a value that is regarded as an overcurrent, and the voltage drop at the resistor R 18 exceeds a predetermined value, the transistor T 3 is turned on, and the upstream MOS 10 is connected to the gate. By applying the battery voltage + B, the upstream MOS 10 is turned off. When the current flowing through the upstream MOS 10 decreases, the transistor T3 is turned off, and when the current flowing through the upstream MOS 10 becomes excessive again, the transistor T3 is turned on again. Therefore, for example, even if the drain side of the upstream MOS 10 is short-circuited to the ground potential and a current exceeding the breakdown tolerance flows in the upstream MOS 10, as long as the upstream MOS 10 is normal, the upstream MOS 10 The flowing current is limited, and the upstream MOS 10 can be protected.

  On the other hand, the downstream side MOS 20 has a source connected to a current detection resistor R2 forming part of the current detection circuit 3, a gate connected to the collector of an NPN transistor T4 via a resistor R27, and a drain connected to a linear solenoid. It is connected to the other end of Lo (PCV-). The base of the transistor T4 is connected to the microcomputer 4 via a resistor R24, and a resistor R25 is connected between the base and the emitter.

  The base of the transistor T4 is configured to be supplied with the downstream drive command SDL from the microcomputer 4 via the resistor R24. During normal control in which energization of the linear solenoid Lo is performed, the downstream drive command SDL becomes L level, and the transistor T4 is turned off. Therefore, a control voltage Vcc (for example, 5 V), which is a control power supply voltage, is supplied to the gate of the downstream MOS 20 via the resistors R26 and R27, and the downstream MOS 20 is turned on. Therefore, in this case, the energization current to the linear solenoid Lo is interrupted depending on whether the upstream MOS 10 is turned on or off.

  On the other hand, when the downstream drive command SDL from the microcomputer 4 becomes H level, the transistor T4 is turned on and the gate voltage of the downstream MOS 20 becomes the ground potential, so that the downstream MOS 20 is turned off. Become. Therefore, in this case, the energization path between the other end (PCV−) of the linear solenoid Lo and the resistor R2 is forcibly interrupted.

  The current detection circuit 3 includes a current detection resistor R2 installed as a part of the energization path between the source of the downstream side MOS 20 and the ground potential in the energization path to the linear solenoid Lo, and the grounding of the resistor R2. A resistor R5 having one end connected to an end opposite to the potential side (that is, the source of the downstream MOS 20), a resistor R4 connected between the other end of the resistor R5 and the ground potential, and a resistor R5 An operational amplifier OP1 having a non-inverting input terminal (+ terminal) connected to a connection point between R4, a resistor R3 connected between the inverting input terminal (− terminal) of the operational amplifier OP1 and the ground potential, and the inversion of the operational amplifier OP1. A resistor R6 connected between the input terminal and the output terminal, a resistor R7 connected between the output terminal of the operational amplifier OP1 and the ground potential, and one end connected to the output terminal of the operational amplifier OP1. Is, the other end and a connected resistor R8 Metropolitan to (end portion opposite to the resistor R1) one end of the capacitor C1 constituting the deviation integrated circuit 7.

  In the current detection circuit 3, the same current as the current flowing through the linear solenoid Lo flows through the current detection resistor R2, and a voltage Vi proportional to the current value is supplied from the output terminal of the operational amplifier OP1 through the resistor R8. It is output to one end of the capacitor C1 of the deviation integrating circuit 7.

  On the other hand, the receiving circuit 6 includes a PNP transistor T1 whose emitter is connected to the control voltage Vcc, a resistor R9 connected between the emitter and base of the transistor T1, and an output of the upstream drive command SDH in the microcomputer 4. The resistor R10 is connected between the terminal (output port) and the base of the transistor T1, and two resistors R11 and R12 connected in series between the collector of the transistor T1 and the ground potential. The connection point between the resistors R11 and R12 is connected to one end of the resistor R1 that constitutes the deviation integrating circuit 7 (the end opposite to the capacitor C1).

  In this receiving circuit 6, the transistor T1 is turned on / off in response to the upstream drive command SDH from the microcomputer 4. That is, the transistor T1 is turned on when the upstream drive command SDH is L level (ground potential), and is turned off when the upstream drive command SDH is H level (control voltage Vcc). When the transistor T1 is turned on, the voltage VD at the connection point between the resistors R11 and R12 becomes a value obtained by dividing the control voltage Vcc by the resistors R11 and R12. When the transistor T1 is turned off, the voltage VD is 0V. Become. Therefore, the voltage VD at the connection point between the resistors R11 and R12 becomes a pulse signal having a waveform obtained by inverting the upstream drive command SDH from the microcomputer 4, and this voltage VD is one end of the resistor R1 of the deviation integrating circuit 7. To be applied.

  The receiving circuit 6 is connected to an abnormal time forced stop circuit 12. Specifically, a configuration including a PNP transistor T6 having an emitter connected to the control voltage Vcc, a collector connected to the base of the transistor T1 of the receiving circuit 6, and a base connected to the monitoring IC 5 via the resistor R16. It has become. A resistor R17 is connected between the base and emitter of the transistor T6.

  When the microcomputer 4 is normal, the abnormal stop signal SE from the monitoring IC 5 to the abnormal forced stop circuit 12 is at the H level, so that the transistor T6 of the abnormal forced stop circuit 12 is turned off. Therefore, the transistor T1 of the receiving circuit 6 is turned on / off in response to the upstream drive command SDH from the microcomputer 4. On the other hand, when the microcomputer 4 is abnormal, the abnormal stop signal SE from the monitoring IC 5 becomes L level, and the transistor T6 of the abnormal forced stop circuit 12 is turned on. Therefore, the transistor T1 of the receiving circuit 6 is forcibly turned off regardless of the state of the upstream drive command SDH from the microcomputer 4, and the voltage VD applied from the receiving circuit 6 to the deviation integrating circuit 7 is 0 V (ground potential). As a result, the upstream side MOS 10 is turned off.

  The comparator CMP1 has a non-inverting input terminal (+ terminal) connected to the other end of the capacitor C1 of the deviation integrating circuit 7 (a connection point between the resistor R1 and the capacitor C1) and an inverting input terminal (− terminal). By connecting one end of the capacitor C1, a comparison signal corresponding to the charging polarity of the capacitor C1 is output.

  That is, the voltage on the resistor R1 side of the capacitor C1 in the deviation integrating circuit 7 (that is, the voltage on the non-inverting input terminal side of the comparator CMP1) is the voltage on the current detection circuit 3 side of the capacitor C1 (that is, the inverting input terminal side of the comparator CMP1). The comparison signal, which is the output of the comparator CMP1, is at the H level. Conversely, if the voltage on the resistor R1 side of the capacitor C1 is equal to or lower than the voltage on the current detection circuit 3 side of the capacitor C1, the comparison signal from the comparator CMP1 is at L level. The comparison signal from the comparator CMP1 is input to the drive circuit 8.

  The drive circuit 8 includes a pull-up resistor R13 connected between the output terminal of the comparator CMP1 and the control voltage Vcc, an NPN type in which the base is connected to the output terminal of the comparator CMP1, and the emitter is connected to the ground potential. Transistor T2, a resistor R14 connected between the collector of the transistor T2 and the battery voltage + B, and a collector voltage of the transistor T2 connected between the collector of the transistor T2 and the gate of the upstream MOS 10 Is connected to the gate of the upstream side MOS 10 as a drive signal and a resistor R15.

  In the drive circuit 8, when the comparison signal from the comparator CMP1 is at the H level, the transistor T2 is turned on, and the drive signal to the upstream side MOS 10 becomes an L level signal for turning on the upstream side MOS 10. Conversely, when the comparison signal from the comparator CMP1 becomes L level, the transistor T2 is turned off, and the drive signal to the upstream MOS 10 becomes an H level signal (battery voltage + B) that turns off the upstream MOS 10.

  Further, in the radio noise reduction circuit 11, the control voltage Vcc is applied to the base via the resistor R22, the collector is connected to the gate of the upstream side MOS1, and the drive circuit 8 is connected to the collector of the transistor T2 via the resistor R15. The transistor T5 has an emitter connected to the battery voltage + B via a resistor R21. A resistor R23 is connected between the base and emitter of the transistor T5.

  With this configuration, the transistor T5 of the radio noise reduction circuit 11 is always on as long as both the battery voltage + B and the control voltage Vcc are applied. Therefore, when the transistor T2 of the drive circuit 8 is turned on, the voltage of the L level drive signal input to the gate of the upstream MOS 10 is almost the same as the collector of the transistor T2 if the radio noise reduction circuit 11 is not provided. Although it is 0 V (ground potential), since the radio noise reduction circuit 11 is provided here, not the ground potential but the battery voltage + B is divided by the resistor R15 and the resistor R21 of the radio noise reduction circuit 11. Value (for example, 7V).

  That is, the radio noise reduction circuit 11 keeps the gate voltage when the upstream side MOS 10 is turned on to a predetermined value (7 V in this example) without dropping from the off-time voltage (12 V in this example) to 0 V. The difference in gate voltage between when the upstream MOS 10 is on and when it is off is reduced. As a result, the ON / OFF change speed of the upstream MOS 10 is slowed down, and the radio noise generated when the ON / OFF changes is reduced. In the present driving device 100, the radio noise reduction circuit 11 is provided as a countermeasure against radio noise, and a capacitor C2 is connected between the gate and drain of the upstream MOS 10.

  The drain of the upstream MOS 10 is connected to one end (PCV +) of the linear solenoid Lo. Between the drain of the upstream MOS 10 and the ground potential, the anode is connected to the ground potential side, and the linear solenoid Lo is connected. A diode D1 for absorbing the generated flyback energy is connected.

  In such an inductive load driving apparatus 100, the upstream side drive command SDH having a duty ratio corresponding to the target current of the linear solenoid Lo from the microcomputer 4 is received by the receiving circuit 6, and the deviation integrating circuit 7 is The pulse signal from the receiving circuit 6 (specifically, the voltage VD at the connection point between the resistors R11 and R12) and the detected current detected by the current detecting circuit 3 (specifically, the output of the operational amplifier OP1) Based on the voltage Vi), a charge / discharge operation is performed. The polarity of the charging voltage of the capacitor C1 of the deviation integrating circuit 7 is inverted at the same cycle as the upstream drive command SDH, and the duty ratio becomes a value corresponding to the deviation between the target current and the detected current. A comparison signal is output from the comparator CMP1 in accordance with the polarity of the charging voltage of the capacitor C1, and the drive circuit 8 controls on / off of the upstream MOS 10 in accordance with the comparison signal. As a result, the energization of the linear solenoid Lo is interrupted, and the current flowing by the interruption is controlled to a target value corresponding to the duty ratio of the upstream drive command SDH.

  More specifically, the output voltage Vi of the operational amplifier OP1 indicating the actual current value flowing through the linear solenoid Lo (hereinafter, also referred to as “current detection value Vi”) is the voltage VD indicating the target current value that should flow through the linear solenoid Lo. If smaller than (hereinafter also referred to as “target value VD”), the polarity of the charging voltage of the capacitor C1 is equal to the non-inverting input terminal side of the comparator CMP1 after a delay time due to the inductance of the linear solenoid Lo and the time constant of the deviation integrating circuit 7. The polarity is larger than that of the inverting input terminal. As a result, the comparison signal, which is the output of the comparator CMP1, becomes H level, the transistor T2 and the upstream MOS 10 are turned on, the current flowing through the linear solenoid Lo increases, and the current detection value Vi also increases.

  If the current detection value Vi increases and becomes equal to or greater than the target value VD, the charge voltage polarity of the capacitor C1 is not delayed by the comparator CMP1 after a delay time due to the inductance of the linear solenoid Lo and the time constant of the deviation integration circuit 7. The inverting input terminal side has a smaller (or the same) polarity than the inverting input terminal side. As a result, the comparison signal from the comparator CMP1 becomes L level, the transistor T2 and the upstream MOS 10 are turned off, the current flowing through the linear solenoid Lo is reduced, and the current detection value Vi is also reduced.

  Therefore, as shown on the left side of time t1 in FIG. 6, the current detection value Vi (output of the operational amplifier OP1) is set to the target value VD with a predetermined delay time with respect to the upstream drive command SDH from the microcomputer 4. It will pulsate to follow. Therefore, the comparison signal, which is an output from the comparator CMP1, has a duty ratio such that the current flowing through the linear solenoid Lo becomes a target current corresponding to the duty ratio of the upstream drive command SDH from the microcomputer 4, and from the microcomputer 4 This is a pulse signal having the same period as the upstream drive command SDH and a phase delayed by the delay time with respect to the upstream drive command SDH. Note that “PCV +” in the third row in FIG. 6 indicates the voltage at one end (PCV +) of the linear solenoid Lo (that is, the drain voltage of the upstream MOS 10).

  Then, by repeating the above operation, the energization current to the linear solenoid Lo is feedback-controlled to the target current corresponding to the duty ratio of the upstream drive command SDH from the microcomputer 4.

  In other words, in the inductive load driving apparatus 100 of FIG. 5, the current feedback control by the microcomputer 4 is not performed, but the current feedback circuit by hardware including the current detection circuit 3, the deviation integration circuit 7, and the comparator CMP1 (FIG. 5). 5, a portion surrounded by a two-dot chain line) is formed. By this current feedback circuit, the energization current to the linear solenoid Lo is feedback controlled in a wide range from a duty ratio of 0%. In addition, since the charging / discharging time constant of the deviation integrating circuit 7 is set to be larger than the cycle of the upstream drive command SDH, the charging voltage of the deviation integrating circuit 7 is not saturated and the battery as the load driving power supply voltage is obtained. Even if the voltage + B fluctuates, highly accurate current feedback control according to the duty ratio of the upstream drive command SDH is performed.

  Furthermore, the inductive load driving apparatus 100 of FIG. 5 has an abnormality detection function by the microcomputer 4 as described above. Specifically, the drive signal output from the drive circuit 8 is applied to the gate of the upstream MOS 10 and also input to the microcomputer 4 as the monitor signal SM. The microcomputer 4 detects an abnormality in the drive system based on whether or not the monitor signal SM (drive signal) input from the drive circuit 8 corresponds to the upstream drive command SDH output by itself. To do.

  Strictly speaking, the monitor signal input to the microcomputer 4 is not the drive signal itself input from the drive circuit 8 to the gate of the upstream side MOS 10, but the collector voltage of the transistor T2. However, the voltage at the collector of the transistor T2 is a drive signal that is the source of the drive signal input to the gate of the upstream MOS 10, and the change in the H level / L level of the source drive signal remains as it is. This is a change in the H level / L level of the drive signal output to the upstream side MOS 10 via R15. Therefore, taking in the collector voltage of the transistor T2 as the monitor signal SM and detecting a drive system abnormality is equivalent to taking in the drive signal input to the gate of the upstream MOS 10 and detecting the drive system abnormality. .

  In the inductive load driving apparatus 100, for example, an abnormality in which the battery voltage + B is directly applied to one end (PCV +) on the upstream side (PCV +) or the other end (PCV−) on the downstream side of the energization path in the linear solenoid Lo ( When a power supply short circuit occurs), a current always flows downstream from the position where the power supply short circuit occurs regardless of the ON / OFF state of the upstream MOS 10.

  Then, the current detection value Vi from the current detection circuit 3 is always a value corresponding to the current that is constantly flowing, and this value is input to the inverting input terminal of the comparator CMP1. As a result, even if the microcomputer 4 outputs the upstream drive command SDH having a predetermined duty ratio, the comparison signal from the comparator CMP1 is kept at a constant L level and is input to the drive signal from the drive circuit 8, that is, the microcomputer 4. The monitored signal SM always becomes H level.

  Therefore, the microcomputer 4 detects an abnormality in the drive system (in this case, a power supply short-circuit) because the upstream drive command SDH output by itself does not correspond to the monitor signal SM. Then, the microcomputer 4 performs processing such as turning off the downstream MOS 20 by supplying an H level downstream drive command SDL to the transistor T4 as fail safe.

  Further, for example, when an abnormality (hereinafter also referred to as “ground short”) occurs in which one end (PCV +) or the other end (PCV−) of the linear solenoid Lo is short-circuited to the ground potential, the upstream side MOS 10 is turned on / off. Regardless of the state, no current always flows through the downstream MOS 20 and the resistor R2 of the current detection circuit 3.

  Then, the current detection value Vi from the current detection circuit 3 is always 0 V, and this is input to the inverting input terminal of the comparator CMP1. As a result, even if the microcomputer 4 outputs the upstream drive command SDH with a predetermined duty ratio, the comparison signal from the comparator CMP1 becomes constant at the H level, and the drive signal from the drive circuit 8, that is, from the drive circuit 8 The monitor signal SM input to the microcomputer 4 is always at L level.

Therefore, the microcomputer 4 detects an abnormality in the drive system (in this case, a ground short) because the upstream drive command SDH output by itself does not correspond to the monitor signal SM.
Further, for example, if a short circuit of the linear solenoid Lo occurs, the inductance of the load disappears. Therefore, the upstream side MOS 10 has the upstream drive command SDH from the microcomputer 4 at the H level (upstream side) regardless of the deviation integrating circuit 7. When the upstream drive command SDH from the microcomputer 4 is at the L level (the level at which the upstream MOS 10 is turned on), it is extremely short corresponding to the delay of the current feedback system. It will be repeatedly turned on and off in cycles.

  This is because when the upstream side MOS 10 is turned on, the current detection value Vi from the current detection circuit 3 immediately increases, and the drive signal from the drive circuit 8 becomes H level, and when the upstream side MOS 10 is turned off, immediately. This is because the operation in which the current detection value Vi from the current detection circuit 3 decreases and the drive signal from the drive circuit 8 becomes L level is repeated.

  In this case, even if the microcomputer 4 outputs the upstream drive command SDH having a predetermined duty ratio, the drive signal from the drive circuit 8, that is, the monitor signal SM input to the microcomputer 4 is extremely short as described above. It becomes a signal (high frequency pulse) in which H level and L level are repeated in a cycle. Therefore, the microcomputer 4 detects an abnormality in the drive system (in this case, a rare short) because the upstream drive command SDH output by itself does not correspond to the monitor signal SM. Then, the microcomputer 4 performs processing such as turning off the downstream MOS 20 by supplying an H level downstream drive command SDL to the transistor T4 as fail safe.

  As described above, the conventional inductive load driving apparatus 100 shown in FIG. 5 is provided with the current feedback circuit by hardware, so that highly accurate current feedback control is realized without using the microcomputer 4. Further, the drive signal for driving (turning on / off) the upstream MOS 10 is taken into the microcomputer 4 as the monitor signal SM, whereby the abnormality detection function of the drive system by the microcomputer 4 based on the monitor signal SM is realized.

JP 2004-201410 A

  However, like the inductive load driving apparatus 100 shown in FIG. 5, a hardware current feedback circuit is provided, and a drive system abnormality is detected based on a monitor signal SM (drive signal) from the drive circuit 8. In this case, when the duty ratio of the upstream drive command SDH from the microcomputer 4 (hereinafter also referred to as “command DUTY”) is 0%, an abnormality in the drive system may be erroneously detected.

  That is, when the command DUTY from the microcomputer 4 is 0%, the current flowing through the linear solenoid Lo becomes 0 and no current flows through the current detection resistor R2 in the current detection circuit 3. Therefore, theoretically, the current detection value Vi, which is the output of the operational amplifier OP1 of the current detection circuit 3, becomes 0V, and 0V is input to the inverting input terminal of the comparator CMP1, and to the non-inverting input terminal of the comparator CMP1. The input voltage of the comparator CMP1 is also 0V, and the voltages of the input terminals of the comparator CMP1 are both 0V. Therefore, the output of the comparator CMP1 should be constant at the L level.

  However, the output of the operational amplifier OP1 of the current detection circuit 3 is in a state where no current flows through the linear solenoid Lo and no current flows through the resistor R2 of the current detection circuit 3 due to the offset voltage of the operational amplifier OP1 itself (that is, the operational amplifier OP1 Even when the input voltage to each input terminal is both 0V and the potential difference between them is 0), it is generally not 0V completely.

  The same applies to the comparator CMP1. In general, the output of the comparator CMP1 does not completely become 0V due to the offset voltage of the comparator CMP1 itself even if the input voltage of each input terminal is both 0V and the potential difference between them is 0. Is.

In addition, there are variations in the offset voltages of the operational amplifier OP1 and the comparator CMP1, and the values differ depending on individual components.
For this reason, when the command DUTY from the microcomputer 4 becomes 0% and no current flows to the linear solenoid Lo, the output of the comparator CMP1 should ideally be constant at the L level. As a result, the output of the comparator CMP1 may turn to the H level.

  When the output of the comparator CMP1 becomes H level in this way, the drive signal from the drive circuit 8 becomes L level, the upstream MOS 10 is turned on, and a current flows through the linear solenoid Lo. Then, the voltage of the inverting input terminal (− terminal) of the comparator CMP1 rises due to the current, whereby the output of the comparator CMP1 becomes L level again, the drive signal from the drive circuit 8 becomes H level again, and the upstream MOS 10 Turn off again. When the upstream MOS 10 is turned off, no current flows again through the linear solenoid Lo. For this reason, the voltage at the inverting input terminal of the comparator CMP1 drops again, and the output of the comparator CMP1 turns to H level due to the influence of the offset voltage.

  In this way, the comparator CMP1 outputs a pulse signal (high frequency pulse) whose level change is repeated at the response speed (very short period) of the current feedback circuit.

  Therefore, as illustrated in FIG. 6, when the command DUTY becomes 0% at time t <b> 1 and the current detection value Vi output from the operational amplifier OP <b> 1 of the current detection circuit 3 also becomes 0 V (or in the vicinity thereof), the offset voltage described above. As a result, the output from the comparator CMP1, which should be constant at the L level, becomes a high-frequency pulse, and the monitor signal SM input from the drive circuit 8 to the microcomputer 4 also becomes a high-frequency pulse.

  Thereby, at the diagnosis detection (abnormality detection) timing at time t2, the microcomputer 4 outputs the upstream drive command SDH with the command DUTY = 0%, but the monitor signal SM becomes a high frequency pulse. Therefore, the rare short of the linear solenoid Lo is erroneously detected.

  Note that this erroneous detection is not only caused when the command DUTY is 0%, but also when the command DUTY is close to 0% so that the ON time of the upstream side MOS is extremely short, the current does not flow through the linear solenoid Lo. There is a risk that it may occur due to the occurrence of a period.

  As a method for preventing such erroneous detection, for example, there is a method of masking the diagnostic detection function by the microcomputer 4 in a region where the command DUTY is close to 0% (including 0%). That is, the microcomputer 4 does not perform the diagnosis detection during the region where the command DUTY is close to 0%, which may be erroneously detected. According to this method, since the diagnosis detection itself is not performed, naturally, the above-described problem of erroneous detection can be solved.

  However, this method causes a problem that the diagnosis detection area is narrowed and the detection capability is lowered. In other words, if any abnormality in the drive system occurs while the command DUTY is close to 0%, the occurrence of the abnormality cannot be detected during that period.

  The present invention has been made in view of the above problems, and the switching element for energization control is turned on / off by current feedback control by hardware so that the energization current of the load becomes a value corresponding to the duty ratio commanded from the microcomputer. In addition, in an inductive load drive device configured to detect an abnormality by monitoring a signal for turning on and off the switching element, at least from the microcomputer without impairing the abnormality detection performance by the microcomputer. An object is to prevent an abnormality from being erroneously detected when the commanded duty ratio is 0%.

  In order to solve the above-mentioned problem, the invention according to claim 1 is provided on a current-carrying path from a power source to an inductive load, and switches a current flowing in the inductive load. Current detecting means for detecting a voltage and generating a detection voltage corresponding to the current, and a pulse-shaped drive command having a duty ratio corresponding to a target current to be supplied to the inductive load and instructing driving of the inductive load Microcomputer for output, drive voltage output means for outputting a drive voltage with a duty ratio corresponding to a drive command from the microcomputer, current detection means having a resistor and a capacitor, and the capacitor is input to one end of the capacitor The voltage is charged and discharged by the drive voltage from the drive voltage output means input to the other end of the capacitor via the resistor with reference to the detected voltage from The deviation integration circuit in which the polarity of the charging voltage of the capacitor changes in the same cycle as the drive command cycle is compared with the voltage at both ends of the capacitor constituting the deviation integration circuit. Comparing means for outputting a pulsed comparison signal according to the comparison result, and driving means for outputting a driving signal for turning on / off the switching element to the switching element according to the comparison signal from the comparing means, The microcomputer is an inductive load driving device configured to detect an abnormality in the energization path based on a driving signal from the driving means.

  That is, the current detection means detects the current flowing through the inductive load, and the drive voltage from the drive voltage output means is integrated by the deviation integration circuit based on the detection result (detection voltage) (the capacitor of the deviation integration circuit is charged / discharged) And use the hardware (current detection means, deviation integration circuit, comparison means) regardless of the microcomputer that the comparison means outputs a comparison signal according to the comparison result (charging polarity) of the voltage across the capacitor. The inductive load driving device is configured with a current feedback system, and has a function of detecting an abnormality in the energization path.

  Further, the inductive load driving device of the present invention (Claim 1) includes a zero duty detecting means for detecting when the duty ratio of the drive command from the microcomputer is 0%, and the zero duty detecting means. When it is detected that the duty ratio is 0%, the drive signal is forcibly fixed by fixing the drive signal to a negative level which is a level for turning off the switching element regardless of the comparison signal from the comparison means. Forcibly turning off.

  In the inductive load driving device configured as described above, when the duty ratio of the drive command is 0%, the detection voltage generated by the current detection circuit is ideally 0 V, and the deviation integration circuit capacitor Since both ends of 0 are at 0V, the comparison means compares 0V and 0V, and the comparison signal that is the output should have a constant negative level.

  However, depending on the specific internal configuration of the current detection means, the current detection signal may not be completely 0V even when no current is applied, and a voltage may be generated although it is very small. For this reason, a voltage is generated across the capacitor of the deviation integration circuit, and there is a possibility that the comparison signal from the comparison means turns to an active level that is a level for turning on the switching element. Further, even if the current detection signal is completely 0V and both ends of the capacitor are completely 0V, the comparison signal may become an active level depending on the specific internal configuration of the comparison means. .

  As described above, when the comparison signal shifts to the active level in spite of the non-energization, the drive signal also shifts to the active level and the microcomputer has an abnormality in the energization path. There is a risk of false detection.

  Therefore, in the inductive load drive device according to claim 1, when the duty ratio of the drive command is 0%, the drive signal is output regardless of what level of the comparison signal is output from the comparison means. The switching element is forcibly turned off by fixing the negative level.

  Therefore, according to the inductive load drive apparatus of the first aspect, when the duty ratio of the drive command is 0%, the drive signal is fixed at the negative level, so that the abnormality detection performance of the energization path by the microcomputer is impaired. Therefore, it is possible to prevent the microcomputer from erroneously detecting an abnormality in the energization path.

  Various methods are conceivable as to how the forcible off means fixes the drive signal to the negative level. For example, as described in claim 2, the duty ratio is set to 0% by the zero duty detection means. When this is detected, the level of the comparison signal input to the driving means can be fixed to a negative level.

  That is, even if an active level comparison signal is output from the comparison means when the duty ratio of the drive command is 0%, it is not input to the drive means as it is, but is forcibly fixed to a negative level (conversion etc.) Then, it is input to the driving means.

  Thus, by fixing the comparison signal to the drive means at a negative level when the duty ratio of the drive command is 0%, the drive signal from the drive means can be reliably fixed at the negative level. An erroneous detection of an abnormality can be reliably prevented.

  Various specific configurations of the zero duty detection means can be considered. For example, as described in claim 3, a level change detection means for detecting a level change of a drive command from a microcomputer, and this level change detection Whenever the timing at which the drive command level changes from the active level, which is the level to turn on the switching element, to the negative level is measured by the means, the duration of the negative level is counted, and the duration is determined in advance. And a detection signal output means for outputting a detection signal indicating that the duty ratio is 0% when the time threshold is exceeded.

  According to the inductive load driving device of the third aspect configured as described above, it is detected that the duty ratio becomes 0% based on the duration after the drive command changes to the negative level. Therefore, it can be reliably detected that the duty ratio is 0%.

  Note that the level change detection means by the level change detection means does not necessarily need to be the drive command itself output from the microcomputer, but is a signal corresponding to the drive command, that is, a signal that changes in level similarly to the drive command. Anything is fine. For this reason, for example, a change in the level of the drive signal output by the drive voltage output means may be detected, which is equivalent to detecting a change in the level of the drive command from the microcomputer.

  Next, the invention according to claim 4 is the inductive load driving device according to any one of claims 1 to 3, wherein the current detecting means is in series with the inductive load on the energizing path. And an amplifier circuit using an operational amplifier that generates a detection voltage by amplifying the voltage at both ends of the current detection resistor with a predetermined amplification factor.

  In the inductive load driving device according to claim 4 configured as described above, when the duty ratio of the drive command is 0%, the output from the operational amplifier (i.e., the influence of the offset voltage of the operational amplifier constituting the amplifier circuit) Even if the output from the amplifier circuit becomes a value larger than 0 V, the drive signal is fixed to a negative level regardless of the value. Therefore, it is possible to reliably prevent the microcomputer from erroneously detecting an abnormality in the energization path due to the offset voltage of the operational amplifier.

The invention according to claim 5 is the inductive load driving device according to any one of claims 1 to 4, wherein the comparison means is a comparator.
In the inductive load driving device according to claim 5 configured as described above, even when the duty ratio of the drive command is 0%, the input voltage of the comparator (that is, the voltage across the capacitor) is all 0V. However, the output from the comparator (comparison signal) may shift to the active level due to the influence of the offset voltage of the comparator, but the drive signal is fixed at the negative level regardless of the output from the comparator. Therefore, it is possible to reliably prevent the microcomputer from erroneously detecting an abnormality in the energization path due to the offset voltage of the comparator.

  Next, the invention according to claim 6 is provided on a current-carrying path from the power source to the inductive load, and detects a current flowing through the inductive load by detecting a switching element that interrupts the current flowing through the inductive load. A current detection means for generating a detection voltage corresponding to the current, a microcomputer having a duty ratio corresponding to the target current to be passed through the inductive load, and outputting a pulsed drive command for instructing driving of the inductive load; A drive voltage output means for outputting a drive voltage having a duty ratio corresponding to a drive command from the microcomputer, a resistor and a capacitor, and the capacitor receives a detection voltage from the current detection means input to one end of the capacitor. Based on the reference, charging / discharging is performed by the driving voltage from the driving voltage output means input to the other end of the capacitor via the resistor, and the time constant is longer than the cycle of the driving command. The deviation integration circuit in which the polarity of the charging voltage of the capacitor changes in the same cycle as the drive command cycle is compared with the voltage at both ends of the capacitor that constitutes the deviation integration circuit, and a pulse-like shape corresponding to the comparison result is obtained. Comparing means for outputting a comparison signal, and driving means for outputting a driving signal for turning on / off the switching element to the switching element in response to the comparison signal from the comparing means, and the microcomputer from the driving means An inductive load driving device configured to detect an abnormality in an energization path based on a driving signal.

  Furthermore, the inductive load driving device according to the present invention (Claim 6) has a voltage higher than 0V at one end of the capacitor constituting the deviation integrating circuit when the duty ratio of the drive command is 0% when the current is not energized. Voltage holding means is provided.

  That is, the voltage at one end of the capacitor during non-energization is intentionally set to a value higher than 0V. As a result, the voltage at the other end of the capacitor is 0 V when no power is supplied, so that the voltage at the one end is higher, and a comparison signal with a negative level is reliably output from the comparison means.

  Therefore, according to the inductive load driving device of the sixth aspect, since the drive signal at the time of non-energization is reliably fixed to the negative level, the duty ratio is in a region close to 0% (including 0%). However, it is possible to prevent the microcomputer from erroneously detecting the abnormality of the energization path without impairing the abnormality detection performance of the energization path by the microcomputer.

  Various specific configurations of the voltage holding means are conceivable. For example, as described in claim 7, a pull-up resistor having one end connected to one end of a capacitor and the other end of the pull-up resistor are connected. And a constant voltage power source for applying a voltage to one end of the capacitor via a resistor.

  According to the inductive load driving device of the seventh aspect configured as described above, the voltage at one end of the capacitor can be reduced even when the power is not supplied by connecting the constant voltage power source via the pull-up resistor. It can be maintained at a value higher than 0V.

  The invention according to claim 8 is the inductive load driving device according to claim 7, wherein the current detection means includes a current detection resistor connected in series with the inductive load on the energization path, a current An amplifier using an operational amplifier that generates a detection voltage by amplifying the voltage at both ends of the detection resistor at a predetermined amplification factor, and an output resistor connected to the output terminal of the operational amplifier. The voltage is input to one end of the capacitor via the output resistor.

  In the inductive load driving apparatus according to claim 8, configured as described above, the voltage of the constant voltage power source is divided by the pull-up resistor and the output resistor, and the divided value is input to one end of the capacitor. Become. For this reason, the voltage at one end of the capacitor can be held at the above-mentioned divided voltage value even when no power is supplied. In addition, by appropriately determining the resistance values of the pull-up resistor and the output resistor, the divided voltage value can be set to a desired value.

  Next, the invention according to claim 9 is the inductive load driving device according to claim 8, wherein the comparison means is a comparator, and one end of a capacitor is connected to the inverting input terminal of the comparator. The other end of the capacitor is connected to the non-inverting input terminal. The resistance value of the pull-up resistor is set to such a value that the divided value obtained by dividing the voltage of the constant voltage power supply by the pull-up resistor and the output resistor is larger than the offset voltage of the comparator.

  According to the inductive load driving device of the ninth aspect configured as described above, the voltage at one end of the capacitor can be maintained at a value larger than the offset voltage of the comparator even when no power is supplied. Therefore, the comparison signal output from the comparator can be reliably fixed at a negative level (here, low level).

  Next, the invention according to claim 10 is the inductive load driving device according to claim 6, wherein the current detecting means is inductive on the energization path downstream of the inductive load and the switching element. A current detection resistor connected in series with the load, and an amplifier circuit using an operational amplifier that generates a detection voltage by amplifying the voltage at both ends of the current detection resistor with a predetermined amplification factor, and holds the voltage The means includes a constant current power source that boosts the detection voltage from the current detection means by a value corresponding to the predetermined amount of current by flowing a predetermined amount of current through the current detection resistor.

  In other words, by separately providing a constant current power source for supplying a predetermined amount of current to the current detection resistor, the current from the constant current power source flows to the current detection resistor even when not energized. Outputs a detection voltage having a value corresponding to the current (predetermined amount of current).

  Therefore, according to the inductive load driving device of the tenth aspect, the voltage at one end of the capacitor is set to a value higher than 0V (here, a value corresponding to the predetermined amount of current) even when no power is supplied. Can be held. Therefore, the comparison signal output from the comparison unit can be reliably fixed at the negative level.

  The invention according to claim 11 is the inductive load driving device according to claim 10, wherein the comparison means is a comparator, and one end of a capacitor is connected to the inverting input terminal of the comparator. The other end of the capacitor is connected to the non-inverting input terminal, and the value of a predetermined amount of current that the constant current power supply passes through the current detection resistor is output from the current detection means when the current flows through the current detection resistor. The detection voltage is set to a value that is larger than the offset voltage of the comparator.

  According to the inductive load drive device of the eleventh aspect configured as described above, even when the duty ratio of the drive command is 0%, the voltage at one end of the capacitor is set to the offset voltage of the comparator. Therefore, the comparison signal output from the comparator can be reliably fixed at the negative level (low level).

It is a block diagram showing the inductive load drive device of 1st Embodiment. It is a time chart showing the operation example before and after the instruction | command DUTY becomes 0% in the inductive load drive device of 1st Embodiment. It is a block diagram showing the inductive load drive device of 2nd Embodiment. It is a block diagram showing the inductive load drive device of 3rd Embodiment. It is a block diagram showing the conventional inductive load drive device. It is a time chart showing the operation example before and after the instruction | command DUTY becomes 0% in the conventional inductive load drive device.

Preferred embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
FIG. 1 is a configuration diagram illustrating an inductive load driving device according to the present embodiment. In FIG. 1, the same components as those of the inductive load driving device 100 and the electromagnetic valve 2 of FIG. 5 described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 1, the inductive load driving device 1 of the present embodiment is the upstream side as a switching element for intermittently passing the current flowing through the linear solenoid Lo, just like the inductive load driving device 100 of FIG. 5 described above. MOS 10, downstream MOS 20, current detection circuit 3, microcomputer 4, monitoring IC 5. A reception circuit 6, a deviation integration circuit 7, a comparator CMP1, a drive circuit 8, a current limiter circuit 9, a radio noise reduction circuit 11, and an abnormal time forced stop circuit 12 are provided.

  The electromagnetic valve 2 is, for example, a linear solenoid type electromagnetic valve for controlling the common rail pressure of a diesel engine, and is generally called a PCV (pressure control valve). In this embodiment, the amount of fuel pumped to the common rail (and thus the common rail pressure) is controlled by controlling the current flowing to the linear solenoid Lo in the solenoid valve 2.

  With the configuration as described above, the inductive load driving device 1 according to the present embodiment also includes the hardware including the current detection circuit 3, the deviation integration circuit 7, and the comparator CMP1, as in the inductive load driving device 100 of FIG. A current feedback circuit is formed.

And compared with FIG. 5, the zero duty detection circuit 21 and the AND gate 22 are added to the inductive load drive device 1 of this embodiment.
The zero duty detection circuit 21 detects when the duty ratio of the upstream drive command SDH from the microcomputer 4 is 0% and outputs a detection signal to that effect. The edge detection circuit 26 and the counter 27 And.

  The edge detection circuit 26 is a circuit for detecting an edge change of the upstream drive command SDH. Specifically, the edge detection circuit 26 inputs the collector voltage of the transistor T1 of the reception circuit 6 and detects the level change of the collector voltage. Thus, the edge change of the upstream drive command SDH is detected.

  That is, as shown on the left side of time t1 in FIG. 2, when the upstream drive command SDH changes from the H level (negative level that turns off the upstream MOS 10) to the L level (active level that turns on the upstream MOS 10), The collector voltage of the transistor T1, which is an input to the edge detection circuit 26, changes from L level (negative level) to H level (active level). The edge detection circuit 26 detects the falling edge (the change timing to the active level) of the upstream drive command SDH by detecting the level change from the negative level to the active level, and sends an H level signal to the counter 27. Is output.

  When the upstream drive command SDH changes from the L level (active level) to the H level (negative level), the collector voltage of the transistor T1, which is an input to the edge detection circuit 26, changes from the H level (active level) to the L level ( Change to negative level). The edge detection circuit 26 detects the rising edge of the upstream drive command SDH (change timing to the negative level) by detecting the level change from the active level to the negative level, and outputs an L level signal to the counter 27. Output.

  The counter 27 has a known configuration for counting (clocking) based on a pulse from a reference clock (not shown). As shown in FIG. 2, the edge detection circuit 26 uses a rising edge ( When a negative level) is detected, counting is started. After the start of counting, when the edge detection circuit 26 detects the falling edge of the upstream drive command SDH (timing to change to the active level), the count value is reset and the upstream drive command SDH is set to the active level ( (L level), the count operation is stopped. When the edge detection circuit 26 detects the falling edge of the upstream drive command SDH again, the count is restarted from the initial value.

  Thus, whenever the upstream drive command SDH changes to the H level (negative level), the counter 27 measures the duration of the H level. The counter 27 normally outputs an H level detection signal to the AND gate 22, but sets a predetermined time threshold for the duration of the H level after the upstream drive command SDH changes to the H level. If exceeded (time t2 in FIG. 2), an L level detection signal is output to the AND gate 22.

  That is, while the command DUTY, which is the duty ratio of the upstream drive command SDH, is not 0%, the counter value of the counter 27 is reset every time the upstream drive command changes to the L level, and thus exceeds the time threshold. There is no. On the other hand, when the command DUTY becomes 0%, the upstream drive command SDH becomes constant at the H level, so the count of the counter 27 proceeds without being reset, and the counter value (H level duration) eventually becomes the time threshold value. Over. Therefore, whether or not the command DUTY has become 0% can be detected depending on whether or not the count value of the counter 27 exceeds the time threshold value. If it is detected that the command DUTY has become 0%, AND is performed. An L level detection signal is output to the gate.

  The AND gate 22 receives a comparison signal output from the comparator CMP1 at one input terminal, and a detection signal from the counter 27 at the other input terminal. The output terminal of the AND gate 22 is connected to the base of the transistor T2 in the drive circuit 8.

  With such a configuration, while the command DUTY from the microcomputer 4 is not 0%, that is, while the energization of the linear solenoid Lo is being performed, the detection signal input from the counter 27 to the AND gate 22 is constant at the H level. Therefore, the output from the AND gate 22 corresponds to the comparison signal from the comparator CMP1. That is, during this period, the comparison signal from the comparator CMP1 is substantially input to the base of the transistor T2 of the drive circuit 8 as it is. Therefore, during the energization period in which the command DUTY is not 0%, the energization to the linear solenoid Lo is feedback-controlled in exactly the same manner as the inductive load driving device 100 in FIG.

  On the other hand, when the command DUTY from the microcomputer 4 becomes 0% (time t1 in FIG. 2), the zero duty is detected by the zero duty detection circuit 21 (time t2 in FIG. 2). An L level detection signal is input to the AND gate 22 from the detection circuit 21 (specifically, from the counter 27). Thereby, the output of the AND gate 22 is fixed at the L level regardless of whether the comparison signal from the comparator CMP1 is at the H level or the L level.

  Here, when the command DUTY from the microcomputer 4 is 0% and the energization to the linear solenoid Lo is not performed, the voltage input to each input terminal of the comparator CMP1 is originally 0V. The output from CMP1 should be constant at the L level. However, as described above, due to the influence of the offset voltage of the operational amplifier OP1 of the current detection circuit 3, the current detection value Vi that is the output of the operational amplifier OP1 often does not completely become 0V even when no current is applied. Further, even if this current detection value Vi becomes completely 0V and all the voltages input to the respective input terminals of the comparator CMP1 become 0V, the offset from the comparator CMP1 is affected by the offset voltage of the comparator CMP1. The output may become H level.

  Therefore, as shown after time t1 in FIG. 2 (and after time t1 in FIG. 6 described above), a high-frequency pulse may be output from the comparator CMP1 while the command DUTY from the microcomputer 4 is 0%. . Therefore, if the state in which the high-frequency pulse is output continues as described above, an abnormality in the drive system is erroneously detected by the microcomputer 4 at the diagnosis detection timing at time t3 as in the case of time t2 in FIG. End up.

  On the other hand, in the inductive load driving device 1 of the present embodiment, when the command DUTY is detected to be 0% by providing the zero duty detection circuit 21 and the AND gate 22, the driving circuit 8 A constant L level signal is input from the AND gate 22 to the base of the transistor T2. As a result, the transistor T2 is forcibly turned off, the drive signal input to the gate of the upstream MOS 10 is also kept at the H level, and the upstream MOS 10 is forcibly turned off. As a result, as shown in FIG. 2, the monitor signal (drive signal) SM input from the drive circuit 8 to the microcomputer 4 also becomes constant at the H level.

  Further, when the detection signal from the counter 27 becomes L level at time t2 in FIG. 2 and the output from the AND gate 22 becomes constant at L level, the upstream MOS 10 is forcibly turned off and the linear solenoid Lo is turned off. Since no current flows, the current detection value Vi from the operational amplifier OP1 of the current detection circuit 3 is also 0 V (however, a minute voltage may be output due to the offset voltage).

  At time t3 when the diagnosis is detected by the microcomputer 4, the monitor signal SM is not a high-frequency pulse as at the time t2 that is the diagnosis detection timing of FIG. Therefore, the microcomputer 4 does not erroneously detect a drive system abnormality (rare short) as shown in FIG.

  The time for detecting that the command DUTY becomes 0% in the zero duty detection circuit 21, that is, the time threshold value in the counter 27 can be determined as appropriate, but is at least the period of the upstream drive command SDH (for example, It is necessary to set it to 2 or more times the period. In addition, since it is necessary to detect that the command DUTY has become 0% before the diagnosis detection timing arrives, the time is sufficient for the diagnosis detection timing by the microcomputer 4. It is desirable.

  Further, when an abnormality of the microcomputer 4 is detected by the monitoring IC 5, the abnormal time forced stop circuit 12 forcibly turns off the transistor T1 of the receiving circuit 6 to forcibly turn off the upstream MOS 10, but FIG. In the conventional inductive load driving device 100 shown in FIG. 1, when the command DUTY from the microcomputer 4 becomes 0%, the abnormal-time forced stop circuit 12 performs the above operation to forcibly turn off the upstream MOS 10, Due to the influence of the offset voltage of the comparator CMP1 and the operational amplifier OP1 described above, the upstream MOS 10 may not be reliably turned off, and the monitoring result by the monitoring IC may not be sufficiently reflected.

  However, in the inductive load driving device 1 of the present embodiment, the edge detection circuit 26 does not directly take in the upstream drive command SDH when detecting the edge change of the upstream drive command SDH from the microcomputer 4. The collector voltage of the transistor T1 in the receiving circuit 6 is taken in.

  Therefore, during the normal operation of the microcomputer 4, the change in the upstream drive command SDH from the microcomputer 4 appears as it is as the change in the collector voltage of the transistor T1 (however, the logic is opposite), and the edge detection circuit 26 The edge change of the upstream drive command SDH can be detected based on this collector voltage.

  On the other hand, when the abnormality of the microcomputer 4 is detected by the monitoring IC 5, the transistor T1 of the receiving circuit 6 is forcibly turned off by the abnormality forced stop circuit 12. Therefore, regardless of the state of the upstream drive command SDH from the microcomputer 4, the collector voltage of the transistor T1 input to the edge detection circuit 26 is constant at the L level.

  Therefore, an L level detection signal is eventually output from the counter 27, the output from the AND gate 22 becomes constant at L level, the drive signal from the drive circuit 8 becomes constant at H level, and the upstream side MOS 10 is forced. Turned off.

  In other words, the zero-duty detection circuit 21 captures the collector voltage of the transistor T1 in the reception circuit 6 to detect when the command DUTY becomes 0% while the microcomputer 4 is normal, and A basic operation of outputting an L level detection signal for forcibly turning off the MOS 10 to the AND gate 22 is performed. If an abnormality of the microcomputer 4 is detected by the monitoring IC 5, the transistor T1 is forcibly turned off, and the upstream MOS 10 is forcibly forced even if the command DUTY from the microcomputer 4 is not 0%. An extended operation of outputting an L level detection signal for turning off to the AND gate 22 is performed.

  In the inductive load driving device 1 of the present embodiment described above, the output of the comparator CMP1 may turn to H level even when the command DUTY becomes 0% due to the influence of the offset voltage of the comparator CMP1 and the operational amplifier OP1. Even if it occurs, since the output from the AND gate 22 is fixed at the L level while the command DUTY is 0%, the drive signal from the drive circuit 8 is fixed at the H level and the upstream side MOS 10 is forcibly turned off. Is done.

  Therefore, when the command duty is 0%, the diagnostic detection function of the microcomputer 4 is masked when the command duty is 0%. The upstream MOS 10 can be reliably fixed off, and it is possible to reliably prevent the microcomputer 4 from erroneously detecting an abnormality in the drive system.

  Also, when an abnormality of the microcomputer 4 is detected by the monitoring IC 5, the transistor T 1 of the receiving circuit 6 is forcibly turned off by the abnormality forced stop circuit 12, whereby the operation of the zero duty detection circuit 21 causes the AND gate 22 to operate. Is fixed at the L level. Therefore, the upstream MOS 10 can be reliably turned off even when an abnormality of the microcomputer 4 is detected.

  Further, in the inductive load driving devices 30 and 40 (see FIGS. 3 and 4) of the second and third embodiments described later, the microcomputer 4 causes an abnormality in the driving system due to the offset voltage of the comparator CMP1 and the operational amplifier OP1. In order to prevent erroneous detection, the voltage at the inverting input terminal of the comparator CMP1 when the command DUTY is 0% and not energized is held at a predetermined holding value higher than 0V. However, in such a method, there is a slight influence on the relationship between the command DUTY and the actual current (second embodiment), and it is necessary to add an offset (details will be described later) to the command DUTY ( The third embodiment) affects the controllability of the current feedback control, that is, the current characteristics of the linear solenoid Lo, although slightly.

  However, in the inductive load driving apparatus 1 of the first embodiment, the voltage at the inverting input terminal of the comparator CMP1 is not raised as in the second and third embodiments. Therefore, it is possible to prevent the microcomputer 4 from erroneously detecting an abnormality in the drive system when the command DUTY is 0% without affecting the current characteristics of the linear solenoid Lo.

  Here, the correspondence between the components of the present embodiment and the components of the present invention will be clarified. In the present embodiment, the current detection circuit 3 corresponds to the current detection means of the present invention, the resistor R2 corresponds to the current detection resistance of the present invention, the reception circuit 6 corresponds to the drive voltage output means of the present invention, and the drive circuit 8 corresponds to the drive means of the present invention, the zero duty detection circuit 21 corresponds to the zero duty detection means of the present invention, the edge detection circuit 26 corresponds to the level change detection means of the present invention, and the counter 27 corresponds to the present invention. The AND gate 22 corresponds to detection signal output means, the forced-off means of the present invention, and the upstream drive command SDH output from the microcomputer 4 corresponds to the drive command of the present invention. The “abnormality of the drive system” detected by the microcomputer 4 corresponds to the “abnormality of the energization path” of the present invention.

[Second Embodiment]
Next, an inductive load driving apparatus according to a second embodiment will be described with reference to FIG. FIG. 3 is a configuration diagram illustrating the inductive load driving device 30 of the present embodiment. In FIG. 3 as well, the same components as those of the inductive load driving device 100 and the electromagnetic valve 2 of FIG. 5 described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the inductive load driving apparatus 1 (FIG. 1) of the first embodiment described above, in order to prevent the microcomputer 4 from erroneously detecting an abnormality in the driving system due to the offset voltage of the comparator CMP1 and the operational amplifier OP1. Although the zero duty detection circuit 21 and the AND gate 22 are provided, in the inductive load driving device 30 of this embodiment, a predetermined value is separately added to one end of the capacitor C1 of the deviation integration circuit 7 (that is, the inverting input terminal of the comparator CMP1). By applying a voltage of (holding value), the voltage of the inverting input terminal of the comparator CMP1 becomes higher than 0V even when the command DUTY is 0% non-energized, thereby solving the above problem. I am trying.

  That is, in the inductive load driving device 30 of this embodiment, the control power supply (control voltage Vcc) is connected to one end of the capacitor C1 via the pull-up resistor R30 as compared with the inductive load driving device 100 of FIG. It is connected.

  As a result, the voltage input to the inverting input terminal of the comparator CMP1 is divided into the current detection value Vi output from the operational amplifier OP1, and the difference between the control voltage Vcc and the current detection value Vi is divided by the pull-up resistor R30 and the resistor R8. The value obtained by adding the partial pressure value. Therefore, when the command DUTY is 0% de-energized and the current detection value Vi from the operational amplifier OP1 is 0 V, the divided value obtained by dividing the control voltage Vcc by the pull-up resistor R30 and the resistor R8 is the holding value. , And input to the inverting input terminal of the comparator CMP1.

  That is, by applying a voltage to the inverting input terminal of the comparator CMP1 via the pull-up resistor R30, even when no current flows through the linear solenoid Lo, it appears as if the current is flowing from the comparator CMP1. To. In this way, when the command DUTY is 0%, the comparison signal from the comparator CMP1 is surely set to the L level, and the upstream MOS 10 is surely turned off.

  The resistance value of the pull-up resistor R30 is such that the divided voltage value (holding value) obtained by dividing the control voltage Vcc by the pull-up resistor R30 and the resistor R8 is greater than the offset voltage of the comparator CMP1 (specifically, the maximum tolerance). What is necessary is just to set to the value which becomes large.

  However, if the current detection value Vi output from the operational amplifier OP1 of the current detection circuit 3 and the voltage value actually input to the inverting input terminal of the comparator CMP1 are greatly shifted, the relationship between the command DUTY and the actual current is affected. This may affect the controllability of current feedback control. That is, the timing at which the upstream side MOS 10 is turned on is delayed and the timing at which it is turned off earlier than the inductive load driving device 100 in FIG. 5 by the amount that the voltage at the inverting input terminal of the comparator CMP1 is raised through the pull-up resistor R30. Become. For this reason, the command DUTY and the duty ratio at which the actual upstream side MOS 10 is turned on / off slightly deviate, which may affect the controllability.

  Therefore, in order to suppress the above influence as much as possible, it is desirable that the resistance value of the pull-up resistor R30 is set to be sufficiently larger than the resistance value of the resistor R8 connected to the output terminal of the operational amplifier OP1. .

  For example, when the control voltage Vcc is 5V and the resistance R8 is 1 kΩ, if a 100 kΩ pull-up resistor R30 is used, for example, 100 kΩ, the divided voltage value is about 50 mV, and the command DUTY is 0%. The voltage at the inverting input terminal of the comparator CMP1 can be increased by about 50 mV.

  According to the inductive load driving device 30 of the present embodiment configured as described above, the voltage at the inverting input terminal of the comparator CMP1 is raised via the pull-up resistor R30, so that the comparator when the command DUTY is 0% is not energized. The comparison signal from CMP1 can be reliably set to the L level.

  Therefore, the command DUTY is 0% without reducing the diagnosis detection function of the microcomputer 4 such as masking the diagnosis detection function of the microcomputer 4 when the command DUTY is close to 0% as in the prior art. The upstream side MOS 10 can be reliably turned off during the region close to, so that it is possible to reliably prevent the microcomputer 4 from erroneously detecting an abnormality in the drive system.

  Further, when the abnormality of the microcomputer 4 is detected by the monitoring IC 5 and the transistor T1 of the receiving circuit 6 is forcibly turned off, the voltage of the non-inverting input terminal of the comparator CMP1 becomes 0V. Is maintained at a value higher than 0 V, the comparison signal from the comparator CMP1 can be reliably set to L level, and the upstream MOS 10 can be reliably turned off.

  Further, by appropriately determining the resistance value of the pull-up resistor R30, the divided voltage value can be set to a more appropriate (desired) value in consideration of the influence on the controllability of the current feedback control.

In the present embodiment, the control power source that generates the control voltage Vcc corresponds to the constant voltage power source of the present invention, and the resistor R8 of the current detection circuit 3 corresponds to the output resistance of the present invention.
[Third Embodiment]
Next, an inductive load driving apparatus according to a third embodiment will be described with reference to FIG. FIG. 4 is a configuration diagram illustrating the inductive load driving device 40 of the present embodiment. In FIG. 4 as well, the same components as those of the inductive load driving device 100 and the electromagnetic valve 2 of FIG. 5 described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  Similarly to the inductive load driving device 30 of the second embodiment shown in FIG. 3, the inductive load driving device 40 of the present embodiment is also the inverting input terminal of the comparator CMP1 even when the command DUTY is 0% non-energized. When the command DUTY is close to 0%, the microcomputer 4 erroneously detects an abnormality in the drive system due to the offset voltage of the comparator CMP1 and the operational amplifier OP1. I try to prevent it.

  That is, the inductive load driving device 40 of the present embodiment is provided with a constant current circuit 41 that outputs a predetermined amount of current as compared with the inductive load driving device 100 of FIG. The current from the constant current circuit 41 is supplied to the current detection resistor R2 in the current detection circuit 3. Specifically, the current output terminal in the constant current circuit 41 is connected to the upstream side of the energization path in the resistor R2 (that is, the connection point with the resistor R5).

  With such a configuration, a predetermined amount of current is constantly supplied from the constant current circuit 41 to the resistor R2 of the current detection circuit 3. Therefore, the current detection value Vi output from the operational amplifier OP1 is a value obtained by boosting the value corresponding to the actual current flowing through the linear solenoid Lo by a value corresponding to a predetermined amount of current from the constant current circuit 41. It becomes.

  Thus, by superimposing the current from the constant current circuit 41 on the current detection resistor R2, the value of the current detection value Vi output from the operational amplifier OP1 is a value corresponding to the current that actually flows through the linear solenoid Lo. Thus, even when the command DUTY is not energized at 0%, the current detection value Vi (holding value) of a value larger than 0 V corresponding to the current from the constant current circuit 41 becomes a deviation integrating circuit. 7 is input to one end of the capacitor C1 and the inverting input terminal of the comparator CMP1.

  In other words, even when no current is flowing through the linear solenoid Lo, the current is always passed through the resistor R2, so that it appears as if the current is flowing as viewed from the comparator CMP1. In this way, when the command DUTY is 0%, the comparison signal from the comparator CMP1 is surely set to the L level, and the upstream MOS 10 is surely turned off.

  The value of a predetermined amount of current that the constant current circuit 41 supplies to the resistor R2 is that the current detection value Vi output from the operational amplifier OP1 when the current is supplied to the resistor R2 when the linear solenoid Lo is not energized is the offset of the comparator CMP1. It may be set to a value larger than the voltage (specifically, the maximum value of the tolerance). Therefore, in setting the current value, the offset voltage of the comparator CMP1, the amplification factor of the current detection circuit 3 including the operational amplifier OP1, and the offset voltage of the operational amplifier OP1 are taken into consideration. As a result, the command DUTY is 0%. It is desirable to set so that the comparison signal from the comparator CMP1 is always at a constant L level when power is not supplied.

  In the inductive load driving device 40 according to the present embodiment, since the current from the constant current circuit 41 always flows through the resistor R2 of the current detection circuit 3, the current detection value detected by the current detection circuit 3 is detected. Vi is always a value larger than the value corresponding to the current actually flowing through the linear solenoid Lo. That is, it is detected that a current larger than the current actually flowing through the linear solenoid Lo is always flowing.

  Therefore, it is preferable to offset the command DUTY from the microcomputer 4 with respect to the original duty ratio corresponding to the target current. That is, the upstream drive command SDH having a duty ratio slightly larger than the original duty ratio corresponding to the target current is output. By adding an offset to the command DUTY in this way, the influence of the current from the constant current circuit 41 on the controllability of the current feedback control can be suppressed, and the current flowing through the linear solenoid Lo can be controlled to the target current. it can.

  According to the inductive load driving device 40 of the present embodiment configured as described above, the voltage at the inverting input terminal of the comparator CMP1 is kept higher than 0V even when the command DUTY is 0% non-energized. Thus, the comparison signal from the comparator CMP1 can be reliably set to the L level.

  Therefore, the command DUTY is 0% without reducing the diagnosis detection function of the microcomputer 4 such as masking the diagnosis detection function of the microcomputer 4 when the command DUTY is close to 0% as in the prior art. The upstream side MOS 10 can be reliably turned off during the region close to, so that it is possible to reliably prevent the microcomputer 4 from erroneously detecting an abnormality in the drive system.

  Further, when the abnormality of the microcomputer 4 is detected by the monitoring IC 5 and the transistor T1 of the receiving circuit 6 is forcibly turned off, the voltage of the non-inverting input terminal of the comparator CMP1 becomes 0V. Is maintained at a value higher than 0 V, the comparison signal from the comparator CMP1 can be reliably set to L level, and the upstream MOS 10 can be reliably turned off.

In the present embodiment, the constant current circuit 41 corresponds to the constant current power source of the present invention.
[Modification]
Although the embodiments of the present invention have been described above, the embodiments of the present invention are not limited to the above-described embodiments, and can take various forms as long as they belong to the technical scope of the present invention. Needless to say.

  For example, in the first embodiment, the voltage of the collector of the transistor T1 in the receiving circuit 6 is taken into the edge detection circuit 26. However, the upstream drive command SDH from the microcomputer 4 may be taken directly in, or the receiving circuit 6 The voltage VD at the connection point of the resistors R11 and R12 may be taken in. That is, as long as the edge change of the upstream drive command SDH from the microcomputer 4 can be detected, it is not always necessary to capture the upstream drive command SDH itself.

  In the first embodiment, when the zero duty detection circuit 21 detects 0% of the command DUTY, the AND gate 22 forces the comparison signal input from the comparator CMP1 to the drive circuit 8 to the L level. By fixing, the drive signal is fixed to the H level and the upstream MOS 10 is turned off. However, providing the AND gate 22 in this way is merely an example. Instead of the AND gate 22, for example, a circuit for forcibly fixing the collector of the transistor T2 in the drive circuit 8 to the H level may be provided.

  In the first embodiment, when the command DUTY becomes 0%, this is detected and the comparison signal from the comparator CMP1 is forcibly fixed to the L level. The reason why the microcomputer 4 may erroneously detect an abnormality in the drive system due to the offset of the operational amplifier OP1 or the comparator CMP1 is not limited to the case where the command DUTY is 0%, but may be erroneous even in a region close to 0%. Detection may occur.

  Therefore, in the first embodiment, the zero duty detection means 21 detects this when the command DUTY is in a region close to 0% (from 0% to a predetermined duty ratio region, for example, 0 to 1%). The L level signal may be input to the AND gate 22. Specifically, for example, a configuration may be considered in which a filter is provided at the input stage of the edge detection circuit 26 so that an edge when the command DUTY is in a region close to 0% is not input. Of course, this is only an example, and various configurations are conceivable as long as the command DUTY is detected in a predetermined region and can be reliably output to the AND gate 22.

  In this way, when the command DUTY is close to 0%, this is detected, and during that time, the comparison signal from the comparator CMP1 is forcibly fixed to the L level (and the upstream side MOS 10 is forcibly turned off. By doing so, it is possible to reliably fix the upstream-side MOS 10 off while the command DUTY is close to 0%, and reliably prevent the microcomputer 4 from erroneously detecting an abnormality in the drive system. it can.

  In the second and third embodiments, as a specific configuration for the inverting input terminal of the comparator CMP1 to be higher than 0 V even when no power is supplied, a configuration in which a pull-up resistor R30 is provided (second embodiment) In addition to the configuration in which the constant current circuit 41 constantly flows current to the current detection resistor R2 (third embodiment), in addition to these configurations, the inverting input terminal of the comparator CMP1 during non-energization is set higher than 0V. As long as it can be held, various configurations can be adopted.

  Moreover, although each said embodiment demonstrated the case where the inductive load drive device of this invention was applied to the common rail type fuel injection system of a diesel engine, not only this but this invention is based on the current feedback circuit by hardware. Applicable to all inductive load drive devices having an abnormality detection function for controlling energization to an inductive load and detecting an abnormality of a drive system based on a drive signal to a switching element for energization control. be able to.

DESCRIPTION OF SYMBOLS 1,30,40,100 ... Inductive load drive device, 2 ... Solenoid valve, 3 ... Current detection circuit, 4 ... Microcomputer, 5 ... Monitoring IC, 6 ... Reception circuit, 7 ... Deviation integration circuit, 8 ... Drive circuit, DESCRIPTION OF SYMBOLS 9 ... Current limiter circuit, 10 ... Upstream side MOS, 11 ... Radio noise reduction circuit, 12 ... Abnormal forced stop circuit, 20 ... Downstream side MOS, 21 ... Zero duty detection circuit, 22 ... AND gate, 26 ... Edge detection circuit 27 ... Counter, 41 ... Constant current circuit, 100 ... Inductive load driving device,
C1, C2 ... Capacitor, CMP1 ... Comparator, D1 ... Diode, Lo ... Linear solenoid, OP1 ... Operational amplifier, R1-R27 ... Resistor, R30 ... Pull-up resistor, T1-T6 ... Transistor

Claims (11)

A switching element that is provided on a current-carrying path from a power source to the inductive load, and interrupts the current flowing through the inductive load;
Current detection means for detecting a current flowing through the inductive load and generating a detection voltage corresponding to the current;
A microcomputer having a duty ratio corresponding to a target current to be passed through the inductive load, and outputting a pulsed drive command for instructing driving of the inductive load;
Drive voltage output means for outputting a drive voltage having a duty ratio corresponding to the drive command from the microcomputer;
A drive voltage output that is input to the other end of the capacitor via the resistor with reference to the detection voltage from the current detection means that is input to one end of the capacitor; A deviation integrating circuit that is charged and discharged by the drive voltage from the means, the time constant of which is greater than the cycle of the drive command, and the polarity of the charging voltage of the capacitor changes in the same cycle as the cycle of the drive command;
Comparing means for comparing the voltage across the capacitor constituting the deviation integrating circuit and outputting a pulsed comparison signal according to the comparison result;
Drive means for outputting a drive signal for turning on / off the switching element to the switching element in response to the comparison signal from the comparison means;
An inductive load drive device configured to detect an abnormality in the energization path based on the drive signal from the drive means,
Zero duty detection means for detecting when the duty ratio of the drive command from the microcomputer is 0%;
When the zero duty detection means detects that the duty ratio is 0%, the drive signal is set to a negative level which is a level for turning off the switching element regardless of the comparison signal from the comparison means. Forcibly turning off means for forcibly turning off the switching element,
An inductive load driving device comprising: The inductive load driving device according to claim 1,
The forced-off means fixes the level of the comparison signal input to the driving means to the negative level when the zero duty detection means detects that the duty ratio is 0%. Inductive load driving device. The inductive load driving device according to claim 1 or 2,
The zero duty detection means includes
Level change detecting means for detecting a level change of the drive command from the microcomputer;
Each time the level change detection means detects the timing at which the level of the drive command changes from the active level, which is the level to turn on the switching element, to the negative level, the time duration of the negative level is counted, Detection signal output means for outputting a detection signal indicating that the duty ratio is 0% when the duration exceeds a predetermined time threshold;
An inductive load driving device comprising: The inductive load driving device according to any one of claims 1 to 3,
The current detection means includes
A current detection resistor connected in series with the inductive load on the energization path;
An amplification circuit using an operational amplifier that generates the detection voltage by amplifying the voltage across the current detection resistor at a predetermined amplification factor;
An inductive load driving device comprising: The inductive load driving device according to any one of claims 1 to 4,
The inductive load driving device characterized in that the comparison means is a comparator. A switching element that is provided on a current-carrying path from a power source to the inductive load, and interrupts the current flowing through the inductive load;
Current detection means for detecting a current flowing through the inductive load and generating a detection voltage corresponding to the current;
A microcomputer having a duty ratio corresponding to a target current to be passed through the inductive load, and outputting a pulsed drive command for instructing driving of the inductive load;
Drive voltage output means for outputting a drive voltage having a duty ratio corresponding to the drive command from the microcomputer;
A drive voltage output that is input to the other end of the capacitor via the resistor with reference to the detection voltage from the current detection means that is input to one end of the capacitor; A deviation integrating circuit that is charged and discharged by the drive voltage from the means, the time constant of which is greater than the cycle of the drive command, and the polarity of the charging voltage of the capacitor changes in the same cycle as the cycle of the drive command;
Comparing means for comparing the voltage across the capacitor constituting the deviation integrating circuit and outputting a pulsed comparison signal according to the comparison result;
Drive means for outputting a drive signal for turning on / off the switching element to the switching element in response to the comparison signal from the comparison means;
An inductive load drive device configured to detect an abnormality in the energization path based on the drive signal from the drive means,
Voltage holding means for holding the voltage at one end of the capacitor constituting the deviation integrating circuit at a value higher than 0 V when the duty ratio of the drive command is 0%. Inductive load driving device. The inductive load driving device according to claim 6,
The voltage holding means is
A pull-up resistor having one end connected to one end of the capacitor;
A constant voltage power source connected to the other end of the pull-up resistor, and applying a voltage to one end of the capacitor via the pull-up resistor;
An inductive load driving device comprising: The inductive load driving device according to claim 7,
The current detection means includes
A current detection resistor connected in series with the inductive load on the energization path;
An amplifier circuit using an operational amplifier that generates the detection voltage by amplifying the voltage across the current detection resistor at a predetermined amplification factor;
An output resistor connected to the output terminal of the operational amplifier;
The inductive load driving device is characterized in that the detection voltage from the operational amplifier is input to one end of the capacitor via the output resistor. The inductive load driving device according to claim 8,
The comparison means is a comparator;
One end of the capacitor is connected to the inverting input terminal of the comparator and the other end of the capacitor is connected to the non-inverting input terminal of the comparator;
The resistance value of the pull-up resistor is set to such a value that a divided value obtained by dividing the voltage of the constant voltage power source by the pull-up resistor and the output resistor is larger than the offset voltage of the comparator. An inductive load driving device characterized by that. The inductive load driving device according to claim 6,
The current detection means includes
A current detection resistor connected in series with the inductive load on the energization path on the downstream side of the inductive load and the switching element;
An amplification circuit using an operational amplifier that generates the detection voltage by amplifying the voltage across the current detection resistor at a predetermined amplification factor;
With
The voltage holding unit includes a constant current power source that boosts the detection voltage from the current detection unit by a value corresponding to the predetermined amount of current by flowing a predetermined amount of current through the current detection resistor. An inductive load driving device characterized by comprising: The inductive load driving device according to claim 10,
The comparison means is a comparator;
One end of the capacitor is connected to the inverting input terminal of the comparator and the other end of the capacitor is connected to the non-inverting input terminal of the comparator;
The value of the predetermined amount of current that the constant current power supply passes through the current detection resistor is such that the detection voltage that is output from the current detection means when the current flows through the current detection resistor is greater than the offset voltage of the comparator. The inductive load driving device is characterized in that the value is set to be large.

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