JP2013255304A - Abnormality detection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an abnormality detection device capable of protecting a device by performing sufficient abnormality detection on the basis of a detection voltage of an energizing node when energizing an inductive load in accordance with on/off drive of a switching element.SOLUTION: A control circuit 11 detects an over-current abnormality and/or a short circuit abnormality on the basis of a drain voltage of a MOSFET 4 while the MOSFET 4 is turned off. At this time, an abnormality is detected except for a mask period in which a mask period generation circuit 11b generates a mask. When the drain voltage of the MOSFET 4 exceeds a threshold voltage Vth during an over-current detection period (B) in an off drive period where the drain voltage rises and changes from the vicinity of the lowest value, the case is regarded as a short circuit abnormality.

Description

  The present invention relates to an abnormality detection device that detects an abnormality such as an overcurrent or a short circuit of a switching element.

  Generally, when a switching element (for example, a power MOSFET) is used in various drive circuits, a device protection function is provided. Examples of the device protection function include an overcurrent detection function for detecting an overcurrent, and a short circuit detection function for detecting a short circuit abnormality of the switching function. This short-circuit detection function can be implemented by making a slight change to the overcurrent detection circuit.

  Usually, for example, a current detection method using a shunt resistor is used as a method for detecting an overcurrent flowing in the power MOSFET. However, a method of providing a sensing mirror circuit and mirroring the current flowing in the power MOSFET to be detected has also been put into practical use. . Among them, for the purpose of reducing circuit elements, a method for detecting the drain voltage of the power MOSFET and performing overcurrent protection has been proposed (for example, see Patent Document 1).

Japanese Utility Model Publication 8-7831

  According to the method described in Patent Document 1, when the drain voltage of the power MOSFET rises above a predetermined voltage, it is determined that an overcurrent has flowed through the drain, and processing such as reducing the gate voltage is performed. In this abnormality detection process, it cannot be said that sufficient abnormality detection process is performed. Similar problems occur when various switching elements are employed instead of the power MOSFET.

  An object of the present invention is to provide an abnormality detection apparatus that can protect a device by performing sufficient abnormality detection based on a detection voltage of the current-carrying node when an inductive load is energized in accordance with on / off driving of a switching element. It is to provide.

  According to the first aspect of the present invention, the abnormality detection means detects an abnormality based on the detection voltage of the energizing node that supplies current to the inductive load in accordance with the on / off drive of the switching element. An abnormality is detected based on the detection voltage of the energized node during the period in which is driven off. For this reason, the abnormality detection conventionally performed during the ON drive period of the switching element can be detected even during the OFF drive period, so that the abnormality can be sufficiently detected and the device can be protected.

According to the second aspect of the present invention, the abnormality can be detected by invalidating the detected voltage change of the energization node according to the on / off drive timing of the switching element.
According to the third aspect of the present invention, the abnormality detection means considers an overcurrent abnormality on the condition that the detection voltage of the energized node straddles the threshold voltage for overcurrent detection. For this reason, an overcurrent abnormality can be detected.

  According to the fourth aspect of the invention, the abnormality detection means considers an abnormality as long as the change in the detection voltage of the energized node does not change more rapidly than the predetermined first gradient at the off-drive timing of the switching element. Yes. For this reason, the abnormality can be sufficiently detected.

  According to the fifth aspect of the present invention, the abnormality detection means detects a change in the detected voltage of the energized node detected in a direction opposite to the detected voltage change in the off drive timing of the switching element during the off drive period of the switching element. This is regarded as a short circuit abnormality of the switching element on the condition that it is steeper than the predetermined second gradient. For this reason, a short circuit abnormality of the switching element can be detected.

  According to the sixth aspect of the present invention, the abnormality detection means is regarded as a short-circuit abnormality on the condition that the change in the detection voltage of the energized node is steeper than the predetermined second gradient ignoring the mask period by the invalidation means. I'm jealous. For this reason, a short circuit abnormality of the switching element can be detected.

1 is a block diagram schematically showing an electrical configuration in a first embodiment of the present invention. Block diagram schematically showing the internal electrical configuration of the control circuit Timing chart showing waveforms of main parts during normal operation Example of generation of mask period (1) Example of generation of mask period (2) Timing chart showing the waveform of the main part when overcurrent is detected Timing chart showing the mode of abnormality detection when the switching element is short-circuited during the ON drive period Timing chart showing the mode of abnormality detection when the switching element is short-circuited during the off-drive period FIG. 3 equivalent view showing the second embodiment of the present invention (No. 1) Figure 3 equivalent (part 2)

(First embodiment)
Hereinafter, a first embodiment of the abnormality detection device X will be described with reference to FIGS. FIG. 1 shows the electrical configuration of the abnormality detection apparatus. Here, a drive circuit for driving an inductive load configured in the step-up DCDC converter 1 will be described as an example.

  Between the output voltage Vcc of the power supply circuit 2 and the ground GND, the primary side of the transformer 3 whose low potential side is commonly connected to the secondary side is connected to the high side, and an N-channel type power MOSFET (switching element) (Hereinafter simply referred to as MOSFET). The drain and source of 4 are connected to the low side.

  On the secondary side of the transformer 3, a diode 5 and a capacitor 6 are connected in series, and a terminal voltage HV of the capacitor 6 is given to the load 7. By applying the DCDC converter 1 using such a non-insulated transformer 3 and adjusting the primary / secondary winding ratio of the transformer 3 to increase the voltage amplification factor, a general boost DCDC The boost voltage can be made higher than that of the converter.

  The drain voltage of the MOSFET 4 (corresponding to the voltage at the energizing node) is applied to the non-inverting input terminal of the converter 9 through the current limiting resistor 8. A reference voltage source 10 is connected to the inverting input terminal of the comparator 9. The comparator 9 compares the reference voltage source 10 with the drain voltage of the MOSFET 4, and outputs the comparison result to the control circuit 11.

  The drain voltage of the MOSFET 4 is also given to the high pass filter 12. The high-pass filter 12 is a filter that passes only a steep change in the drain voltage of the MOSFET 4 and outputs the steep change in the drain voltage as a pulse. The output of the high pass filter 12 is given to the pulse shaping circuit 13. The pulse shaping circuit 13 shapes the output of the high-pass filter 12 into a rectangular waveform and outputs the waveform to the control circuit 11.

  FIG. 2 schematically shows an internal electrical configuration of the control circuit 11 by a block diagram. The control circuit 11 includes a gate drive timing generation circuit 11a, a mask period generation circuit 11b, a gate drive mask circuit 11c, and a power supply control circuit 11d, and is configured as an abnormality detection unit (abnormality detection means). The gate drive timing generation circuit 11a generates a PWM signal having a predetermined frequency and a predetermined duty ratio in accordance with a clock having a predetermined frequency generated by a clock generation circuit (not shown).

  The mask period generation circuit 11b is configured by combining a resistor and a capacitor, for example, and extends the pulse signal output from the pulse shaping circuit 13. This prolonged pulse signal becomes a mask period described later. The gate drive mask circuit 11c is based on the output signal of the comparator 9, the output signal of the gate drive timing generation circuit 11a, and the output signal of the mask period generation circuit 11b, except for the mask period output by the mask period generation circuit 11b. An on / off timing control signal is output to the gate drive circuit 14.

  The gate drive circuit 14 controls the duty ratio of the PWM signal based on the given control signal, and applies the PWM voltage to the gate of the MOSFET 4. As a result, the DCDC converter 1 boosts the power supply voltage Vcc of the power supply circuit 2 based on the control circuit 11 and outputs a DC voltage HV. On the other hand, the power supply control circuit 11d of the control circuit 11 outputs the power supply voltage Vcc of the power supply circuit 2 on / off based on the output signal of the gate drive timing generation circuit 11a, the output signal of the mask period generation circuit 11b, and the output signal of the comparator 9. It is controllable.

  As shown in the waveform example during normal operation in FIG. 3, the control circuit 11 drives and controls the MOSFET 4 with a PWM signal having a predetermined frequency and duty ratio through the gate drive circuit 14. At this time, when the MOSFET 4 is turned on, the drain voltage of the MOSFET 4 rapidly decreases.

  When the drain voltage of the MOSFET 4 sharply decreases, the high-pass filter 12 uses the sharp change in the drain voltage as a pulse signal, and the pulse shaping circuit 13 shapes the detection pulse into a falling rectangular waveform (detection pulse at timing (A)). reference). The mask period generation circuit 11b of the control circuit 11 receives the falling rectangular wave signal and generates a mask signal for a predetermined period T including the rectangular wave pulse period (see the mask period at timing (A)). The reason for generating the mask signal is to invalidate the determination in the signal steep change period when the drain voltage of the MOSFET 4 is ringing and changes steeply during normal operation. The predetermined period T described above indicates a predetermined period, but this may not be a fixed period.

  4 and 5 show examples of setting the mask period. The example shown in FIG. 3 shows a schematic example in which the application timing of the on / off control signal of the MOSFET 4 and the decrease timing of the drain voltage are almost the same, but the MOSFET 4 requires charging / discharging time of its gate capacitance. The on / off control signal application timing and the drain voltage decrease / rise timing slightly deviate (about several μs).

  Therefore, as shown in FIG. 4, the mask period generation circuit 11b may generate the mask period in accordance with the ON control signal or the OFF control signal of the MOSFET 4, or the rising timing or falling edge of the drain voltage as shown in FIG. The mask period generation circuit 11b may generate a mask period according to the timing. Then, the mask period can be changed according to the situation. During the mask period, the output of the normal comparator 9 is invalidated.

  The reference drawing will be described with reference to FIG. When the MOSFET 4 is turned on, a voltage near the power supply voltage Vcc is applied to the primary side of the transformer 3. At this time, a current flows to the primary side behind the applied voltage on the primary side of the transformer 3. When current flows to the primary side of the transformer 3, the drain current of the MOSFET 4 flows. Since the primary side of the transformer 3 is an inductor, the drain current increases monotonously. When the drain current monotonously increases, the drain voltage of MOSFET 4 also monotonously increases.

  A threshold voltage Vth for overcurrent detection is set in advance between the maximum value (MAX: ≈power supply voltage Vcc) and the minimum value (MIN: ≈0 V) of the drain voltage of the MOSFET 4, and the reference voltage source 10 is set to the threshold voltage Vth. , The comparator 9 compares the output threshold voltage Vth of the reference voltage source 10 with the drain voltage of the MOSFET 4.

  The comparator 9 outputs this comparison result to the gate drive mask circuit 11c and the power supply control circuit 11d of the control circuit 11, and the gate drive mask circuit 11c of the control circuit 11 is in the ON drive period of the MOSFET 4 except for the mask period. It is determined whether or not the drain voltage exceeds the threshold voltage Vth. Usually, an overcurrent abnormality occurs during the ON drive period of the MOSFET 4. When the drain voltage of the MOSFET 4 exceeds the threshold voltage Vth, it is determined that the drain current Id also exceeds the threshold current Ith accordingly (see the overcurrent detection period (B) in FIG. 3).

  In the normal timing chart shown in FIG. 3, since the drain voltage of the MOSFET 4 does not exceed the overcurrent detection threshold voltage Vth in the overcurrent detection period (B), the drain current is in the normal range (less than the threshold current Ith). Maintained. However, in the timing chart of FIG. 6 showing the operation at the time of abnormality (when detecting an overcurrent of the inductive load), when the drain current Id exceeds the threshold current Ith due to some influence, the drain voltage of the MOSFET 4 is changed to the threshold voltage Vth at this timing. Over.

  When it is detected that the drain voltage of the MOSFET 4 exceeds the threshold voltage Vth during the overcurrent detection period (B), the control circuit 11 considers that the drain current of the MOSFET 4 exceeds the threshold current Ith. An off drive control signal is applied to the gate to forcibly control the MOSFET 4 to be turned off (see timing (C) in FIG. 6).

  When the control circuit 11 forcibly controls the MOSFET 4 to be turned off, the drain voltage of the MOSFET 4 suddenly rises to the maximum value (MAX), and as long as an overcurrent is detected, the drain voltage does not exceed the threshold voltage Vth. The overcurrent detection operation continues.

  Further, the abnormality detection device of the present embodiment has a function of detecting a drain-source short-circuit abnormality of the MOSFET 4 in addition to such an overcurrent detection function. Here, the case where the drain and source of the MOSFET 4 are short-circuited during the on-drive period or the off-drive period due to some influence will be described.

<Short-circuit abnormality during on-drive period of MOSFET 4>
If a short circuit abnormality occurs between the drain and source during the on-drive period of the MOSFET 4, even if the control circuit 11 changes the gate control signal of the MOSFET 4 from on to off, the MOSFET 4 remains on.

  Then, as shown in the timing chart of FIG. 7, the drain voltage of the MOSFET 4 continues to rise while being turned on. During this time, since the voltage is continuously applied to the primary side of the transformer 3, the primary side voltage continues to rise as it is (see the timing after (D) in FIG. 7).

  At this time, there are two methods for the control circuit 11 to detect a short circuit abnormality between the drain and source of the MOSFET 4, and (1) a method for detecting that the drain voltage of the MOSFET 4 exceeds the threshold voltage Vth for overcurrent detection, (2) A method for detecting that the drain voltage does not change sharply at the timing when the gate control signal of the MOSFET 4 is turned from on to off.

  In the method (1), even when the gate control signal of the MOSFET 4 is turned from on to off, if the short circuit abnormality occurs between the drain and source of the MOSFET 4, the control circuit 11 causes a steep change in the drain voltage through the high-pass filter 12 as a pulse. It will not be detected. Therefore, there is no mask period at the timing (D) in FIG.

  Normally, the output of the comparator 9 is invalidated (mask period) in accordance with the rising edge of the drain voltage during the period in which the MOSFET 4 is driven off. However, since no edge is generated when a short circuit abnormality occurs, the output of the comparator 9 is It remains activated and the overcurrent detection period (B) is continued. Therefore, the overcurrent detection period (B) continues after the timing (D).

  Thereafter, when the drain current Id of the MOSFET 4 exceeds the threshold current Ith, the drain voltage also exceeds the threshold voltage Vth, so that the output of the comparator 9 is inverted. Since it is not a mask period at this timing, it can be detected that the drain current exceeds the threshold current Ith at the timing when the drain voltage exceeds the threshold voltage Vth. Thus, a short circuit abnormality that occurs during the on-drive period can be detected during the off-drive period.

  In the method (2) described above, when the control circuit 11 turns off the MOSFET 4, an off control signal is applied to the MOSFET 4 through the gate drive circuit 14, but thereafter the drain voltage changes abruptly (from a predetermined first gradient). Therefore, it can be determined that an abnormality has occurred. When the control circuit 11 detects such a short-circuit abnormality, the power supply control circuit 11d performs an abnormality countermeasure such as forcibly turning off the power supply voltage Vcc output of the power supply circuit 2.

<Short-circuit abnormality during off-drive period of MOSFET 4>
When the MOSFET 4 is turned off, the drain voltage of the MOSFET 4 rises to the maximum value (MAX). At this time, the case where the MOSFET 4 breaks down and breakdown occurs between the drain and the source will be described. At this time, if a drain-source short circuit abnormality occurs due to breakdown voltage breakdown or the like, the drain voltage rapidly decreases as shown in FIG. 8 (see the timing in FIG. 8E).

  Then, the falling pulse is detected through the high-pass filter 12, and the control circuit 11 can determine that there is a short circuit abnormality by detecting the falling pulse. Since the normal falling edge occurs after the transition from OFF to ON, it is abnormal to generate the falling edge during the OFF drive period. For this reason, the control circuit 11 can detect a short circuit abnormality. During the off drive period (off control signal output), a short circuit abnormality may be considered when the falling edge is detected ignoring the mask period. In this manner, even if a short circuit abnormality occurs between the drain and source of the MOSFET 4, this abnormality can be detected during the off-drive period of the MOSFET 4.

  As described above, according to the present embodiment, the control circuit 11 can detect an overcurrent abnormality and / or a short-circuit abnormality based on the drain voltage of the MOSFET 4 during the period in which the MOSFET 4 is driven to turn off.

  Further, since the control circuit 11 detects an abnormality except for the mask period generated by the mask period generation circuit 11b, the influence of the ringing of the drain voltage of the MOSFET 4 can be eliminated. It is considered as a short circuit abnormality on condition that the drain voltage exceeds the threshold voltage Vth in the overcurrent detection period (B) during the off-drive period in which the drain voltage rises from near the minimum value (MIN). For this reason, even if a short circuit abnormality occurs during the ON drive period, this short circuit abnormality can be detected during the OFF drive period.

  In particular, when the control circuit 11 shifts the MOSFET 4 from the on-control period to the off-control, a mask period corresponding to the falling edge is used, and when the transistor 4 transitions from the off-control period to the on-control, the rising edge Anomaly detection may be performed using a mask period corresponding to an edge and excluding this mask period. Then, erroneous detection can be prevented as much as possible.

  When the gate drive mask circuit 11c outputs an off drive control signal to the gate drive circuit 14, the drain voltage does not change more rapidly than the predetermined first gradient, and no detection pulse is detected through the high-pass filter 12. It is assumed that an abnormality exists. Therefore, an abnormality can be detected during the off drive period.

  In addition, during the off-drive period of the transistor 4, the change in the drain voltage detected in the opposite direction (decreasing direction) to the detection voltage change at the off-drive timing of the transistor 4 becomes steeper than the second gradient and is detected through the high-pass filter 12. It is assumed that the short circuit abnormality of the transistor 4 exists on the condition that the pulse is detected. Thereby, a short circuit abnormality can be detected during the off drive period.

(Second Embodiment)
FIGS. 9 to 10 show a second embodiment of the present invention. The difference from the above-described embodiment is that the threshold voltage used for overcurrent detection and the threshold voltage used for short circuit detection are switched to cause overcurrent abnormalities and short circuits. An abnormality is being detected. Parts that are the same as or similar to those in the previous embodiment are given the same or similar reference numerals, and descriptions thereof are omitted. Hereinafter, different parts will be mainly described.

  FIG. 9 shows a setting example of the threshold voltages Vth1 and Vth2. The control circuit 11 is configured by connecting a control line to the reference voltage source 10, and switches the output threshold voltage of the reference voltage source 10 by outputting a control signal to the reference voltage source 10 through the control line. In this case, the control circuit 11 switches between the two types of threshold voltages Vth1 and Vth2 by the following two methods.

  (1) A method of switching the threshold voltage Vth1 for overcurrent detection and the threshold voltage Vth2 for short circuit detection each time the gate control signal of the transistor 4 is switched from on to off or from off to on. 2) When the drain voltage of the transistor 4 crosses the threshold voltage Vth1 for overcurrent detection, the transistor 4 switches to the threshold voltage Vth2 for short circuit detection, and when the drain voltage crosses the threshold voltage Vth2 for short circuit detection, the threshold voltage for overcurrent detection A method of switching to Vth1 is used.

  In the case of the method (1), the control circuit 11 switches the threshold voltages Vth1 and Vth2 every time an on / off drive control signal is output from the gate drive mask circuit 11c. In the method (2), the control circuit 11 switches the threshold voltages Vth1 and Vth2 at the output conversion timing of the comparator 9.

  The example shown in FIG. 9 shows a signal waveform during normal operation in the method (1), and the drain voltage of the transistor 4 is normally close to 0 V during the on-drive period of the transistor 4, but in this case For example, a threshold voltage Vth1 for detecting an overcurrent abnormality is set. Further, for example, a threshold voltage Vth2 for detecting a short circuit abnormality is set during the off-drive period of the transistor 4.

  The magnitude relationship between the threshold voltages Vth1 and Vth2 may be set to any value. However, as shown in FIG. 9, the threshold voltage Vth1 is set to be relatively low during the on-drive period, and is relatively set during the off-drive period. It is preferable to set a high threshold voltage Vth2. Then, the threshold voltages Vth1 and Vth2 can be set on the side close to the voltage during normal operation.

  That is, during the on-drive period of the transistor 4, the drain voltage of the transistor 4 normally fluctuates on the side closer to the minimum value MIN than the maximum value MAX, so the threshold voltage Vth1 should be set to the side close to the minimum value MIN side. . Further, during the off-drive period of the transistor 4, the drain voltage of the transistor 4 is normally substantially constant on the maximum value MAX side, so it is preferable to set the drain voltage on the side close to the maximum value MAX.

  Further, the example shown in FIG. 10 shows a signal waveform during normal operation in the method (2). During an abnormal operation, an abnormality can be detected during the off-drive period as in FIG. 7 described in the above embodiment. As shown in FIG. 10, as an example of an abnormal operation, when the overcurrent detection threshold voltage Vth1 is exceeded during the off-drive period, it is considered abnormal, and the abnormality can be detected at a timing exceeding the threshold voltage Vth1.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be modified or expanded as follows, for example. For example, a mode in which coils (inductive loads) such as solenoids, relays, and motors are arranged on the high side and driven by switching elements arranged on the low side may be applied. That is, the circuit configuration is not limited to the configuration of the DCDC converter 1 shown in the above-described embodiment as long as the switching element is arranged on the low side and the high side inductive load is driven. Although an example using the non-insulated transformer 3 has been shown, a flyback DCDC converter using an insulated transformer may be applied. Further, a boost type DCDC converter may be used.

  In the drawing, 3 is a non-insulated transformer (inductive load), 4 is a power MOSFET (switching element), and 11 is a control circuit (abnormality detection means).

Claims (7)

In the circuit in which the switching element (4) is disposed on the low side between the first and second power supply lines and the inductive load (3) is connected to the high side, the switching element (4) and the inductive load (3 ) An abnormality detection means (11) for detecting an abnormality based on a detection voltage of an energization node provided between the energization nodes and energizing the inductive load (3) according to the on / off drive of the switching element (4). )
The abnormality detection device (11) detects an abnormality based on a detection voltage of the energization node during a period in which the switching element (4) is driven to be turned off. A disabling means (11b) for masking a change in the detection voltage of the energization node according to the on / off drive timing of the switching element (4);
The abnormality detection device according to claim 1, wherein the abnormality detection means (11) detects an abnormality except for a mask period by the invalidation means (11b). The detection voltage of the energization node is a voltage that decreases to near the minimum value when the switching element is turned on and then increases and changes,
The abnormality detection means (11) detects a short-circuit abnormality on the condition that the detection voltage of the energized node rises after the switching element starts to be turned on and exceeds a threshold voltage in the overcurrent detection period during the off drive period. The abnormality detection device according to claim 1, wherein the abnormality detection device is regarded.   The abnormality detection means (11) assumes that an abnormality exists on the condition that the change in the detection voltage of the energization node does not change more rapidly than the predetermined first gradient at the off-drive timing of the switching element (4). The abnormality detection device according to any one of claims 1 to 3.   The abnormality detection means (11) is a detection voltage of the energization node that is detected in a direction opposite to a detection voltage change of the off drive timing of the switching element (4) during the off drive period of the switching element (4). 5. The abnormality detection device according to claim 1, wherein the switching element is regarded as a short-circuit abnormality of the switching element on condition that the change of A is steeper than a predetermined second gradient. A disabling means (11b) for masking a change in the detection voltage of the energization node according to the on / off drive timing of the switching element (4);
The abnormality detection means (11) is regarded as a short-circuit abnormality on the condition that the change of the detection voltage of the energization node is steeper than a predetermined second gradient ignoring the mask period by the invalidation means (11b). The abnormality detection apparatus according to claim 5, wherein   The abnormality detection means (11) detects the overcurrent abnormality and the short circuit abnormality by switching a threshold voltage used at the time of overcurrent detection and a threshold voltage used at the time of short circuit detection. The abnormality detection device described in 1.

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