JP2000298523A - Constant voltage output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of a constant voltage output circuit itself and to reduce the change of output voltage. SOLUTION: This constant voltage output circuit is provided with an output circuit 101 for supplying power to an oscillation circuit or the like, a feedback circuit 102 for feeding back and inputting an output from the circuit 101 and outputting a control signal for controlling the output from the circuit 101, a sampling circuit 103 for continuously turning on/off the circuit 102, a switch 104 arranged on a signal line for inputting the control signal outputted from the circuit 102 to the circuit 101 and capable of turning on/off the signal line on the basis of the ON/OFF of the circuit 103, and a holding circuit 105 arranged between the switch 104 and the circuit 101 and capable of holding the input terminal of the circuit 101 for inputting the control signal at a signal level obtained before turning off the signal line when the signal line is turned off by the switch 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant voltage output circuit for outputting a constant voltage, and more particularly to a constant voltage output circuit for reducing power consumption by performing a sampling operation of a feedback circuit.

[0002]

2. Description of the Related Art As a conventional constant voltage output circuit, for example,
There is a "constant voltage output circuit" disclosed in Japanese Patent Application Laid-Open No. 6-59756. This circuit uses the constant voltage output of the constant voltage circuit as the power supply of the oscillation circuit, so that the output voltage of the constant voltage circuit exhibits a change rate characteristic equal to the oscillation start voltage or the oscillation maintenance voltage of the oscillation circuit. It was done. Therefore, in the manufacturing process, even if the threshold voltage of the transistor constituting each circuit changes, the voltage difference between the oscillation start voltage or the oscillation sustain voltage of the oscillation circuit and the output voltage of the constant voltage circuit becomes substantially constant, and the output voltage Can be reduced to near the absolute value of the oscillation start voltage or the oscillation sustain voltage, and the power consumption of the oscillation circuit can be reduced.

[0003] An oscillator circuit, a constant voltage generating circuit, a semiconductor device,
And a portable electronic device and a watch equipped with the same, adjust the threshold voltage of the transistor constituting the oscillation inverter of the oscillation circuit and the threshold voltage of the transistor connected to the input of the operational amplifier of the constant voltage generation circuit. It is described that the power consumption of the oscillation circuit is thereby reduced.

However, in the above-described constant voltage output circuits disclosed in JP-A-6-59756 and JP-A-10-21686, the power consumption of the oscillation circuit to which power is supplied can be reduced. However, there is a problem that the power consumption of the constant voltage output circuit itself is still large.

As a conventional constant voltage output circuit for solving this problem, there is provided a constant voltage output circuit for supplying power to an oscillation circuit or the like of a wristwatch, and an output circuit for supplying power to the oscillation circuit or the like of a wristwatch; And a sampling circuit that continuously turns on and off the feedback circuit. This constant voltage output circuit does not keep the feedback circuit on, but turns on and off continuously, so the power consumed by the feedback circuit can be reduced and the power consumption of the constant voltage output circuit itself can be reduced. it can.

[0006]

However, according to the above-described conventional constant voltage output circuit in which the feedback circuit is continuously turned on and off, when the feedback circuit is turned off, the feedback circuit which is turned off is turned off. Due to the influence, the voltage of the input terminal of the output circuit for inputting the control signal changes, so that there is a problem that the output of the output circuit changes greatly and the output voltage changes greatly.

Further, the absolute value of the output voltage changes in a wave-like manner in accordance with the on / off cycle of the feedback circuit due to a change in the output of the output circuit when the feedback circuit is turned off. In this case, a voltage having an absolute value higher than necessary is supplied to the target circuit to which the power supply is supplied, and there is a disadvantage that power consumption in the target circuit increases.
Note that the voltage level of the absolute value of the output voltage should be such that the absolute value of the output voltage does not fall below the absolute value of the stop voltage of the oscillation circuit or the like even at the trough of the wave, taking into account the wave-like change. Must be set.

The present invention has been made in view of the above, and has as its object to reduce the power consumption of the constant voltage output circuit itself and reduce the change in the output voltage.

[0009]

In order to achieve the above object, a constant voltage output circuit according to claim 1 is a constant voltage output circuit for supplying power to a target circuit to which power is to be supplied. An output circuit for supplying power to the circuit, a feedback circuit for receiving an output of the output circuit as a feedback signal and outputting a control signal for controlling an output of the output circuit, and a sampling circuit for continuously turning on and off the feedback circuit A switch provided on a signal line for inputting a control signal output from the feedback circuit to the output circuit, and turning on and off the signal line based on on and off of the sampling circuit; Provided between the output circuit,
When the signal line is turned off by the switch, the input terminal of the output circuit for inputting the control signal,
And a holding circuit for holding the signal level before the signal line is turned off.

In the constant voltage output circuit of the first aspect, the sampling circuit continuously turns on and off the feedback circuit, and a signal line for inputting a control signal output from the feedback circuit to the output circuit. When the signal line is turned off based on the on / off state of the sampling circuit, the input terminal of the output circuit for inputting the control signal is held at the signal level before the signal line was turned off. As a result, there is no change in the voltage at the input terminal of the output circuit.

Further, the constant voltage output circuit according to claim 2 is
2. The constant voltage output circuit according to claim 1, wherein the feedback circuit includes a reference voltage generation circuit for generating a reference voltage, a load circuit for the feedback input, and a reference voltage generated by the reference voltage generation circuit. A differential circuit for receiving an output of the load circuit according to the feedback input and outputting the control signal, wherein the sampling circuit turns on and off the differential circuit.

In the constant voltage output circuit according to the second aspect, the sampling circuit continuously turns on and off the differential circuit.

Further, the constant voltage output circuit according to claim 3 is
2. The constant voltage output circuit according to claim 1, wherein the feedback circuit includes a reference voltage generation circuit for generating a reference voltage, a load circuit for the feedback input, and a reference voltage generated by the reference voltage generation circuit. A differential circuit that inputs an output of the load circuit according to the feedback input and outputs a control signal, wherein the sampling circuit turns on and off the differential circuit and the load circuit.

In the constant voltage output circuit according to the third aspect, the sampling circuit continuously turns on and off the differential circuit and the load circuit.

The constant voltage output circuit according to claim 4 is
4. The constant voltage output circuit according to claim 1, wherein said holding circuit comprises a phase compensation capacitor.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail in the order of Embodiment 1 and Embodiment 2 with reference to the accompanying drawings.

Embodiment 1 As a constant voltage output circuit according to the first embodiment, a constant voltage output circuit used for a wristwatch or a portable device and serving as a power supply of an oscillation circuit or the like will be described as an example with reference to FIGS. FIG. 1 is a block diagram showing a configuration of the constant voltage output circuit according to the first embodiment.

The constant voltage output circuit according to the first embodiment includes an output circuit 101 that supplies power to a not-shown target circuit, and an output circuit 101 that supplies power to a not-shown target circuit to which power is supplied. A feedback circuit 102 which receives a feedback input of an output of the circuit 101 and outputs a control signal for controlling an output of the output circuit 101; a sampling circuit 103 which continuously turns on and off the feedback circuit 102;
A switch 104 that is provided on a signal line for inputting the control signal output from the second circuit 2 to the output circuit 101 and that turns the signal line on and off based on the on and off of the sampling circuit 103; And a holding circuit 105 that holds an input terminal of the output circuit 101 for inputting a control signal at a signal level before the signal line is turned off when the signal line is turned off by the switch 104.
And

The feedback circuit 102 receives the output of the output circuit 101 as a feedback input and outputs a control signal. The sampling circuit 103 continuously turns on and off the feedback circuit 102, and the switch 104 turns on and off the signal line based on the on and off. When the signal line is turned off by the switch 104, the holding circuit 105 holds the input terminal of the output circuit 101 at a signal level before the signal is turned off.

FIG. 2 is a schematic circuit diagram showing a configuration of the constant voltage output circuit according to the first embodiment. In the constant voltage output circuit of the first embodiment, transistor QN13 is connected to output circuit 10
1, a load circuit comprising resistors R1 and R2, a differential circuit OP1, and a constant voltage source 201 for generating a reference voltage Vref form a feedback circuit 102, and a phase compensation capacitor CC forms a holding circuit 105. . Here, the output voltage VREG is obtained by the following equation. VREG = Vref × (R1 + R2) / R1

FIG. 3 is a circuit diagram showing a configuration of the constant voltage output circuit according to the first embodiment. In the constant voltage output circuit of the first embodiment, transistors QP11, constant current source 301 and transistors QP2, QP1, QN1, QP1
5, QP16, QN11, QP17 and QN12 constitute a differential circuit OP1, and transistors QP3 and QN
2 constitutes the switch 104. SP and SPX are
These signals have opposite logic and are output from the sampling circuit 103.

The operation of the first embodiment in the above configuration will be described. FIG. 4 is a timing chart of signals SP and SPX output from sampling circuit 103 of the first embodiment. SP is at a high level while the feedback circuit 102 is turned on (at the time of enable (EN)), and is at a low level while the feedback circuit 102 is turned off (at the time of hold (HOLD)). SPX has reverse logic to SP.

When enabled, SP is high level, SPX
Goes low, and the transistors QP1 and QN1
Is turned on, and the transistors QP11 and QP15 form a current mirror circuit. Transistor QP
A current determined by the characteristics of the transistor QP11 flows through 15 and branches into a current flowing through the transistor QP16 and a current flowing through the transistor QP17.

Here, the operation of the differential circuit OP1 is stabilized in a state where the current flowing through the transistor QP16 and the current flowing through the transistor QP17 are equal. In order for these currents to be equal, the gate voltage of the transistor QP16 and the gate voltage of the transistor QP17 must be equal. In other words, the gate voltage of transistor QP17 must be equal to reference voltage Vref. The gate voltage of the transistor QP17 is equal to the reference voltage Vr.
To control the current flowing through transistor QN13 to be equal to ef, the drain voltage of transistor QP16 is applied to the gate terminal of transistor QN13 via transistors QP3 and QN2.

At the time of holding, SP goes low and SPX goes high, turning off the transistors QP1 and QN1 and turning on the transistor QP2 instead. The gate voltage of the transistor QP15 goes high via the transistor QP2, turning off the transistor QP15 and stopping the current flowing through the transistor QP15. Thereby, the power consumption of the constant voltage output circuit of the first embodiment is reduced.

Since the transistor QP3 and the transistor QN2 are turned off and the gate terminal of the transistor QN13 is separated from the differential circuit OP1, the gate terminal of the transistor QN13 is turned off.
Not affected by 1. The gate terminal of the transistor QN13 is held at a voltage at the time of enable by the phase compensation capacitor CC, and a current having the same magnitude as that at the time of enable flows through QN13. As long as the load on the target circuit does not change significantly, a constant voltage output similar to that during enable can be obtained even during hold.

As described above, according to the first embodiment, the sampling circuit 103 turns on the differential circuit OP1 continuously,
It turns off and turns on and off a signal line for inputting a control signal output from the differential circuit to the output circuit 101 based on on and off of the sampling circuit 103. When this signal line is turned off, a control signal is input. The input terminal of the output circuit 101 for holding the signal line at the signal level before the signal line is turned off,
Since there is no change in the voltage at the input terminal of the output circuit 101,
The power consumption of the constant voltage output circuit itself can be reduced, and the change in the output voltage can be reduced. Furthermore, since the change in the output voltage can be reduced, the output voltage can be brought close to the vicinity of the stop voltage of the target circuit to which power is supplied,
The power consumption of the target circuit can be reduced.

Further, since the holding circuit 105 is constituted by a phase compensating capacitor, the number of components can be reduced by using a phase compensating capacitor generally provided in a constant voltage output circuit.

Embodiment 2 Second Embodiment A constant voltage output circuit according to a second embodiment will be described with reference to FIGS. In addition,
The configuration of the constant voltage output circuit of the second embodiment is the same as that of the first embodiment.
Since the configuration is the same as that of the constant voltage output circuit described above, the same portions are denoted by the same reference numerals as in FIGS. 2 and 3 and the description thereof is omitted, and only different portions will be described.

FIG. 5 is a schematic circuit diagram showing a configuration of the constant voltage output circuit according to the second embodiment. The constant voltage output circuit according to the second embodiment includes a constant current source 501 as a load circuit instead of the resistors R1 and R2. The constant current source 501 is connected to the sampling circuit 103, and the sampling circuit 103 turns on and off the constant current source 501 as a load circuit together with the differential circuit. Here, the output voltage VREG
Is determined by the following equation. VREG = Vref

FIG. 6 is a circuit diagram showing a configuration of the constant voltage output circuit according to the second embodiment. In the constant voltage output circuit of the second embodiment, transistors QP22, QP21, QN2
1 and QP25 constitute a constant current source 501.

The operation of the second embodiment in the above configuration will be described. Since the operation of the second embodiment is the same as the operation of the first embodiment, the description of the same portions will be omitted, and only different portions will be described.

When enabled, SP is high level, SPX
Goes low, and the transistors QP21 and QN
21 turns on, and transistors QP11 and QP25 form a current mirror circuit. A current determined by the characteristics of the transistor QP11 flows through the transistor QP25.

At the time of hold, SP goes low, SPX goes high, and the transistors QP21 and QN2
1 turns off and the transistor QP22 turns on instead. The gate voltage of transistor QP25 attains a high level via transistor QP22,
25 is turned off, and the current flowing through the transistor QP25 stops. Thereby, the power consumption of the constant voltage output circuit according to the second embodiment is further reduced.

As described above, according to the second embodiment, since the sampling circuit 103 turns on and off the load circuit together with the differential circuit, the power consumption of the constant voltage output circuit itself can be further reduced.

The feedback circuit 102 may be of any type, for example, as shown in FIGS. 7 and 8, and the sampling circuit 103 further generates a reference voltage Vref. The circuit to be turned on and off may be turned on and off.

[0037]

As described above, in the constant voltage output circuit according to the present invention, the sampling circuit continuously turns on and off the feedback circuit, and outputs the control signal output from the feedback circuit to the output circuit. A signal line for inputting the signal is turned on and off based on the sampling circuit, and when the signal line is turned off, the input terminal of the output circuit for inputting the control signal is turned off. Since the signal level is maintained at the same level as before and the voltage at the input terminal of the output circuit does not change, the power consumption of the constant voltage output circuit itself and the change in the output voltage can be reduced.

Further, in the constant voltage output circuit according to the present invention, the sampling circuit continuously turns on the differential circuit.
Since it is turned off, the power consumption of the constant voltage output circuit itself can be reduced.

In the constant voltage output circuit according to the present invention, the sampling circuit continuously turns on the differential circuit.
Since the load circuit is turned off and the load circuit is continuously turned on and off, the power consumption of the constant voltage output circuit itself can be further reduced.

In the constant voltage output circuit according to the present invention, the holding circuit is constituted by a phase compensating capacitor. By using a capacitor, the number of components can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a constant voltage output circuit according to a first embodiment.

FIG. 2 is a schematic circuit diagram showing a configuration of a constant voltage output circuit according to the first embodiment.

FIG. 3 is a circuit diagram showing a configuration of a constant voltage output circuit according to the first embodiment.

FIG. 4 is a timing chart of signals SP and SPX output from the sampling circuit of the first embodiment.

FIG. 5 is a schematic circuit diagram showing a configuration of a constant voltage output circuit according to a second embodiment.

FIG. 6 is a circuit diagram showing a configuration of a constant voltage output circuit according to a second embodiment.

FIG. 7 is a schematic circuit diagram showing another configuration of the constant voltage output circuit of the second embodiment.

FIG. 8 is a circuit diagram showing another configuration of the constant voltage output circuit according to the second embodiment.

[Explanation of symbols]

 Reference Signs List 101 output circuit 102 feedback circuit 103 sampling circuit 104 switch 105 holding circuit

Claims (4)

[Claims] 1. A constant voltage output circuit for supplying power to a target circuit to which power is to be supplied, comprising: an output circuit for supplying power to the target circuit; and a feedback input of an output of the output circuit; A feedback circuit that outputs a control signal for controlling an output; a sampling circuit that continuously turns on and off the feedback circuit; and a control circuit that is provided on a signal line for inputting a control signal output from the feedback circuit to the output circuit. A switch for turning on and off the signal line based on on and off of the sampling circuit; and a switch provided between the switch and the output circuit, wherein when the signal line is turned off by the switch, A holding circuit for holding an input terminal of the output circuit for inputting a control signal at a signal level before the signal line is turned off. Output circuit. 2. The feedback circuit according to claim 1, wherein the feedback circuit includes a reference voltage generation circuit for generating a reference voltage, a load circuit for the feedback input, and a reference voltage generated by the reference voltage generation circuit and the feedback input. 2. A constant voltage output according to claim 1, further comprising: a differential circuit that receives an output of a load circuit and outputs the control signal, wherein the sampling circuit turns on and off the differential circuit. circuit. 3. The feedback circuit according to claim 1, wherein the feedback circuit includes a reference voltage generation circuit for generating a reference voltage, a load circuit for the feedback input, and the reference voltage generated by the reference voltage generation circuit and the feedback input. 2. A differential circuit that inputs an output of a load circuit and outputs the control signal, wherein the sampling circuit turns on and off the differential circuit and the load circuit. Constant voltage output circuit. 4. The constant voltage output circuit according to claim 1, wherein said holding circuit is constituted by a phase compensation capacitor.