JP4435197B2 - 半導体集積回路 - Google Patents
半導体集積回路 Download PDFInfo
- Publication number
- JP4435197B2 JP4435197B2 JP2007087862A JP2007087862A JP4435197B2 JP 4435197 B2 JP4435197 B2 JP 4435197B2 JP 2007087862 A JP2007087862 A JP 2007087862A JP 2007087862 A JP2007087862 A JP 2007087862A JP 4435197 B2 JP4435197 B2 JP 4435197B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- converter
- test signal
- test
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
- H03M1/108—Converters having special provisions for facilitating access for testing purposes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
- H03M1/1095—Measuring or testing for ac performance, i.e. dynamic testing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Tests Of Electronic Circuits (AREA)
Description
図1は、本発明の第1の実施形態にしたがった半導体集積回路の構成例(要部)を示すものである。なお、ここでは、IEEEが定めた無線LAN通信の規格「802.11a」に準拠したBB−LSIを例に、その送受信部に搭載されたDACおよびADCの良品選別動作について説明する。
図3は、本発明の第2の実施形態にしたがった半導体集積回路の構成例(要部)を示すものである。ここでは、IEEEが定めた無線LAN通信の規格「802.11a」に準拠したBB−LSIを例に説明する。また、本実施形態においては、応答信号(ループバック信号)に対する自己相関演算結果とその期待値との直交性から、BB−LSIの送受信部に搭載されたDACおよびADCの良品選別を行うようにした場合について説明する。なお、図1と同一部分には同一符号を付して、詳しい説明は割愛する。
図5(a)は、BB−LSIでプレアンブル(スタンダード)な波形の信号をテスト信号とした場合の例である。このテスト信号は、たとえば40MHzごとの離散値32サンプルで構成される、800nsを1周期とする信号で、テスト信号生成部より連続的に繰り返し送出されるものとする。また、その波形は、1.25MHz,2.5MHz,3.75MHz,5MHz,6.25MHz,7.5MHzの各周波数成分を適当な位相で等利得に合成したものである。
Claims (3)
- テスト時に、テスト信号を発生する信号生成部と、
前記信号生成部で発生された前記テスト信号をアナログ信号に変換するデジタル−アナログ変換器と、
テスト時に、前記デジタル−アナログ変換器より出力される信号を取り込んで、デジタル信号に変換するアナログ−デジタル変換器と、
前記アナログ−デジタル変換器より出力される信号の自己相関演算を行う演算部と、
前記演算部での自己相関演算結果と所定の参照信号との直交性を評価する評価部と
を具備したことを特徴とする半導体集積回路。 - 前記テスト信号は該テスト信号の自己相関関数が該テスト信号と直交するように設計された信号であり、
前記所定の参照信号は、前記デジタル−アナログ変換器および前記アナログ−デジタル変換器が理想的に動作した場合の、前記自己相関演算結果の期待値であることを特徴とする請求項1に記載の半導体集積回路。 - 前記所定の参照信号は、それぞれ、前記テスト信号をもとに生成されることを特徴とする請求項1に記載の半導体集積回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007087862A JP4435197B2 (ja) | 2007-03-29 | 2007-03-29 | 半導体集積回路 |
US12/056,976 US7633416B2 (en) | 2007-03-29 | 2008-03-27 | Semiconductor integrated circuit capable of screening conforming digital-analog converters and analog-digital converters to be mounted by auto-correlation arithmetic operation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007087862A JP4435197B2 (ja) | 2007-03-29 | 2007-03-29 | 半導体集積回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008252235A JP2008252235A (ja) | 2008-10-16 |
JP4435197B2 true JP4435197B2 (ja) | 2010-03-17 |
Family
ID=39793362
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007087862A Expired - Fee Related JP4435197B2 (ja) | 2007-03-29 | 2007-03-29 | 半導体集積回路 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7633416B2 (ja) |
JP (1) | JP4435197B2 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4966329B2 (ja) * | 2009-03-19 | 2012-07-04 | 株式会社東芝 | 無線受信機の消費電力制御方法 |
WO2013085506A1 (en) * | 2011-12-07 | 2013-06-13 | Intel Corporation | Apparatus, systems and methods for for digital testing of adc/dac combination |
US9157939B2 (en) * | 2012-08-09 | 2015-10-13 | Infineon Technologies Ag | System and device for determining electric voltages |
US10474553B2 (en) * | 2017-07-18 | 2019-11-12 | Nxp Usa, Inc. | Built-in self test for A/D converter |
US10581447B1 (en) * | 2018-09-28 | 2020-03-03 | Apple Inc. | Method and apparatus for measuring phase response |
US20240063810A1 (en) * | 2022-08-17 | 2024-02-22 | International Business Machines Corporation | Automated waveform validation |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4419656A (en) * | 1980-11-07 | 1983-12-06 | Fairchild Camera & Instrument Corp. | Method and apparatus for digital converter testing |
JPS57119259A (en) | 1981-01-19 | 1982-07-24 | Hitachi Ltd | Testing method for a/d converter |
JPS63169123A (ja) | 1987-01-06 | 1988-07-13 | Fujitsu Ltd | 雑音量測定装置 |
US6326909B1 (en) | 1997-09-18 | 2001-12-04 | Advantest Corporation | Evaluation system for analog-digital or digital-analog converter |
US6667702B2 (en) * | 2001-04-27 | 2003-12-23 | Rohm Co., Ltd | Semiconductor device having DACs and method of testing such semiconductor device |
JP2004048383A (ja) | 2002-07-11 | 2004-02-12 | Renesas Technology Corp | 送受信システムおよび通信用半導体集積回路並びにテスト方法 |
US7035756B2 (en) * | 2003-12-17 | 2006-04-25 | Texas Instruments Incorporated | Continuous digital background calibration in pipelined ADC architecture |
US7129879B1 (en) * | 2005-07-12 | 2006-10-31 | Analog Devices, Inc. | Method of and apparatus for characterizing an analog to digital converter |
-
2007
- 2007-03-29 JP JP2007087862A patent/JP4435197B2/ja not_active Expired - Fee Related
-
2008
- 2008-03-27 US US12/056,976 patent/US7633416B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20080238741A1 (en) | 2008-10-02 |
US7633416B2 (en) | 2009-12-15 |
JP2008252235A (ja) | 2008-10-16 |
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