JP4432197B2 - Multistage level shift circuit and semiconductor device using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
In a semiconductor integrated circuit in which multiple power supplies are mixed, the present invention has different specifications in a circuit that converts signals between different power supplies, particularly when a potential difference between different power supply systems is large, for example, in a gate array semiconductor device or a master slice semiconductor device. The present invention relates to a configuration of a multistage level shift circuit and a semiconductor device which can be easily handled.
[0002]
[Prior art]
A typical circuit of a conventional level shift circuit is shown in FIGS. FIG. 5 is a circuit diagram of West German Patent Publication 2154877 (DE, A), and FIG. 6 is a circuit diagram of Japanese Patent Laid-Open No. 57-59690. 5 and 6 both have the power supply voltage E₁System power supply voltage E₂It is configured to convert to a system signal. Japanese Patent Laid-Open No. 02-089345 discloses an example in which a level shift circuit is mounted on an input / output circuit cell in a gate array corresponding to various specifications in a wiring process. In addition, by devising the basic cell transistors in the gate array by using the wirings in series and parallel, the conductance of each of the P and N insulated gate field effect transistors (hereinafter abbreviated as MOSFETs) equivalent to the specifications is equivalently required. An example of creating β and β ratio as constants is shown in FIG.
[0003]
[Problems to be solved by the invention]
Now, the conventional circuit described above is E₁And E₂This circuit is practical when the potential difference is not so large. However, E₁And E₂As the potential difference increases, β-type MOSFET β_PAnd β of N-type MOSFET_NIt is necessary to take a very large ratio, and there are problems that the operation is extremely reduced, the current consumption is increased, and the layout shape is unreasonable. In particular, in recent years, elements such as MOSFETs used in integrated circuits have been miniaturized, the withstand voltage has been reduced, and it has become unavoidable to use low-voltage power supplies. In addition, as the demand for low power consumption and low voltage for portable devices is increasing, the internal circuit is operated at a low voltage, and the above-described E₁And E₂There is a need for a level shift circuit with good characteristics even when the potential difference is large.
[0004]
In addition, a level shift circuit for converting signals between different power supply systems is also required for semiconductor devices corresponding to various specifications by changing only a wiring layer such as a gate array. In the case of a custom-designed model that uniquely corresponds to each specification, the shape of the MOSFET and the β ratio between P and N types can be freely designed according to the required specifications. However, for gate arrays and the like, Japanese Patent Laid-Open No. 02-089345 However, even if a dedicated level shift circuit is built in, if the specifications change, the characteristics of the optimum level shift change accordingly, so that there is a problem that many different specifications cannot be accommodated.
[0005]
In addition, the method of ensuring the equivalently required β ratio of the conventional circuit in FIGS. 5 and 6 by using the MOSFETs in the basic cell in series or in parallel in the gate array is a low voltage and the potential difference between the conversions. Is very large, an enormous number of MOSFETs are required, which is undesirable in terms of layout and other electrical characteristics.
[0006]
Therefore, the present invention solves such a problem, and the object of the present invention is that the response speed is fast and the current consumption is small even when the voltage is lowered or the potential difference between different power supply systems is very large. An object of the present invention is to provide a multistage level shift circuit that can be easily laid out.
[0007]
Also, it is possible to provide a semiconductor device that can easily cope with a case where a number of level shift circuits having different specifications have to be configured by combining the same cell and the same shape MOSFET wiring layer, such as a gate array device. With the goal.
[0008]
[Means for Solving the Problems]
  The multi-stage level shift circuit according to the present invention includes a first power source having a first potential having a first polarity, a second power source having a second potential having a first polarity, and a third power source having a second polarity. A multi-stage level shift circuit having an input signal terminal and an inverting input signal terminal, an output signal terminal and an inverting output signal terminal, and a low voltage system input signal as the input signal terminal and the inverting input signal terminal. And has a level conversion function to output to the output signal terminal and the inverted output signal terminal as a high voltage signal, and an insulated gate field effect transistor (hereinafter abbreviated as a MOSFET). N (N is a combination of3(Integer above) basic level shift circuits,A first (N-1) th MOS diode power supply circuit, and an Mth (1≤M≤N-1) MOS of the first to (N-1) th MOS diode power supply circuits. The diode power supply circuitMOS diode in which gate electrode and drain electrode of MOSFET of first polarity are connected to each other(N−M) pieces are connected in series,On the power supply side of the first basic level shift circuit of the N basic level shift circuits,First MOS diode power supply circuitAnd the signal of the first power supply system is connected to the input signal terminalIsThe inverted input signal terminal is connected to the inverted signal of the signal, and the power supply side of the Kth (2 ≦ K ≦ N−1) basic level shift circuit is connected to the inverted input signal terminal.Kth MOS diode power supply circuitAre connected, the output signal terminal of the (K-1) th basic level shift circuit is connected to the input signal terminal, and the inverted output signal of the (K-1) th basic level shift circuit is connected to the inverted input signal terminal. A second power supply is connected to the power supply side of the Nth basic level shift circuit, an output signal terminal of the (N-1) th basic level shift circuit is connected to the input signal terminal, The inverted output signal terminal of the (N-1) th basic level shift circuit is connected to the inverted input signal terminal, and the output signal terminal and the inverted output signal terminal of the Nth basic level shift circuit are respectively the final output signals. Terminal and inverted output signal terminal.
[0009]
  In other words, a power supply with a moderate voltage drop from a plurality of basic level shift circuits and a MOS diode power supply circuit in which MOS diodes are connected in series is prepared. A slightly higher output signal is produced with a lower power supply voltage. Similarly, a plurality of basic level shift circuits, each of which is supplied with a power supply voltage little by little from the MOS diode power supply circuit in order, level conversion gradually becomes impossible while repeating this.LineIn the end, a high voltage output signal is produced.
[0011]
Further, the product of the number N of the basic level shift circuits used and the threshold voltage of the first polarity MOSFET used for the basic level shift circuit and the MOS diode is the potential of the second power supply and the first power supply. The configuration may be larger than the potential difference.
[0012]
In addition, the basic level shift circuit and the MOS diode power supply circuit use P-type or N-type MOSFETs configured with the same basic cell size incorporated in a gate array semiconductor device or a master slice semiconductor device. You may comprise as a semiconductor device characterized by being implement | achieved.
[Action]
According to the above configuration of the present invention, the basic level shift circuit is used with a power supply having a moderate voltage drop, and the conversion is performed in a range in which the P and N MOSFETs do not compete during the conversion operation of the basic level shift circuit. Since this unreasonable conversion is repeatedly performed to obtain a signal of the final target output voltage, the operation is quickly performed in this conversion process, and since there is no competing short-circuit current, current consumption is small.
[0013]
Also, since the P and N MOSFETs do not compete during the conversion operation of the basic level shift circuit with the above-described configuration, the shape of the MOSFET transistors that affect the driving capability is substantially irrelevant. Therefore, even if the same MOSFET is combined in the basic cell of the gate array device, the conversion operation is performed without any trouble.
[0014]
  There are also various specifications between the voltage systems to be converted.TsuHowever, it is only necessary to change the number of stages, which is the number of basic level shift circuits, and the number of MOS diodes in series in the MOS diode power supply circuit. it can.
[0015]
Further, as described above, since there is no unreasonable circuit operation, the specification is such that the potential difference between conversions is low and the voltage is very large, and the semiconductor device is composed of MOSFETs of basic cells in the master slice or gate array. Even in this case, it can be realized with a reasonable number of MOSFETs.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, details of the present invention will be described by way of examples. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, reference numerals 101, 102, 103, and 104 surrounded by an alternate long and short dash line are basic level shift circuits. Since these basic level shift circuits play an important and basic role in the present invention, they will be described first. FIG. 2 is an enlarged circuit diagram showing only these basic level shift circuits. The circuit of FIG. 2 is also used in FIG. 6 shown in the prior art and is a well-known level shift circuit. The configuration and operation will be briefly described below. In FIG. 2, the source electrode of the P-type MOSFET 201 is a positive power source V.₂The drain electrode is connected to the source electrode of the P-type MOSFET 202. The drain electrode of the P-type MOSFET 202 and the drain electrode of the N-type MOSFET 203 are connected to each other as an inverted output signal terminal 210. The source electrode of the N-type MOSFET 203 is connected to a negative power source 212 (0 potential). The source electrode of the P-type MOSFET 204 is a positive power source V₂The drain electrode is connected to the source electrode of the P-type MOSFET 205. The drain electrode of the P-type MOSFET 205 and the drain electrode of the N-type MOSFET 206 are connected to each other as an output signal terminal 209. The source electrode of the N-type MOSFET 206 is connected to the negative power source 212. The gate electrode of the P-type MOSFET 202 and the gate electrode of the N-type MOSFET 203 are connected to each other and connected to the input signal terminal 207. The gate electrode of the P-type MOSFET 205 and the gate electrode of the N-type MOSFET 206 are connected to each other and connected to the inverting input signal terminal 208. The gate electrode of the P-type MOSFET 201 is connected to the output signal terminal 209, and the gate electrode of the P-type MOSFET 204 is connected to the inverted output signal terminal 210.
[0017]
Now, the input signal terminal 207 and its inverted signal inverting input signal terminal 208 are V₁The output signal terminal 209 and the inverted output signal terminal 210 have V₂The system potential is output. Initially, the input signal terminal 207 is 0 (Low) and the inverted input signal terminal 208 is V₁(High), the output signal terminal 209 has a potential of 0, and the inverted output signal terminal 210 has a potential of V₂Potential. Next, the input signal terminal 207 is V₁(High) If the inverting input signal terminal 208 is changed to 0 (Low), the source potential of the P-type MOSFET 202 is approximately V.₂The gate potential is V₁It becomes. At this time, the threshold voltage of the P-type MOSFET is set to V_TPgiven that,
V₂-V₁-V_TP<0
Is off (OFF),
V₂-V₁-V_TP> 0
If it is, it will be in a weak ON state. In any case, the situation is closer to OFF than when the gate potential was initially zero. The N-type MOSFET 203 is turned on. Further, the P-type MOSFET 205 is turned on and the N-type MOSFET 206 is turned off. Therefore, if the N-type MOSFET 203 exceeds the driving capability of the P-type MOSFET 202, the inverted output signal terminal 210 approaches the low potential, so that the P-type MOSFET 204 is turned on, and the P-type MOSFET 205 is connected to the V-type MOSFET 205.₂The power supply potential of the system is supplied, and the output signal terminal 209 is V₂V potential is applied to the gate electrode of the P-type MOSFET 201 as well as the potential.₂Is supplied, and the P-type MOSFET 201 is turned off. Therefore, the output signal terminal 209 is V₂And the inverted output signal terminal 210 are finally stabilized at 0 potential. Furthermore, the input signal terminal is again 0 (Low), and the inverted input signal terminal 208 is V₁(High), the same thing happens when the P-type MOSFET 204 is replaced with the 201, the P-type MOSFET 205 is replaced with the 202, and the N-type MOSFET 206 is replaced with the N-type MOSFET 203. Finally, the output signal terminal 209 is at the 0 potential and the inverted output. Signal terminal 210 is V₂Eventually stabilizes at potential. From the above, V₁From the input signal of the system, V₂Converted to the output signal of the system.
[0018]
Returning to FIG. In FIG. 1, reference numeral 116 denotes a positive power source, which is a first potential E.₁have. Reference numeral 117 denotes a positive power source and a second potential E.₂have. Where E₂> E₁It is. Reference numeral 118 is a negative power source and serves as a common ground. Reference numerals 101, 102, 103, and 104 surrounded by a one-dot chain line are basic level shift circuits as described above. Reference numeral 105 surrounded by an alternate long and short dash line is a MOS diode power supply circuit, and P-type MOSFETs 106, 107, 108 are connected to a gate electrode and a drain electrode, respectively, constitute a MOS diode, and are connected in series. It serves to supply a potential that has caused a voltage drop that is an integral multiple of the voltage. 111 is E₁An inverting input signal is generated by a CMOS inverter circuit composed of a P-type MOSFET 109 and an N-type MOSFET 110 at an input signal terminal of the system.
[0019]
The basic level shift circuit 101 uses a negative power supply 118 and the output of the drain electrode of the P-type MOSFET 108 of the MOS diode power supply circuit 105 as a positive power supply. The input signal terminal 112 has E described above.₁The input signal terminal 111 of the system is connected, and the output of the CMOS inverter circuit composed of the P-type MOSFET 109 and the N-type MOSFET 110 is connected to the inverted input signal terminal 113.
[0020]
The basic level shift circuit 102 uses the output of the negative electrode power supply 118 and the drain electrode of the P-type MOSFET 107 of the MOS diode power supply circuit 105 as the positive power supply. The output signal terminal and the inverted output signal terminal of the basic level shift circuit 101 are connected to the input signal terminal and the inverted input signal terminal of the basic level shift circuit 102, respectively.
[0021]
The basic level shift circuit 103 uses the output of the negative electrode power supply 118 and the drain electrode of the P-type MOSFET 106 of the MOS diode power supply circuit 105 as a positive power supply. The output signal terminal and the inverted output signal terminal of the basic level shift circuit 102 are connected to the input signal terminal and the inverted input signal terminal of the basic level shift circuit 103, respectively.
[0022]
The basic level shift circuit 104 includes a negative power source 118 and a second potential E.₂Is the power source for the positive electrode. The output signal terminal and the inverted output signal terminal of the basic level shift circuit 103 are connected to the input signal terminal and the inverted input signal terminal of the basic level shift circuit 104, respectively. The output signal terminal 114 and the inverted output signal terminal 115 of the basic level shift circuit 104 are an output signal terminal and an inverted output signal terminal as the multistage level shift circuit of the present invention.
[0023]
With the above configuration, 0 and E₁E operating between two voltages₁The system signal passes through the basic level shift circuits 101, 102, 103, 104, and gradually increases the voltage of the output signal.₂To a signal that operates between the two voltages. In this case, the product of the number of basic level shift circuits used and the threshold voltage of the first polarity MOSFET used in the basic level shift circuit and the MOS diode is equal to the potential of the second power supply and the first voltage. It is larger than the potential difference of one power source.
[0024]
In order to make the functions and effects of the above circuits easier to understand, actual numerical examples are shown below.
[0025]
The power supply voltage on the low voltage side is E₁= 0.9 [V], the power supply voltage on the high voltage side is E₂= 3.0 [V], the threshold voltages of the P-type and N-type MOSFETs are V_TP, V_TNAs V_TP= 0.6 [V], V_TN= 0.6 [V]. Then, the voltage drop due to the three stages of the MOS diodes of the P-type MOSFETs 106, 107 and 108 becomes 1.8 [V] (0.6 × 3), so the power supply potential of the positive electrode of the basic level shift circuit 101 is 1.2 [V]. ] (3.0-1.8). Therefore, when 0.9 [V], which is a high signal, is applied to the input signal terminal 112, the gate of the P-type MOSFET corresponding to the P-type MOSFET 202 of FIG. Because it becomes 2 [V]
V_GS-V_TH= (1.2-0.9) -0.6 <0
It has become. Therefore, the P-type MOSFET corresponding to the P-type MOSFET 202 is unconditionally turned off. This is an effect of reducing the source potential (1.2 [V]) because the gate potential is low (0.9 [V]). Of course, at this time, the N-type MOSFET corresponding to the N-type MOSFET 203 has a source electrode of 0 potential, a gate potential of 0.9 [V], and V_TN= 0.6 [V]
V_GS-V_TH= (0.9-0) -0.6> 0
It turns on unconditionally. Therefore, the P-type MOSFET and the N-type MOSFET do not compete with each other, and the output signal changes according to the change of the input signal without difficulty. Then, 1.2 [V] or 0 [V] is output to the output signal terminal and the inverted output signal terminal.
[0026]
Next, regarding the basic level shift circuit 102, the voltage drop due to the two stages of the MOS diodes of the P-type MOSFETs 106 and 107 is 1.2 [V] (0.6 × 2). Is 1.8 [V] (3.0-1.2). Therefore, when 1.2 [V], which is the output signal of the basic level shift circuit 101, is added to the input signal terminal, the gate of the P-type MOSFET corresponding to the P-type MOSFET 202 of FIG. ], The source electrode is almost 1.8 [V]
V_GS-V_TH= (1.8-1.2) -0.6 ≦ 0
It has become. Therefore, the P-type MOSFET corresponding to the P-type MOSFET 202 is turned off. Of course, the N-type MOSFET corresponding to the N-type MOSFET 203 is turned on unconditionally because the source electrode is 0 potential and the gate potential is 1.2 [V]. Therefore, without competing between the P-type MOSFET and the N-type MOSFET, the input signal of 1.2 [V] system is converted into the output signal of 1.8 [V] system without difficulty.
[0027]
Next, regarding the basic level shift circuit 103, the voltage drop due to one stage of the MOS diode of the P-type MOSFET 106 is 0.6 [V] (0.6 × 1). The potential is 2.4 [V] (3.0-0.6). Therefore, when 1.8 [V], which is a high signal of the output signal of the basic level shift circuit 102, is added to the input signal terminal, the gate of the P-type MOSFET corresponding to the P-type MOSFET 202 of FIG. ], The source electrode is almost 2.4 [V]
V_GS-V_TH= (2.4-1.8) -0.6 ≦ 0
It has become. Therefore, the P-type MOSFET corresponding to the P-type MOSFET 202 is turned off. Of course, the N-type MOSFET corresponding to the N-type MOSFET 203 is turned on unconditionally because the source electrode is 0 potential and the gate potential is 1.8 [V]. Therefore, without competing between the P-type MOSFET and the N-type MOSFET, the input signal of 1.8 [V] system is converted into the output signal of 2.4 [V] system without difficulty.
[0028]
Next, regarding the basic level shift circuit 104, 3.0 [V] is applied to the positive electrode of the basic level shift circuit 104. Therefore, when 2.4 [V], which is the output signal of the basic level shift circuit 103, is added to the input signal terminal, the gate of the P-type MOSFET corresponding to the P-type MOSFET 202 of FIG. ] Since the source electrode is 3.0 [V]
V_GS-V_TH= (3.0-2.4) -0.6 ≦ 0
It has become. Therefore, the corresponding P-type MOSFET 202 is turned off. Of course, the N-type MOSFET corresponding to the N-type MOSFET 203 is turned on unconditionally because the source electrode is 0 potential and the gate potential is 2.4 [V]. Therefore, a 2.4 [V] system input signal is converted into a 3.0 [V] system output signal without difficulty without competition between the P-type MOSFET and the N-type MOSFET.
[0029]
In the above circuit, the conventional level shift circuit is designed such that the P-type MOSFET 202 and the N-type MOSFET 203 compete with each other, whereas the P-type MOSFET and the N-type MOSFET perform conversion operation without competition. In this way, the output voltage of the desired voltage is created by decreasing the voltage on the positive electrode side, increasing the number of stages, and repeating the conversion. As a result, high speed and low current consumption are achieved. This effect can be achieved with the conventional circuit shown in FIG. 6 or FIG.₁Next, a case where the voltage is increased from 0.9 [V] to 3.0 [V] at a stretch will be compared. For simplicity, the P-type MOSFETs 201, 202, 204, and 205 in FIG._PAnd threshold voltage V_TPSuppose you have The N-type MOSFETs 203 and 206 all have the same conductance constant β._NAnd threshold voltage V_TNSuppose you have At this time, the problem in operation is that the input signal terminal 207 changes from Low (0) to High (E₁= 0.9 [V]), the N-type MOSFET 203 is of course turned on, but the P-type MOSFET 202 is
V_GS-V_TH= (3.0-0.9) -0.6> 0
Because it is, it is not turned off. At this time, a situation occurs in which the P-type MOSFET and the N-type MOSFET compete with each other. Consider this contention as a comparison of the difference in driving capability between the N-type and P-type MOSFETs in the initial state when the signal changes. At this time, since the N-type MOSFET 203 operates in the saturation region, the equivalent resistance R_N1Is
R_N1= 2E₂/ Β_N(E₁-V_TN)²
Since the P-type MOSFET 202 operates in the unsaturated region, the equivalent resistance R_P2Is
R_P2= 1 / β_P(E₂-E₁-V_TP)
It becomes. Here, (E₂-E₁-V_TP) = (3.0−0.9−0.6)> 0
It is. Further, since the P-type MOSFET 201 operates in the unsaturated region, the equivalent resistance R_P3Is
R_P3= 1 / β_P(E₂-0-V_TP) = 1 / β_P(E₂-V_TP)
It is expressed. Here, the limit of whether or not the level shift circuit normally operates is generally quite difficult, but here, it is simplified and a guide for evaluation is compared between the drive characteristics of the N-type MOSFET and the P-type MOSFET. However, we compare it by replacing it with an equivalent resistance that is inversely proportional to the driving ability. The limit judgment formula is considered as follows.
[0030]
R_N1 <R_P2+ R_P3
If the above relational expression is substituted,
A = 2E₂(E₂-E₁-V_TP) ・ (E₂-V_TP)
B = (E₁-V_TN)²・ {2 (E₂-V_TP-E₁}
Anyway
β_N/ Β_P  > A / B
This is a limit judgment formula as to whether or not the level shift circuit operates normally.
[0031]
Now, E₁= 0.9 [V], E₂= 3.0 [V], V_TP= 0.6 [V], V_TN= 0.6 [V]
β_N/ Β_P  > 61.5
It becomes. In manufacturing, the threshold voltage usually varies about 0.1 [V].
E₁= 0.9 [V], E₂= 3.0 [V], V_TP= 0.7 [V], V_TN= 0.7 [V]
β_N/ Β_P  > 130.5
It also becomes. Since the β ratio between the normal N-type MOSFET and the P-type MOSFET is about 3, in order to achieve the above β-ratio, the shape is changed about 20 to 40 times between the P-type MOSFET and the N-type MOSFET, It is necessary to make a difference in driving ability. Originally, when configuring a CMOS circuit, it is desirable for the characteristics of high-speed response and low current consumption that the P-type MOSFET and the N-type MOSFET are balanced in driving capability. Therefore, although the shape can be secured by custom design or the like in which the shape of the MOSFET can be freely designed, if the β ratio is unbalanced as described above, the responsiveness and current consumption characteristics are adversely affected. Further, in the case of achieving the above-mentioned abnormal β ratio in the case of the gate array by connecting the P-type MOSFETs in series as shown in FIG. 7, 20 parts of the P-type MOSFETs are provided in each part 701, 702, 704, 705 of FIG. It means that ~ 40 pieces are necessary. Therefore, in the system shown in FIG. 7, series connection is required at four locations, so that 80 to 160 P-type MOSFETs and three N-type MOSFETs are required. On the other hand, the circuit system of FIG. 1 according to the present invention achieves this with 20 P-type MOSFETs and 9 N-type MOSFETs. Therefore, it can be understood that the circuit system of the present invention can be achieved with an overwhelmingly smaller number of MOSFETs than the conventional system in order to realize the level shift circuit of this example specification by the gate array system. Further, the conventional method of FIG. 7 not only requires a large number of MOSFETs, but also causes competition in the transition period of signal transition. Therefore, the circuit system of the present invention has better response and low current consumption characteristics. Further, since competition does not occur in the present invention, it can be seen that the circuit has stable characteristics and is resistant to manufacturing variations.
[0032]
FIG. 3 is a circuit diagram showing a second embodiment of the present invention. 2 is different from FIG. 1 in the configuration of a MOS diode power supply circuit 305 surrounded by an alternate long and short dash line. In FIG. 1, the power supply of each basic level shift circuit is taken out from three MOS diode circuits connected in series. However, in FIG. 3, serial MOS diodes 318, 319, and 320 having different numbers of stages are provided separately. The power supply potential is separately supplied to the level shift circuit. Although the number of MOSFETs is slightly increased, the circuit system of FIG. 3 is an effective circuit system for pursuing faster response because the current supply capability as a MOS diode power supply circuit is increased.
[0033]
FIG. 4 is a circuit diagram showing a third embodiment of the present invention. 3 is different from FIG. 1 in the polarity on the multi-power supply side. Therefore, the configurations of the P-type MOSFET and the N-type MOSFET are opposite to those in FIG. Although the configuration is reversed, the operation principle and effect are the same.
In the embodiment of FIG. 1, the case of performing the same thing in the conventional circuit is shown as a numerical example. However, if the same thing is performed in FIG. 4 as the conventional example, the conventional level shift circuit operates normally. Considering the limit judgment formula of whether or not
-E₁= -0.9 [V], -E₂= -3.0 [V], V_TP= 0.6 [V], V_TN= 0.6 [V]
β_P/ Β_N  > 61.5
It becomes. In manufacturing, the threshold voltage usually varies about 0.1 [V], so if the worst condition is considered,
-E₁= -0.9 [V], -E₂= -3.0 [V], V_TP= 0.7 [V], V_TN= 0.7 [V]
β_P/ Β_N  > 130.5
It is. Here, the numerical value on the right side of the inequality is the same as in the calculation example of FIG._PAnd β_NThe relationship between the denominator and the numerator is interchanged. As described above, the β ratio between the normal N-type MOSFET and the P-type MOSFET having the same shape is about 3. In this case, in order to achieve the above β ratio, the P-type MOSFET and the N-type MOSFET are 180 to 360. It is necessary to make a difference in driving ability by changing the shape about twice, and the disparity widens. Therefore, it can be seen that the present invention is more effective when the signal voltage to be converted is negative as shown in FIG.
[0034]
1, 3, and 4 exemplify four basic level shift circuits, depending on the specification, the number of stages may be 3 or less, or 5 or more may be desirable.
[0035]
1, 3, and 4 show examples using the basic level shift circuit of FIG. 2, but the essence of the present invention is to repeatedly convert between the unreasonable voltages. The configuration is not necessarily related to FIG. As shown in FIG. 5 for the conventional example, the basic level shift circuit has many other circuits and is effective.
[0036]
1, 3, and 4, E₁Although an inverter circuit that generates an inverted signal of the input signal terminal 111 of the system is shown, it is not always necessary when the input signal and its inverted signal are originally supplied in a pair.
[0037]
Further, in the embodiment of FIG. 1, a case has been described in which there is no complete competition at the time of signal transition, but if there is a moderate voltage drop by the circuit-type MOS diode power supply circuit of the present invention, there will be some competition. Even if this happens, much better characteristics than the conventional circuit can be expected.
[0038]
1, 3, and 4, the MOS diode power supply circuit is configured by connecting MOS diode circuits with MOSFETs having gates and drains connected in series in multiple stages, and a method of causing a voltage drop is employed. Since the essence of the function of the MOS diode power supply circuit is to reduce the voltage appropriately, other MOSFET combinations are possible. Moreover, you may implement | achieve by a resistance means.
[0039]
In addition, since the embodiments of FIGS. 1, 3 and 4 describe the case where no competition occurs completely, the present invention can be applied to an existing gate array irrespective of the shape of the MOSFET.
[0040]
【The invention's effect】
As described above, according to the present invention, there is an effect that it is possible to provide a level shift circuit having a low voltage and a high speed and a low current consumption even when a potential difference to be converted is large.
[0041]
Further, since the circuit configuration does not compete between the P and N MOSFETs during the conversion operation, there is an effect that it can be easily configured even by a combination of existing MOSFETs such as a gate array.
[0042]
Therefore, an existing gate array can incorporate a level shift circuit, and has the effect that it can cope with multiple power supplies.
[0043]
In addition, since the circuit system can be realized with an existing gate array, it is possible to cope with various specifications only by changing the wiring layer.
[0044]
In addition, there is an effect that it is possible to provide a level shift circuit having a very small number of transistors and good characteristics as compared with the case where the gate array is used in the conventional circuit system.
[0045]
In addition, since the circuit configuration does not compete between the P and N MOSFETs during the conversion operation, the operation is stable, and there is an effect that the manufacturing variation is strong.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
FIG. 2 is a circuit diagram of a basic level shift circuit used in the present invention.
FIG. 3 is a circuit diagram showing a second embodiment of the present invention.
FIG. 4 is a circuit diagram showing a third embodiment of the present invention.
FIG. 5 is a circuit diagram of a conventional level shift circuit.
FIG. 6 is a circuit diagram of a conventional level shift circuit.
FIG. 7 is a circuit diagram of a conventional level shift circuit.
[Explanation of symbols]
101, 102, 103, 104, 401, 402, 403, 404 ... basic level shift circuit
105, 305, 318, 319, 320 ... MOS diode power supply circuit
106, 107, 108, 109, 201, 202, 204, 205, 410 ... P-type MOS diode
110, 203, 206, 405, 406, 407, 408, 409 ... N-type MOSFET
111, 112, 207, 411, 413 ... Input signal terminals
113, 208, 412... Inverted input signal terminal
114, 209, 415... Output signal terminal
115, 210, 414 ... Inverted output signal terminal
116, 416 ... first power source
117, 211, 417 ... second power source
118, 212, 418 ... Ground (third power supply)
701, 702, 704, 705 ... P-type MOSFET group connected in series

Claims (3)

A multi-stage level shift circuit having a first power supply having a first potential having a first polarity, a second power supply having a second potential having a first polarity, and a third power supply having a second polarity. ,
It has an input signal terminal and an inverted input signal terminal, and an output signal terminal and an inverted output signal terminal,
Receives a low voltage input signal at the input signal terminal and the inverted input signal terminal, and outputs a high voltage signal to the output signal terminal and the inverted output signal terminal, and has an insulated gate field effect. N (N is an integer of 3 or more) basic level shift circuits composed of combinations of type transistors (Metal Oxide Semiconductor Field Effect Transistor (hereinafter abbreviated as MOSFET));
Comprising first to (N-1) th MOS diode power supply circuits,
Of the first to (N−1) th MOS diode power supply circuits, the Mth (1 ≦ M ≦ N−1) MOS diode power supply circuit includes a gate electrode and a drain electrode of a first polarity MOSFET. MOS diodes (NM) connected to each other are connected in series,
The first MOS level power supply circuit is connected to the power supply side of the first basic level shift circuit of the N basic level shift circuits, and the signal of the first power supply system is connected to the input signal terminal. The inverted signal of the signal is connected to the inverted input signal terminal,
The Kth MOS diode power supply circuit is connected to the power supply side of the Kth (2 ≦ K ≦ N−1) basic level shift circuit, and the (K−1) th basic level shift is connected to the input signal terminal. An output signal terminal of the circuit is connected, and an inverted output signal terminal of the (K-1) th basic level shift circuit is connected to the inverted input signal terminal,
The second power supply is connected to the power supply side of the Nth basic level shift circuit, the output signal terminal of the (N-1) th basic level shift circuit is connected to the input signal terminal, and the inverting input signal terminal is connected to the inverting input signal terminal. Is connected to the inverted output signal terminal of the (N-1) th basic level shift circuit, and the output signal terminal and inverted output signal terminal of the Nth basic level shift circuit are respectively the final output signal terminal and the inverted output signal. A multistage level shift circuit characterized by being a terminal.   2. The multistage level shift circuit according to claim 1, wherein the product of the number N of the basic level shift circuits used and the threshold voltage of the first polarity MOSFET used for the basic level shift circuit and the MOS diode is the first level shift circuit. A multistage level shift circuit characterized by being larger than the difference between the potential of the two power sources and the potential of the first power source.   The basic level shift circuit in the multi-stage level shift circuit according to claim 1 and the MOS diode power supply circuit are P-types configured with the same size of basic cells incorporated in a gate array semiconductor device or a master slice semiconductor device, Alternatively, the semiconductor device is realized using an N-type MOSFET.

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