CN111313887A - Level conversion circuit and corresponding drive circuit - Google Patents
Level conversion circuit and corresponding drive circuit Download PDFInfo
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- CN111313887A CN111313887A CN201811508265.7A CN201811508265A CN111313887A CN 111313887 A CN111313887 A CN 111313887A CN 201811508265 A CN201811508265 A CN 201811508265A CN 111313887 A CN111313887 A CN 111313887A
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Abstract
The invention relates to a level switching circuit and a corresponding driving circuit, wherein the level switching circuit comprises an input module, a positive feedback module, a level switching module and an output module, different logic levels can be converted at high speed through the connection of the four modules, and high-speed matching between the two levels is realized. The level conversion circuit and the corresponding driving circuit can effectively reduce the area of a circuit layout and reduce the circuit cost.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to the technical field of control circuits, and particularly relates to a level conversion circuit and a corresponding driving circuit.
Background
The level shift circuit in the prior art can generally only convert a fixed voltage, and cannot adjust within a certain range along with different working states of the circuit, and the conventional level shift circuit cannot be applied to a bootstrap boosting circuit, and has a slow conversion speed and a small application range.
The following description will be made by taking a general driving circuit as an example:
with the rise of power driving technologies such as modern switching power supplies, inverters, power amplifiers and motor drives, power MOS transistors (Metal-Oxide-Semiconductor) are increasingly commonly used due to their advantages of high input impedance, small driving current, high efficiency, good transconductance linearity, fast switching speed, and the like, and particularly, in some heavy current situations, the power MOS transistors can better exhibit their own advantages in circuits. When the power MOS tube works under the condition of large current, strong interference can be formed instantaneously by a switch, the power MOS tube is generally used for driving inductive loads such as a coil or an inductor, the working environment of the whole circuit system is poor, and strong interference can exist in a power supply or the ground. In general, a power MOS transistor connected to a driving power supply side of a circuit in the circuit is generally referred to as a high-side power transistor, and a power MOS transistor connected to a ground side of the circuit is generally referred to as a low-side power transistor.
If a strong interference exists in the power supply or ground and is transmitted to the grid electrode of the corresponding power MOS tube, the high-side power tube and the low-side power tube can be burnt out due to simultaneous conduction. In addition to the anti-interference measures in the application, in the prior art, a through-preventing structure is usually added to a driving structure of the circuit to prevent the high-side power tube and the low-side power tube from being burned out due to simultaneous conduction. A conventional power transistor driving circuit structure having a shoot-through prevention structure is shown in fig. 1.
In fig. 1, I1 is a nor gate, I3 is a nand gate, I2 and I4 are inverters, MP1 is a high-side power transistor, and MN1 is a low-side power transistor. The input signal HSIN is a high-side input signal and the input signal LSIN is a low-side input signal. When the high-side power transistor MP1 needs to be turned on, the gate thereof is at low level, i.e. the output terminal of I2 is low, this signal is connected to the input terminal of I3, I3 outputs high level, I4 outputs low level, which ensures that the low-side power transistor MN1 is turned off. Similarly, when the low side power transistor MN1 needs to be turned on, the high side power transistor MP1 is guaranteed to be turned off. By adopting the interlocking structure, the power tubes of the high-side power tube MP1 and the low-side power tube MN1 can be effectively prevented from being simultaneously started.
The power tube driving circuit structure with the direct connection prevention structure in the prior art can effectively solve the direct connection phenomenon caused by circuit timing error or abnormal interference, but has the following problems:
the VBRG voltage supplied to the high side power transistor MP1 in the circuit is generally determined by the rated voltage of the load, but in some characteristic situations, such as dc motor driving, the voltage can reach 24v or even higher. In this case, for level matching in the logic control and driving stage in the whole circuit structure, all devices in the circuit structure must be high-voltage devices, and the layout area is usually large in order to increase the withstand voltage. Meanwhile, the high-side power tube is a P-type power tube, so the layout area of the high-side power tube is also large. This makes the overall circuit very costly.
However, if a level conversion module is added to the driving circuit to perform level conversion, the level conversion circuit in the prior art has the problems of limitation in voltage regulation and low conversion efficiency, and cannot be directly used in the driving circuit.
Disclosure of Invention
The present invention is directed to overcome at least one of the above-mentioned disadvantages of the prior art, and provides a level shifter and a driving circuit thereof, which have a wide application range and can adjust an output voltage according to an input voltage in the circuit.
To achieve the above and other objects, a level shifter and a corresponding driving circuit of the present invention are as follows:
the level shift circuit is mainly characterized in that the level shift circuit comprises:
the input module comprises a first input end and a second input end, wherein the first input end of the input module is connected with an external first input voltage, the second input end of the input module is connected with an external second input voltage, the input module is also connected with a third input voltage, and the input module is used for converting the logic level of the first input end of the input module relative to the second input end into the logic level of the first input end of the input module relative to the ground to obtain a voltage after the first level conversion; the first input end of the input module is used as the first input end of the level shift circuit, and the second input end of the input module is used as the second input end of the level shift circuit;
the positive feedback module is connected with the working voltage of the integrated circuit and the third input voltage and used for reducing the level conversion time of the input module;
the level conversion module is connected with the working voltage of the integrated circuit and the third input voltage and is used for converting the voltage range of the third input voltage relative to the ground into the voltage range of the working voltage of the integrated circuit relative to the ground to obtain a voltage after the level conversion for the second time;
the output module is connected with the working voltage of the integrated circuit and used for logically shaping the voltage subjected to the second level conversion, and the output end of the output module is used as the output end of the level conversion circuit to output the voltage subjected to the logical shaping to drive a post-stage circuit;
the input ends of the positive feedback module and the level conversion module are connected with the output end of the input module, and the output end of the level conversion module is connected with the input end of the output module.
Preferably, the input module includes a first NMOS transistor and a first current source;
the grid electrode of the first NMOS tube is used as the first input end of the input module, the source electrode of the first NMOS tube is used as the second input end of the input module, the drain electrode of the first NMOS tube is connected with the third input voltage through the first current source, and the drain electrode of the first NMOS tube is used as the output end of the input module.
Preferably, the positive feedback module includes a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first current sink, and a second current source;
the grid electrode of the second NMOS tube is connected with the working voltage of the integrated circuit, the source electrode of the second NMOS tube is grounded through the first current sink, and the drain electrode of the second NMOS tube is simultaneously connected with the drain electrode of the first PMOS tube and the grid electrode of the second PMOS tube;
the grid electrode of the first PMOS tube and the drain electrode of the second PMOS tube are simultaneously connected with the output end of the input module;
the source electrode of the first PMOS tube is connected with the third input voltage;
and the source electrode of the second PMOS tube is connected with the third input voltage through the second current source.
Preferably, the level shift module includes a third PMOS transistor, a third NMOS transistor, and a second current sink;
the grid electrode of the third PMOS tube is used as the input end of the level conversion module; the source electrode of the third PMOS tube is connected with the third input voltage, and the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube;
the grid electrode of the third NMOS tube is connected with the working voltage of the integrated circuit, the source electrode of the third NMOS tube is grounded through the second current sink, and the source electrode of the third NMOS tube is used as the output end of the level conversion module.
Preferably, the output module includes a fourth NMOS transistor, a third current source, and a low voltage buffer;
the grid electrode of the fourth NMOS tube is used as the input end of the output module, the source electrode of the fourth NMOS tube is grounded, the drain electrode of the fourth NMOS tube is connected with the working voltage of the integrated circuit through the third current source, the drain electrode of the fourth NMOS tube is also connected with the input end of the low-voltage buffer, the output end of the low-voltage buffer is used as the output end of the output module, the power supply end of the low-voltage buffer is connected with the working voltage of the integrated circuit, and the grounding end of the low-voltage buffer is grounded.
The driving circuit comprising the level conversion circuit comprises a high-side driving power tube, a low-side driving power tube, a first inverter, a second inverter and a first NAND gate, and is mainly characterized in that the driving circuit comprises a bootstrap circuit module, a level shift module and a second NAND gate;
the input end of the level shift module is connected with a high-side input signal, the output end of the level shift module is connected with the first input end of the second NAND gate, the output end of the second NAND gate is connected with the first input end of the first phase inverter, and the output end of the first phase inverter is simultaneously connected with the first input end of the level conversion circuit and the control end of the high-side driving power tube;
the first input end of the first NAND gate is connected with a low-side input signal, the output end of the first NAND gate is connected with the first input end of the second inverter, and the output end of the second inverter is simultaneously connected with the second input end of the second NAND gate and the control end of the low-side driving power tube;
the bootstrap circuit module is used for providing bootstrap voltage, and an output end of the bootstrap circuit module is simultaneously connected with a first end of the high-side driving power tube, a first end of the low-side driving power tube and a second input end of the level conversion circuit;
the first end of the high-side driving power tube is also connected with the second input end of the first inverter and the third input end of the second NAND gate;
the first end of the high-side driving power tube and the first end of the low-side driving power tube jointly form the output end of the driving circuit and are connected with one end of an external load;
the output end of the level switching circuit is connected with the second input end of the first NAND gate;
the power supply end of the first NAND gate and the power supply end of the second inverter are both connected with the working voltage of the integrated circuit; the power supply end of the second NAND gate and the power supply end of the first inverter are both connected with the third input voltage; the second end of the high-side driving power tube is connected with a fourth input voltage;
the third input end of the first nand gate, the second input end of the second inverter and the second end of the low-side driving power tube are all grounded.
Preferably, the output end of the second inverter is connected to the second input end of the second nand gate through the schmitt trigger.
Preferably, the bootstrap circuit module includes a capacitor and a diode, one end of the capacitor and a cathode of the diode are both connected to the third input voltage, an anode of the diode is connected to the working voltage of the integrated circuit, and the other end of the capacitor is used as an output end of the bootstrap circuit module.
Preferably, the high-side driving power tube and the low-side driving power tube are both N-type power tubes.
The level switching circuit can effectively switch the levels between different logic levels, has high conversion efficiency and can realize high-speed matching between the two levels. The level conversion circuit can be applied to the occasions of conventional level conversion, can also be applied to a bootstrap boosting structure, and has wider application range. The drive circuit comprising the level conversion circuit can convert a high-voltage power supply in the drive circuit into a low-voltage power supply, avoid the problem that all devices in the whole drive circuit need to adopt high-voltage devices, effectively reduce the area of a circuit layout and save the circuit cost.
Drawings
Fig. 1 is a schematic structural diagram of a driving circuit in the prior art.
Fig. 2 is a schematic structural diagram of a level shift circuit according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram of a driving circuit according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to specific embodiments.
As shown in fig. 2, the level shift circuit includes:
an input module, including a first input end (a position marked with HG in fig. 2) and a second input end (a position marked with PHASE in fig. 2), where the first input end of the input module is connected to an external first input voltage, the second input end of the input module is connected to an external second input voltage, the input module is further connected to a third input voltage VBT, and the input module is configured to convert a logic level of the first input end of the input module with respect to the second input end into a logic level of the first input end of the input module with respect to ground, so as to obtain a voltage after first level conversion; the first input end of the input module is used as the first input end of the level shift circuit, and the second input end of the input module is used as the second input end of the level shift circuit;
the positive feedback module is connected with the working voltage VDD of the integrated circuit and the third input voltage VBT and used for reducing the level conversion time of the input module;
the level conversion module is connected with the working voltage VDD of the integrated circuit and the third input voltage VBT and used for converting the voltage range of the third input voltage VBT relative to the ground into the voltage range of the working voltage VDD of the integrated circuit relative to the ground so as to obtain the voltage after the second level conversion;
the output module is connected with the working voltage VDD of the integrated circuit and used for logically shaping the voltage subjected to the second level conversion, and the output end OUT of the output module is used as the output end of the level conversion circuit and outputs the voltage subjected to the logical shaping to drive a post-stage circuit;
the input ends of the positive feedback module and the level conversion module are connected with the output end of the input module, and the output end of the level conversion module is connected with the input end of the output module.
In the above embodiment, the input module includes the first NMOS transistor MN1 and the first current source I11;
the gate of the first NMOS transistor MN1 is used as the first input terminal of the input module, the source of the first NMOS transistor MN1 is used as the second input terminal of the input module, the drain of the first NMOS transistor MN1 is connected to the third input voltage VBT via the first current source I11, and the drain of the first NMOS transistor MN1 is used as the output terminal of the input module.
In the above embodiment, the positive feedback module includes a second NMOS transistor MN2, a first PMOS transistor MP1, a second PMOS transistor MP2, a first current sink I21, and a second current source I12;
the grid electrode of the second NMOS tube MN2 is connected with the working voltage VDD of the integrated circuit, the source electrode of the second NMOS tube MN2 is grounded through the first current sink I21, and the drain electrode of the second NMOS tube MN2 is simultaneously connected with the drain electrode of the first PMOS tube MP1 and the grid electrode of the second PMOS tube MP 2;
the grid electrode of the first PMOS pipe MP1 and the drain electrode of the second PMOS pipe MP2 are simultaneously connected with the output end of the input module;
the source of the first PMOS transistor MP1 is connected to the third input voltage VBT;
the source of the second PMOS transistor MP2 is connected to the third input voltage VBT via the second current source I12.
In the above embodiment, the level shifter module includes a third PMOS transistor MP3, a third NMOS transistor MN3, and a second current sink I22;
the grid electrode of the third PMOS tube MP3 is used as the input end of the level conversion module; the source of the third PMOS transistor MP3 is connected to the third input voltage VBT, and the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN 3;
the gate of the third NMOS transistor MN3 is connected to the operating voltage VDD of the integrated circuit, the source of the third NMOS transistor MN3 is grounded via the second current sink I22, and the source of the third NMOS transistor MN3 is used as the output terminal of the level shifter module.
In the above embodiment, the output module includes a fourth NMOS transistor MN4, a third current source I13, and a low voltage buffer I3;
the gate of the fourth NMOS transistor MN4 is used as the input terminal of the output module, the source of the fourth NMOS transistor MN4 is grounded, the drain of the fourth NMOS transistor MN4 is connected to the operating voltage VDD of the integrated circuit through the third current source I13, the drain of the fourth NMOS transistor MN4 is further connected to the input terminal of the low voltage buffer I3, the output terminal of the low voltage buffer I3 is used as the output terminal OUT of the output module, the power supply terminal of the low voltage buffer I3 is connected to the operating voltage VDD of the integrated circuit, and the ground terminal of the low voltage buffer I3 is grounded.
The first NMOS transistor MN1, the second PMOS transistor MP2, and the fourth NMOS transistor MN4 in the level shift circuit may all be formed by low voltage devices, and only the first PMOS transistor MP1, the second NMOS transistor MN2, the third PMOS transistor MP3, and the third NMOS transistor MN3 are formed by high voltage devices. The first current source I11, the second current source I12, the third current source I13, the first current sink I21, and the second current sink I22 are all formed by low voltage devices, and are used as active loads for currents of each stage, wherein the current sink, which may also be referred to as a current sink, is a device that is a current source, the current source is a structure that draws current from a power supply terminal, and is usually formed by a PMOS device, and the current sink is a structure that sinks current to ground, and is usually formed by an NMOS device.
In an embodiment, the level shift circuit in the above embodiment is applied to a driving circuit to solve the problem of high cost of the driving circuit, and the structure of the driving circuit can be seen from fig. 3.
The driving circuit comprising the level shifter circuit comprises a level shifter circuit I4, a high-side driving power tube MN5, a low-side driving power tube MN6, a first inverter I7, a second inverter I9 and a first NAND gate I8, wherein the driving circuit further comprises a bootstrap circuit module, a level shift module I5 and a second NAND gate I6;
the input end of the level shift module I5 is connected to the high-side input signal HSIN, the output end of the level shift module I5 is connected to the first input end of the second nand gate I6, the output end of the second nand gate I6 is connected to the first input end of the first inverter I7, and the output end of the first inverter I7 is simultaneously connected to the first input end of the level shift circuit I4 and the control end of the high-side driving power transistor MN 5;
a first input end of the first nand gate I8 is connected to a low-side input signal LSIN, an output end of the first nand gate I8 is connected to a first input end of the second inverter I9, and an output end of the second inverter I9 is simultaneously connected to a second input end of the second nand gate I6 and a control end of the low-side driving power transistor MN 6;
the bootstrap circuit module is configured to provide a bootstrap voltage VBT, and an output end of the bootstrap circuit module is simultaneously connected to the first end of the high-side driving power transistor MN5, the first end of the low-side driving power transistor MN6, and the second input end of the level shifter circuit I4;
the first end of the high-side driving power tube MN5 is also connected with the second input end of the first inverter I7 and the third input end of the second NAND gate I6;
the first end of the high-side driving power tube MN5 and the first end of the low-side driving power tube MN6 jointly form the output end of the driving circuit, the output end of the driving circuit is connected with one end of an external load, and the other end of the external load can be grounded;
the output end of the level switching circuit I4 is connected with the second input end of the first NAND gate I8;
the power supply end of the first NAND gate I8 and the power supply end of the second inverter I9 are both connected with the working voltage VDD of the integrated circuit; the power supply terminal of the second nand gate I6 and the power supply terminal of the first inverter I7 are both connected to the third input voltage VBT; a second end of the high-side driving power tube MN5 is connected to a fourth input voltage VBRG;
the third input terminal of the first nand gate I8, the second input terminal of the second inverter I9 and the second terminal of the low-side driver MN6 are all grounded.
The level shift module I5 converts the level of the high-side input signal HSIN into a level between the second input voltage and the third input voltage VBT, and converts the level of the logic portion into a level matching the bootstrapped logic.
The level shifter I4 functions in the driving circuit to convert the high voltage (the high voltage is the first input voltage) collected at the gate of the high-side driving power transistor MN5 into a digital logic voltage acceptable by a low-voltage gate circuit, which is referred to as the first nand gate I8 in the driving circuit in this embodiment.
In the above embodiment, the output terminal of the second inverter I9 is connected to the second input terminal of the second nand gate I6 through the schmitt trigger I10.
The schmitt trigger I10 functions as: the sampled signal of the control terminal of the low-side driving power tube MN6 is fed back to the logic control device before the high-side driving power tube MN5 (i.e., fed back to the second input terminal of the second nand gate I6).
In the above embodiment, the bootstrap circuit module includes a capacitor C1 and a diode D1, one end of the capacitor C1 and a cathode of the diode D1 are both connected to the third input voltage VBT, an anode of the diode D1 is connected to the operating voltage VDD of the integrated circuit, and the other end of the capacitor C1 is used as an output end of the bootstrap circuit module.
In the above embodiments, the high-side driver MN5 and the low-side driver MN6 are both N-type power transistors.
Since the N-type power transistor is used as the high-side driving power transistor MN5 in this embodiment, while the performance is guaranteed, compared with the technical solution in the prior art in which the P-type power transistor must be used as the high-side driving power transistor MN5, the layout area at the position of the high-side driving power transistor MN5 can be reduced by at least fifty percent.
The position where the first input end of the level shifter I4 is connected to the control end of the high-side driver power transistor MN5 (i.e., the position marked with HG in the figure) is a gate line network of the high-side driver power transistor MN5, and the position where the second input end of the level shifter I4 is connected to the first end of the high-side driver power transistor MN5 (i.e., the position marked with PHASE in the figure) is a line network connected to the high-side and low-side driver power transistors (the line network is formed by the high-side driver power transistor MN5 and the low-side driver power transistor MN 6).
The level shift circuit I4 in the above embodiment is included in the driving circuit, so that the bootstrap voltage of the high-side portion in the driving circuit can be shifted to a low-voltage level, and the shifting speed is high, and the level shift circuit I4 is used as a part of a functional module in the driving circuit that plays a role in preventing a shoot-through, and plays an important role in ensuring that the high-side driving power transistor MN5 and the low-side driving power transistor MN6 are prevented from being burnt out due to the shoot-through. And because the level shift circuit I4 is adopted in the driving circuit, most of the devices in the driving circuit can adopt low-voltage devices (for example, the second nand gate I6 and the first inverter I7 in fig. 3 can be formed by low-voltage isolation devices, the substrate voltages of the second nand gate I6 and the first inverter I7 are connected to the first end of the high-side driving power tube MN5 (i.e. the source end of the NMOS tube forming the high-side driving power tube MN 5), and the first nand gate I8, the second inverter I9 and the schmitt trigger I10 can be formed by common low-voltage devices, so that the consumption of the circuit layout area is reduced, the circuit layout area is greatly reduced, the cost of the driving circuit is reduced under the condition of ensuring the working speed of the driving circuit, and the driving circuit has a simple structure and reliable performance.
The operation of the level shifter circuit in the present embodiment in the driving circuit is further analyzed with reference to fig. 2 and 3 as follows:
in fig. 2, a1 to A3 indicate intermediate circuit net names at each point, that is, a1 is an intermediate circuit net name at a connection point of the gate of the first PMOS transistor MP1, the drain of the second PMOS transistor MP2, the drain of the first NMOS transistor MN1, and the first current source, a2 is an intermediate circuit net name at a connection point of the drain of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and the drain of the second NMOS transistor MN2, and A3 is an intermediate circuit net name at a connection point of the gate of the fourth NMOS transistor MN4, the source of the third NMOS transistor MN3, and the second current sink.
When the high-side driving power transistor MN5 is turned on, the potential of the first input terminal (HG terminal in the figure) in the level shifter I4 is higher than the potential of the second input terminal (PHASE terminal in the figure) in the level shifter, where the second input voltage input by the second input terminal is a bootstrap voltage slightly lower than the operating voltage VDD of the integrated circuit, at this time, the first NMOS transistor MN1 is turned on, the potential at a1 point in fig. 2 outputs a low potential relative to the second input terminal in the level shifter, the third PMOS transistor MP3 is turned on, and the third NMOS transistor MN3 is normally on, the A3 position in fig. 2 outputs a high level relative to ground (i.e., the voltage after the second level shift), and the output terminal OUT of the output module outputs the low level relative to ground;
when the high-side driving power tube MN5 is turned off, the potential of the first input terminal (the position of the HG terminal in fig. 2) in the level shifter circuit I4 is equal to the potential of the second input terminal (the position of the PHASE terminal in fig. 2) in the level shifter circuit, the position of a1 in fig. 2 outputs a high level higher than the second input terminal in the level shifter circuit due to the action of the first current source I11, the position of A3 in fig. 2 outputs a low level (i.e., a voltage after the second level shift) with respect to the ground, and the output terminal OUT of the output module outputs the high level with respect to the ground.
In the level shift circuit, a positive feedback module is formed by the second NMOS transistor MN2, the first PMOS transistor MP1, the second PMOS transistor MP2, the first current sink I21 and the second current source I12, when the high-side driving power transistor MN5 is turned off,
in fig. 2, the potential at point a1 is at a high level relative to the second input terminal of the input module, point a2 changes to a low level relative to the second input terminal of the input module due to the action of the pull-down current sink, the second PMOS transistor MP2 is turned on, and the first current source I11 and the second current source I12 are simultaneously turned on as pull-up current sources, which reduces the time of the rising edge of the potential at point a 1.
Compared with the level conversion circuit in the prior art, the level conversion circuit in the embodiment can effectively improve the level conversion time efficiency, and the actual measurement of the circuit structure in the embodiment finds that the delay from the rising edge of an input signal to the falling edge of an output end is about 5ns, the delay from the falling edge of the input signal to the rising edge of the output signal is about 10ns, and the voltage conversion efficiency is particularly high.
In the driving circuit structure shown in fig. 3, in the control structure, the gate driving devices (e.g., the first inverter I7 and the second inverter I9) of the high-side driving power transistor MN5 and the low-side driving power transistor MN6 and the feedback device (e.g., the schmitt trigger I10) for preventing shoot-through can be implemented by using low-voltage gates. In order to ensure that the high-side driving power transistor MN5 is turned on, the high-level voltage of the gate of the high-side driving power transistor MN5 is obtained by bootstrap boosting, which is generally the fourth input voltage VBRG plus the operating voltage VDD of the integrated circuit. When the high-side driving power transistor MN5 is turned off, the gate voltage is ground. This voltage range needs to be converted to a low voltage potential from the operating voltage VDD of the integrated circuit to ground in order to be potential matched to the low voltage devices in the anti-shoot-through circuit. Such voltage conversion can be realized by the level conversion circuit proposed in the present invention.
The level conversion circuit can convert the bootstrapped level into the level corresponding to the low-voltage digital logic in the driving circuit, has smaller time delay, and plays an important role in a direct connection prevention structure of the power driving circuit.
The level shift circuit in the above embodiment may be used in other applications besides the above driving circuit, and may also be used to implement level shift between different logic levels. For example, in a data acquisition system, the ADC uses a voltage of +5v, and the VDD voltage used by the microcontroller is a voltage of 3.3v or 2.5v, when high-speed data transmission is performed, a level conversion circuit in the embodiment may be used to perform level conversion, at this time, only the second input terminal in the circuit is connected to ground, the third input voltage VBT is connected to a voltage of 5v, the first input terminal in the level conversion circuit is connected to a logic level output by the ADC, the operating voltage VDD of the integrated circuit is connected to a power supply terminal of the microcontroller, and the output terminal outputs the same logic level as the microcontroller, so that high-speed matching between the two levels can be achieved. The level shift circuit in this embodiment can be used in a bootstrap boosting structure. In such a bootstrap boosting structure, the voltage to which the logic level of the input signal is referenced is not fixed, but switches at any time with different working states of the circuit, such as the PHASE end potential in the above-described embodiment, the voltage at the first input terminal HG of the corresponding level shifter circuit may vary from the fourth input voltage VBRG to ground, which may be provided by the power supply of the external load for other different load applications, and may vary from the third input voltage VBT (the third input voltage VBT is a bootstrap voltage in the above-mentioned driver circuit, which is provided by the capacitor C1 in the bootstrap circuit module) to the operating voltage VDD of the integrated circuit, which may vary from VBRG + VDD to VDD (the fourth input voltage VBRG is the drain voltage of the high-side driving power transistor MN5 in the driver circuit). The logic level of the input signal of the module is determined by the voltage difference between the first input end HG of the level shift circuit and the second input end PHASE of the level shift circuit, and the logic level of the first input end HG refers to a variable voltage, so that the module is more suitable for the application occasions of bootstrap boosting circuits in high-side level detection.
The level switching circuit can effectively switch the levels between different logic levels, has high conversion efficiency and can realize high-speed matching between the two levels. The level conversion circuit can be applied to the occasions of conventional level conversion, can also be applied to a bootstrap boosting structure, and has wider application range. The drive circuit comprising the level conversion circuit can convert a high-voltage power supply in the drive circuit into a low-voltage power supply, avoid the problem that all devices in the whole drive circuit need to adopt high-voltage devices, effectively reduce the area of a circuit layout and save the circuit cost.
In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (9)
1. A level shift circuit, comprising:
the input module comprises a first input end and a second input end, wherein the first input end of the input module is connected with an external first input voltage, the second input end of the input module is connected with an external second input voltage, the input module is also connected with a third input voltage, and the input module is used for converting the logic level of the first input end of the input module relative to the second input end into the logic level of the first input end of the input module relative to the ground to obtain a voltage after the first level conversion; the first input end of the input module is used as the first input end of the level shift circuit, and the second input end of the input module is used as the second input end of the level shift circuit;
the positive feedback module is connected with the working voltage of the integrated circuit and the third input voltage and used for reducing the level conversion time of the input module;
the level conversion module is connected with the working voltage of the integrated circuit and the third input voltage and is used for converting the voltage range of the third input voltage relative to the ground into the voltage range of the working voltage of the integrated circuit relative to the ground to obtain a voltage after the level conversion for the second time;
the output module is connected with the working voltage of the integrated circuit and used for logically shaping the voltage subjected to the second level conversion, and the output end of the output module is used as the output end of the level conversion circuit to output the voltage subjected to the logical shaping to drive a post-stage circuit;
the input ends of the positive feedback module and the level conversion module are connected with the output end of the input module, and the output end of the level conversion module is connected with the input end of the output module.
2. The circuit of claim 1, wherein the input module comprises a first NMOS transistor and a first current source;
the grid electrode of the first NMOS tube is used as the first input end of the input module, the source electrode of the first NMOS tube is used as the second input end of the input module, the drain electrode of the first NMOS tube is connected with the third input voltage through the first current source, and the drain electrode of the first NMOS tube is used as the output end of the input module.
3. The circuit of claim 1, wherein the positive feedback module comprises a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first current sink, and a second current source;
the grid electrode of the second NMOS tube is connected with the working voltage of the integrated circuit, the source electrode of the second NMOS tube is grounded through the first current sink, and the drain electrode of the second NMOS tube is simultaneously connected with the drain electrode of the first PMOS tube and the grid electrode of the second PMOS tube;
the grid electrode of the first PMOS tube and the drain electrode of the second PMOS tube are simultaneously connected with the output end of the input module;
the source electrode of the first PMOS tube is connected with the third input voltage;
and the source electrode of the second PMOS tube is connected with the third input voltage through the second current source.
4. The circuit of claim 1, wherein the level shift module comprises a third PMOS transistor, a third NMOS transistor, and a second current sink;
the grid electrode of the third PMOS tube is used as the input end of the level conversion module; the source electrode of the third PMOS tube is connected with the third input voltage, and the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube;
the grid electrode of the third NMOS tube is connected with the working voltage of the integrated circuit, the source electrode of the third NMOS tube is grounded through the second current sink, and the source electrode of the third NMOS tube is used as the output end of the level conversion module.
5. The circuit of claim 1, wherein the output module comprises a fourth NMOS transistor, a third current source, and a low voltage buffer;
the grid electrode of the fourth NMOS tube is used as the input end of the output module, the source electrode of the fourth NMOS tube is grounded, the drain electrode of the fourth NMOS tube is connected with the working voltage of the integrated circuit through the third current source, the drain electrode of the fourth NMOS tube is also connected with the input end of the low-voltage buffer, the output end of the low-voltage buffer is used as the output end of the output module, the power supply end of the low-voltage buffer is connected with the working voltage of the integrated circuit, and the grounding end of the low-voltage buffer is grounded.
6. A driving circuit comprising the level shift circuit as claimed in any one of claims 1 to 5, comprising a high-side driving power transistor, a low-side driving power transistor, a first inverter, a second inverter and a first NAND gate, wherein the driving circuit comprises a bootstrap module, a level shift module and a second NAND gate;
the input end of the level shift module is connected with a high-side input signal, the output end of the level shift module is connected with the first input end of the second NAND gate, the output end of the second NAND gate is connected with the first input end of the first phase inverter, and the output end of the first phase inverter is simultaneously connected with the first input end of the level conversion circuit and the control end of the high-side driving power tube;
the first input end of the first NAND gate is connected with a low-side input signal, the output end of the first NAND gate is connected with the first input end of the second inverter, and the output end of the second inverter is simultaneously connected with the second input end of the second NAND gate and the control end of the low-side driving power tube;
the bootstrap circuit module is used for providing bootstrap voltage, and an output end of the bootstrap circuit module is simultaneously connected with a first end of the high-side driving power tube, a first end of the low-side driving power tube and a second input end of the level conversion circuit;
the first end of the high-side driving power tube is also connected with the second input end of the first inverter and the third input end of the second NAND gate;
the first end of the high-side driving power tube and the first end of the low-side driving power tube jointly form the output end of the driving circuit and are connected with one end of an external load;
the output end of the level switching circuit is connected with the second input end of the first NAND gate;
the power supply end of the first NAND gate and the power supply end of the second inverter are both connected with the working voltage of the integrated circuit; the power supply end of the second NAND gate and the power supply end of the first inverter are both connected with the third input voltage; the second end of the high-side driving power tube is connected with a fourth input voltage;
the third input end of the first nand gate, the second input end of the second inverter and the second end of the low-side driving power tube are all grounded.
7. The driving circuit of claim 6, wherein an output of the second inverter is connected to a second input of the second nand gate through a schmitt trigger.
8. The driving circuit according to claim 6, wherein the bootstrap circuit module includes a capacitor and a diode, one end of the capacitor and a cathode of the diode are both connected to the third input voltage, an anode of the diode is connected to the operating voltage of the integrated circuit, and the other end of the capacitor is used as an output end of the bootstrap circuit module.
9. The driving circuit as claimed in claim 6, wherein the high side driving power transistor and the low side driving power transistor are both N-type power transistors.
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| CN201811508265.7A CN111313887B (en) | 2018-12-11 | 2018-12-11 | Level conversion circuit and corresponding driving circuit |
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| CN201811508265.7A CN111313887B (en) | 2018-12-11 | 2018-12-11 | Level conversion circuit and corresponding driving circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112511142A (en) * | 2020-12-10 | 2021-03-16 | 中国电子科技集团公司第十四研究所 | Fully-integrated NMOS (N-channel metal oxide semiconductor) tube driving circuit |
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| CN111313887B (en) | 2023-06-23 |
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