JP2001274674A - Multi-stage level shift circuit and semiconductor device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve problems that a conventional level shift circuit converting signals with different power supplies in a semiconductor integrated circuit employing many kinds of power supplies is deteriorated in characteristics such as the response and low current consumption at a low voltage or at a high voltage difference among different power supplies and has had a difficulty of the configuration by means of combinations of transistors(TRs) of the same size such as a gate array. SOLUTION: The level shift circuit employs basic level shift circuits, receives different voltages from a MOS diode power supply circuit, converts voltages of a reasonable range and obtains a voltage signal with a final objective voltage through the repetitive conversions as above. Since the respective conversions are conducted within the rational voltage range not causing contention, the level shift circuit with high response and a low consumed current can be realized even at a low voltage and a high voltage difference. Since no contention takes place and the circuit can easily be configured even with combinations of the identical TRs, the circuit of this invention can easily cope with various specifications even through the use of existing gate arrays on market.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for converting signals between different power supplies in a semiconductor integrated circuit in which multiple power supplies are mixed, particularly when a potential difference between different power supply systems is large, for example, in a gate array semiconductor device or a master slice. In a semiconductor device, the present invention relates to a configuration of a multi-stage level shift circuit and a semiconductor device which easily correspond to different specifications.

[0002]

2. Description of the Related Art Typical circuits of a conventional level shift circuit are shown in FIGS. FIG. 5 shows West German Patent Publication 21548.
77 (DE, A). FIG. 6 is a circuit diagram of Japanese Patent Application Laid-Open No. 57-59690. 5, the circuit of Figure 6 is configured and summer for both converting a signal of the power supply voltage E ₁ system to the power source voltage E ₂ system signal. Japanese Patent Application Laid-Open No. 02-089345 discloses an example in which a level shift circuit is mounted on an input / output circuit cell in a gate array corresponding to various specifications in a wiring process.
There is a number. Also, by devising the transistors of the basic cells in the gate array in series and parallel with wiring, the conductance of each of the P and N insulated gate field effect transistors (hereinafter abbreviated as MOSFETs) equivalently required for the specification. FIG. 7 shows an example in which the constants β and β ratio are created.

[0003]

[SUMMARY OF THE INVENTION Now, the conventional circuit described above is a practical circuit if the potential difference between E ₁ and E ₂ is not so large. However, as the potential difference between E ₁ and E ₂ increases, β _{P of the} P-type MOSFET and the N-type
Very large it becomes necessary to take the ratio of beta _N of SFET, operation is lowered extremely, the current consumption or a great deal, there is a problem that excessive occurs in the shape of the layout. In particular, in recent years, elements such as MOSFETs used for integrated circuits have been miniaturized, the withstand voltage has been reduced, and a low-voltage power supply has become inevitable. In addition, as the demand for lower power consumption and lower voltage for portable devices has increased, the above-described E ₁ and E ₁ have been applied between components operating at a low voltage inside the integrated circuit and components operating at a relatively high voltage outside. There is a need for a level shift circuit having good characteristics even when the potential difference of ₂ is large.

Further, a level shift circuit for converting signals between different power supply systems is also required for a semiconductor device corresponding to various specifications by changing only a wiring layer such as a gate array. For custom-designed models that uniquely correspond to individual specifications, the MOSFET shape, P, N
The β ratio between the molds can be freely designed. However, even if a gate array or the like includes a dedicated level shift circuit as disclosed in Japanese Patent Application Laid-Open No. 02-089345, if the specifications change, the optimum level shift characteristics will be reduced. There was a problem that it was not possible to cope with many different specifications because it changed accordingly.

In the gate array, the MOSFETs in the basic cells are used in series or in parallel to secure the equivalently required β ratio of the conventional circuit shown in FIGS. 5 and 6 and the like. When the potential difference between them is very large, a huge number of MOSFETs are required, which is undesirable in terms of layout and other electrical characteristics.

Therefore, the present invention solves such a problem, and an object of the present invention is to reduce the voltage when the voltage is reduced.
Another object of the present invention is to provide a multistage level shift circuit which has a high response speed even when the potential difference between different power supply systems is very large, consumes little current, and is easy to layout.

Further, a semiconductor device which can easily cope with the case where a number of level shift circuits having various different specifications must be constituted by a combination of the same cell and the same shape of MOSFET wiring layer such as a gate array device. The purpose is to provide.

[0008]

According to the present invention, there is provided a multi-stage level shift circuit comprising: a first power supply having a first potential of a first polarity;
A semiconductor integrated circuit device having a second power supply having a second potential of a first polarity and a third power supply of a second polarity, comprising: an input signal terminal, an inverted input signal terminal, an output signal terminal, and an inverted output. A level conversion function of receiving a low-voltage input signal at the input signal terminal and the inverted input signal terminal, and outputting a low-voltage input signal to the output signal terminal and the inverted output signal terminal as a high-voltage signal. N (where N is an integer of 2 or more) basic level shift circuits comprising a combination of insulated gate field effect transistors (hereinafter abbreviated as MOSFETs), and a gate electrode and a drain electrode of the MOSFET of the first polarity. MOS diodes (N-
1) a MOS diode power supply circuit connected in series and taking a potential from each drain electrode, and the power supply side of the first basic level shift circuit of the N basic level shift circuits is A MOS diode power supply circuit is connected to a drain electrode in which (N-1) MOS diodes are cascade-connected, an input signal terminal is connected to a signal of a first power supply system, and an inverted input signal terminal is connected to an inverted input signal terminal. The inverted signal of the signal is connected, and the K-th signal (2 ≦ K
≦ N−1) on the power supply side of the basic level shift circuit.
A drain electrode in which (NK) MOS diodes of the OS diode power supply circuit are connected in cascade is connected, an input signal terminal is connected to an output signal terminal of the (K-1) th basic level shift circuit, The inverted input signal terminal is connected to the inverted output signal terminal of the (K-1) th basic level shift circuit, and the Nth basic level shift circuit is connected to the second power supply at the power supply side. The terminal is connected to the output signal terminal of the (N-1) th basic level shift circuit, the inverted input signal terminal is connected to the inverted output signal terminal of the (N-1) th basic level shift circuit, The output signal terminal and the inverted output signal terminal of the first basic level shift circuit are the final output signal terminal and the inverted output signal terminal, respectively.

[0009] That is, a power supply whose voltage is appropriately lowered from a plurality of basic level shift circuits and a MOS diode power supply circuit in which MOS diodes are connected in series is prepared. With a sufficiently low power supply voltage that does not compete, an output signal of a slightly higher voltage is generated. Similarly, a plurality of basic level shift circuits, each of which is supplied with a slightly higher power supply voltage from the MOS diode power supply circuit in order, sequentially and smoothly perform level conversion while repeating this, and finally obtain a higher voltage. Producing an output signal.

Further, the basic level shift circuit comprises a first
Polarity first MOSFET and first polarity second MO
An SFET and a third MOSFET of a second polarity are connected in series, a fourth MOSFET of a first polarity, a fifth MOSFET of a first polarity, and a sixth MOSFET of a second polarity.
ET are connected in series, the source electrodes of the first MOSFET and the fourth MOSFET are connected to each other to form a power supply system of a first polarity, and the third MOSFET
T and the source electrode of the sixth MOSFET are connected to each other to form a power supply system of a second polarity, and the second MO
The SFET and the gate electrode of the third MOSFET are connected to each other to serve as an input signal terminal, and
The SFET and the gate electrode of the sixth MOSFET are connected to each other to form an inverted input signal terminal, and the second MOSFET and the drain electrode of the third MOSFET are connected to each other to form an inverted output signal terminal. The drain electrode of the fifth MOSFET and the drain electrode of the sixth MOSFET are connected to each other to form an output signal terminal, and the gate electrode of the first MOSFET is connected to the output signal terminal, and the gate of the fourth MOSFET is The electrode may be connected to the inverted output signal terminal.

Further, the product of the number N of the basic level shift circuits used and the threshold voltage of the MOSFET of the first polarity used in the basic level shift circuit and the MOS diode is the potential of the second power supply and the second power supply. The configuration may be larger than the difference between the potentials of one power supply.

Further, the basic level shift circuit and the MOS diode power supply circuit are P-type or N-type MOSFETs having the same size as a basic cell built in a gate array semiconductor device or a master slice semiconductor device. May be configured as a semiconductor device characterized by being realized by using a semiconductor device.

According to the above construction of the present invention, the basic level shift circuit is used with a power supply having an appropriate voltage drop, and the P and N MOS transistors are used during the conversion operation of the basic level shift circuit.
The conversion is performed within a range where the FETs do not compete, and this reasonable conversion is repeatedly performed to obtain a signal of the final target output voltage. In this conversion process, the operation is quickly performed, and there is no competitive short-circuit current. Low current consumption.

In addition, in the above-described configuration, the P and N MOSFETs do not compete during the conversion operation of the basic level shift circuit, so that the shape of the MOSFET transistors which affect the driving capability is substantially irrelevant. Therefore, even with a combination of the same MOSFETs of the basic cells of the gate array device, the conversion operation is performed without any trouble in the operation.

Even if the specifications between the voltage systems to be converted are various, the number of stages, which is the number of basic level shift circuits, and the number of series MOS diodes in the MOS diode power supply circuit may be changed. The gate array device can respond to various specifications only by changing the wiring.

Further, since the circuit operation is natural as described above, the semiconductor device is designed to have a low voltage, a very large potential difference during conversion, and a basic cell MOSFET in a master slice or gate array. Can be realized with a reasonable number of MOSFETs.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to examples. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, 101 and 102 surrounded by a dashed line.
103 and 104 are basic level shift circuits, respectively. Since these basic level shift circuits play important and basic roles in the present invention, they will be described first. FIG. 2 is an enlarged circuit diagram showing only these basic level shift circuits. The circuit shown in FIG. 2 is a well-known level shift circuit which is also used internally in FIG. 6 shown in the conventional example, and its configuration and operation will be briefly described below.
In FIG. 2, a source electrode of a P-type MOSFET 201 is connected to a positive power supply V ₂ , and a drain electrode is a P-type MOSFET.
It is connected to the source electrode of the FET 202. P-type MO
Drain electrode of SFET 202 and N-type MOSFET 20
3 are connected to each other and the inverted output signal terminal 2
It is 10. The source electrode of the N-type MOSFET 203 is connected to a negative power supply 212 (zero potential). P
The source electrode of the MOSFET 204 is connected to the positive power supply V ₂ , and the drain electrode is connected to the source electrode of the P-type MOSFET 205. The drain electrode of the P-type MOSFET 205 and the drain electrode of the N-type MOSFET 206 are connected to each other to form an output signal terminal 209. N
The source electrode of the MOSFET 206 is a negative power supply 212.
It is connected to the. The gate electrode of the P-type MOSFET 202 and the gate electrode of the N-type MOSFET 203 are connected to each other and to the input signal terminal 207. P-type MOS
The gate electrode of the FET 205 and the gate electrode of the N-type MOSFET 206 are connected to each other and to the inverted input signal terminal 208. The gate electrode of the P-type MOSFET 201 is connected to the output signal terminal 209, and the P-type MOSFET 2
The gate electrode 04 is connected to the inverted output signal terminal 210.

Now, the input signal terminal 207 and its inverted signal
The inverted input signal terminal 208 ₁Works with system power supply
The output signal terminal 209 and the inverted output signal terminal 210
V_TwoThe system potential is output. Initially, the input signal terminal 207
Is 0 (Low) and the inverted input signal terminal 208 is V₁(Hi
gh), the output signal terminal 209 is at 0
Output signal terminal 210 is V_TwoPotential. next
Input signal terminal 207 is V₁(High), inverted input signal
If the terminal 208 changes to 0 (Low), the P-type M
The OSFET 202 has a source potential of approximately V_Two, Gate potential
Is V₁Becomes At this time, the threshold of the P-type MOSFET
Voltage to V_TPThen, V_Two-V₁-V_TPIf <0, it is turned off (OFF), and V_Two-V₁-V_TPIf> 0, it is in a weak ON state. Either way
When the heat potential is closer to off than when it was initially 0,
Become. Further, the N-type MOSFET 203 is turned on. Ma
In addition, the P-type MOSFET 205 is turned on and the N-type MOS
The FET 206 turns off. Therefore, N-type MOSF
ET203 exceeds driving capability of P-type MOSFET 202
Then, the inverted output signal terminal 210 approaches the Low potential,
The P-type MOSFET 204 turns on and the P-type MOSFET 2
05 to V_TwoSystem power supply potential is supplied to the output signal terminal 20
9 is V_TwoPotential and the P-type MOSFET 201
V to the gate electrode_TwoPotential is supplied to the P-type MOSFET
201 turns off. Therefore, the output signal terminal 209 is at V
_TwoAnd the inverted output signal terminal 210 is finally set to a potential of 0.
To be stable. Further, the input signal terminal is again 0 (Low),
When the inverted input signal terminal 208 is at V₁(High)
Then, the P-type MOSFET 204 is 201 and the P-type MOS is
FET 205 is 202, N-type MOSFET 206 is N-type
The same thing happens when MOSFET 203 is replaced.
Finally, the output signal terminal 209 has 0 potential and the inverted output signal.
No. terminal 210 is V_TwoThe potential finally stabilizes. Or more
V₁From the input signal of the system, V_TwoSystem output signal
You.

Returning to FIG. In FIG. 1, reference numeral 116 denotes a positive power supply having a _first potential E1. Reference numeral 117 denotes a positive power supply having a _second potential E2. Where E ₂ >
It is E _1. Reference numeral 118 denotes a negative power supply, which is a common ground. 101, 102, 10 surrounded by a chain line
Reference numerals 3 and 104 denote basic level shift circuits as described above. Reference numeral 105 denotes a MOS diode power supply circuit surrounded by an alternate long and short dash line, and P-type MOSFETs 106, 107, and 108.
Are connected to a gate electrode and a drain electrode, respectively, constitute a MOS diode and are connected in series, and serve to supply a potential having a voltage drop which is an integral multiple of a threshold voltage. 111 P-type MOSFET109 and N-type MOS input signal terminal of the E ₁ series
An inverted input signal is created by a CMOS inverter circuit using the FET 110.

The basic level shift circuit 101 includes a negative power supply 118 and a P-type MOS of a MOS diode power supply circuit 105.
The output of the drain electrode of the FET 108 is used as a positive power supply. The input signal terminal 112 is connected to the input signal terminal 111 of the E ₁ system described above, the inverted input signal terminal 113 is connected the output of the CMOS inverter circuit according to a P-type MOSFET109 and N-type MOSFET110 is.

The basic level shift circuit 102 includes a negative power supply 118 and a P-type MOS of the MOS diode power supply circuit 105.
The output of the drain electrode of the FET 107 is used as a positive power supply. The output signal terminal and the inverted output signal terminal of the basic level shift circuit 101 are connected to the input signal terminal and the inverted input signal terminal of the basic level shift circuit 102, respectively.

The basic level shift circuit 103 includes a negative power supply 118 and a P-type MOS of the MOS diode power supply circuit 105.
The output of the drain electrode of the FET 106 is used as a positive power supply. The input signal terminal and the inverted input signal terminal of the basic level shift circuit 103 are connected to the output signal terminal and the inverted output signal terminal of the basic level shift circuit 102, respectively.

The basic level shift circuit 104 uses the negative power supply 118 and the second potential E ₂ as the positive power supply. The input signal terminal and the inverted input signal terminal of the basic level shift circuit 104 are connected to the output signal terminal and the inverted output signal terminal of the basic level shift circuit 103, respectively. Output signal terminal 114 of basic level shift circuit 104
And the inverted output signal terminal 115 are an output signal terminal and an inverted output signal terminal as a multi-stage level shift circuit of the present invention.

[0023] With the above configuration, 0 and E ₁ system signal operating at voltages of E ₁ is the basic level shift circuit 101,1
Through 02,103,104, gradually to continue to increase the voltage of the output signal is finally converted into a signal operating at voltages of 0 and E _2. In this case, the product of the number of basic level shift circuits used and the threshold voltage of the first polarity MOSFET used in the basic level shift circuit and the MOS diode is the potential of the second power supply and the potential of the second power supply. It is larger than the difference between the potentials of one power supply.

In order to make it easier to understand the functions and effects of the above circuit, actual numerical examples are shown below.

The power supply voltage on the low voltage side is E₁= 0.9
[V], the power supply voltage on the high voltage side is E_Two= 3.0 [V], P
Threshold voltage of N-type and N-type MOSFETs
Each V_TP, V _TNAs V_TP= 0.6 [V], V_TN= 0.
6 [V]. Then, the P-type MOSFET 106, 10
The voltage drop due to the three stages of MOS diodes 7 and 108 is
1.8 [V] (0.6 × 3), so the basic level shift
The power supply potential of the positive electrode of the gate circuit 101 is 1.2 [V] (3.0
-1.8). Therefore, H
When 0.9 [V] which is a high signal is applied, FIG.
P-type MOSFET corresponding to the P-type MOSFET 202
Is 0.9 [V] and the source electrode is approximately 1.2.
[V], so V_GS-V_TH= (1.2−0.9) −0.6 <0. Therefore, the P-type MOSFET 202
The corresponding P-type MOSFET is unconditionally turned off. this
Is the source potential because the gate potential is low (0.9 [V]).
Is also lower (1.2 [V]). Of course,
N-type MOSFET equivalent to N-type MOSFET 203
Indicates that the source electrode has 0 potential and the gate potential has 0.9 [V].
And V_TN= 0.6 [V], so V_GS-V_TH= (0.9-0) -0.6> 0, and the relay is unconditionally turned on. Therefore, the P-type MOSF
ET and N-type MOSFET do not compete,
The output signal changes according to the change of the input signal. So
To the output signal terminal and the inverted output signal terminal.
[V] or 0 [V] is output.

Regarding the basic level shift circuit 102, the voltage drop due to the two stages of the MOS diodes of the P-type MOSFETs 106 and 107 is 1.2 [V] (0.6
× 2), the power supply potential of the positive electrode of the basic level shift circuit 102 becomes 1.8 [V] (3.0-1.2).
Therefore, the basic level shift circuit 10 is connected to the input signal terminal.
When 1.2 [V] which is a High signal of the output signal of No. 1 is applied, the gate of the P-type MOSFET corresponding to the P-type MOSFET 202 in FIG. 2 is 1.2 [V], and the source electrode is almost 1.8. [V], so that V _GS −V _TH = (1.8−1.2) −0.6 ≦ 0. Therefore, the P-type MOSFET corresponding to the P-type MOSFET 202 is turned off. Of course, at this time N
The N-type MOSFET corresponding to the N-type MOSFET 203 is unconditionally turned on because the source electrode has 0 potential and the gate potential is 1.2 [V]. Therefore, the P-type MOSFET and the N-type MOSFET do not compete with each other, and
The input signal of the [V] system is converted into an output signal of the 1.8 [V] system.

Next, regarding the basic level shift circuit 103, the voltage drop by one stage of the MOS diode of the P-type MOSFET 106 is 0.6 [V] (0.6 × 1). The power supply potential of the positive electrode is 2.4 [V] (3.0-0.6). Therefore, when 1.8 [V] which is a High signal of the output signal of the basic level shift circuit 102 is applied to the input signal terminal,
P-type MOSF corresponding to P-type MOSFET 202 in FIG.
The gate of ET is 1.8 [V], and the source electrode is almost 2.4.
[V], so that V _GS -V _TH = (2.4-1.8) -0.6 ≦ 0. Therefore, the P-type MOSFET corresponding to the P-type MOSFET 202 is turned off. Of course, at this time N
The N-type MOSFET corresponding to the N-type MOSFET 203 is unconditionally turned on since the source electrode has 0 potential and the gate potential is 1.8 [V]. Therefore, the P-type MOSFET and the N-type MOSFET do not compete with each other and are reasonably 1.8.
The input signal of [V] system is converted into an output signal of 2.4 [V] system.

Next, with respect to the basic level shift circuit 104, the positive electrode of the basic level shift circuit 104 has 3.
0 [V] is applied. Therefore, when 2.4 [V] which is a High signal of the output signal of the basic level shift circuit 103 is applied to the input signal terminal, the P-type M of FIG.
Since the gate of the P-type MOSFET corresponding to the OSFET 202 is 2.4 [V] and the source electrode is 3.0 [V], V _GS −V _TH = (3.0−2.4) −0.6 ≦ 0 It has become. Therefore, the corresponding P-type MOSFET 202 is turned off. Of course, at this time, the N-type MOSFET corresponding to the N-type MOSFET 203 is unconditionally turned on because the source electrode has 0 potential and the gate potential is 2.4 [V]. Therefore, the P-type MOSFET and N
2.4 without competing with the MOSFET
The input signal of the [V] system is converted into an output signal of the 3.0 [V] system.

In the above circuit, in the conventional level shift circuit, a P-type MOSFET 202 and an N-type MOSFET
While the ET203 was designed to compete,
The voltage on the positive electrode side is reduced so that the P-type MOSFET and the N-type MOSFET perform a conversion operation without competing with each other, the number of stages is increased accordingly, and the conversion is repeated to produce an output signal of a desired voltage. As a result, high speed and low current consumption are achieved. Next, the case where this effect is increased from E ₁ = 0.9 [V] to 3.0 [V] at once by the circuit of FIG. 6 or FIG.
For simplicity, the P-type MOSFETs 201, 202, 2 in FIG.
04 and 205 all have the same conductance constant β _P and threshold voltage V _TP . Further, it is assumed that all N-type MOSFETs 203 and 206 have the same conductance constant β _N and threshold voltage V _TN . At this time, a problem in operation is that the input signal terminal 207 changes from low (0) to high (E ₁ =
0.9 [V]), the N-type MOSFET 20
Of course, the P-type MOSFET 20 is turned on.
2 is not turned off because V _GS −V _TH = (3.0−0.9) −0.6> 0. At this time, a situation occurs in which the P-type MOSFET and the N-type MOSFET compete with each other. Consider this competition as a comparison of the difference between the driving capabilities of the N-type and P-type MOSFETs in the initial state where the signal has changed, as follows. At this time, since the N-type MOSFET 203 operates in the saturation region, the equivalent resistance R _N1 is R _N1 = 2E ₂ / β _N (E ₁ −V _TN ) ^2. R _P2 becomes R _P2 = 1 / β _P (E ₂ −E ₁ −V _TP ). Here, (E ₂ −E ₁ −V _TP ) = (3.0−
0.9-0.6)> 0. Also, P-type MOSFET
Since 201 is an operation in the unsaturated region, the equivalent resistance R _P3 is R _P3 = 1 / β _P (E ₂ −0−V _TP ) = 1 / β _P (E ₂ −
V _TP ). Here, the limit of whether or not the level shift circuit operates normally is generally quite difficult.
A comparison of the driving capability of the type MOSFETs will be made by replacing the driving capability with an equivalent resistance that is inversely proportional to the driving capability. The judgment formula of the limit is considered as follows.

[0030] R _N1 <R _P2 + if R _P3, or if the solved by substituting the equation _{A = 2E 2 (E 2 -E} 1 -V TP) · (E 2 -V TP) B = (E ₁ −V _TN ) ² · {2 (E ₂ −V _TP ) −E ₁ }, β _N / β _P > A / B is a determination formula of the limit of whether or not the level shift circuit operates normally. .

Now, E ₁ = 0.9 [V] and E ₂ = 3.0.
If [V], V _TP = 0.6 [V], and V _TN = 0.6 [V], β _N / β _P > 61.5. Also, in manufacturing, the threshold voltage usually fluctuates about 0.1 [V], so that the worst conditions are taken into account, so that E ₁ = 0.9 [V], E ₂ = 3.0 [V], and V _TP =
If 0.7 [V] and V _TN = 0.7 [V], then β _N / β _P > 130.5. Normally identical N-type MOSFET and P-type M
Since the β ratio with the OSFET is about 3, to achieve the above β ratio, it is necessary to change the shape of the P-type MOSFET and the N-type MOSFET by about 20 to 40 times to make a difference in the driving capability. Originally, a P-type M
It is desirable that the OSFET and the N-type MOSFET have a good balance in drive capability for high-speed response and characteristics of low current consumption. Therefore, although the shape can be secured by custom design that can freely design the shape of the MOSFET,
If the β ratio is unbalanced, the response and the characteristics of current consumption are adversely affected. Also, in the case of a gate array, in which the above-mentioned abnormal β ratio is achieved by connecting P-type MOSFETs in series as shown in FIG. 7, 701, 702, 7 in FIG.
P-type MOSFETs 20 to
This means that 40 are required. Therefore, in the system shown in FIG. 7, series connection is required at four locations, so that 80 to 160 P-type MOSFETs and 3 N-type MOSFETs are required.
Need. On the other hand, in the circuit system of FIG. 1 of the present invention, 20 P-type MOSFETs and 9 N-type MOSFETs are used. Therefore, in order to realize the level shift circuit of the specification of this example in the gate array system, it can be understood that the circuit system of the present invention can be achieved with an overwhelmingly small number of MOSFETs as compared with the conventional system. The conventional method shown in FIG.
Not only does a large number of FETs be required, but also competition occurs during the transition of the signal transition. Therefore, the circuit system of the present invention has better responsiveness and characteristics of low current consumption. In addition, since no competition occurs in the present invention, it can be seen that the circuit has stable characteristics and is resistant to manufacturing variations.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. FIG. 2 differs from FIG. 1 in the configuration of a MOS diode power supply circuit 305 surrounded by a chain line. In FIG. 1, the power supply of each basic level shift circuit is taken out from three MOS diode circuits connected in series. In FIG. 3, however, serial MOS diodes 318, 319 and 320 having different numbers of stages are provided separately, The point is that the power supply potential is separately supplied to the level shift circuit. Although the number of MOSFETs is slightly increased in the circuit system of FIG. 3, the current supply capability of the MOS diode power supply circuit is increased, and thus the circuit system is effective when pursuing higher-speed response.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.
It is. 3 differs from FIG. 1 in the polarity on the multiple power supply side.
Therefore, P-type MOSFET and N-type MOSFET
Is reverse to that of FIG. The configuration is the opposite,
The operating principle and effects are the same. In the embodiment of FIG.
Numerical examples show cases where the same is done with conventional circuits.
Assuming that FIG. 4 is the same as the conventional example,
Judgment formula for limit of whether or not bell shift circuit operates normally
Given that -E₁= -0.9 [V], -E_Two= -3.0
[V], V_TP= 0.6 [V], V_TN= 0.6 [V]
Then β_P/ Β_N > 61.5. In manufacturing, the threshold voltage is
About 0.1 [V] usually varies, so consider the worst conditions.
Then -E₁= -0.9 [V], -E_Two= -3.0
[V], V_TP= 0.7 [V], V_TN= 0.7 [V]
Then β_P/ Β_N > 130.5. Here, the numerical value on the right side of the inequality is the same as the calculation example in FIG.
Same but β on the left _PAnd β_NDenominator and numerator between
The relationship has been reversed. Normal same as above
Β ratio of N-type MOSFET and P-type MOSFET
In this case, about 3 is required to achieve the above β ratio.
Is 180 to 3 for P-type MOSFET and N-type MOSFET
It is necessary to change the shape by about 60 times to make a difference in driving capacity
Yes, the disparity widens. Therefore, the present invention as shown in FIG.
It is more effective when the signal voltage to be converted is negative.
I understand.

Although FIGS. 1, 3 and 4 show an example in which there are four basic level shift circuits, the number of stages is three depending on the specifications.
In some cases, the number of stages is less than or equal to five.

Although FIGS. 1, 3 and 4 show examples in which the basic level shift circuit of FIG. 2 is used, the essence of the present invention is to repeat a reasonable conversion between voltages. The configuration of the shift circuit is not necessarily limited to FIG. As shown in FIG. 5 in the conventional example, the basic level shift circuit has many other circuits and is effective.

Further, FIGS. 1, 3, when showed inverter circuit to make an inverted signal of the input signal terminal 111 of the E ₁ series in Figure 4, the inverted signal thereof is supplied by a pair originally input signal A It is not necessary.

Further, in the embodiment of FIG. 1, the case where no contention occurs completely at the time of signal transition has been described. However, if a moderate voltage drop occurs due to the MOS diode power supply circuit of the circuit system of the present invention, Even if some competition occurs, much better characteristics than the conventional circuit can be expected.

In FIGS. 1, 3 and 4, a MOS diode power supply circuit is a MOSFE having a gate and a drain connected.
It is configured by connecting MOS diode circuits by T in series in multiple stages, and adopts a method of causing a voltage drop. However, the essence of the function of the MOS diode power supply circuit is to cause an appropriate voltage drop. Other MOSFET
Is also possible. Further, it may be realized by resistance means.

In the embodiments shown in FIGS. 1, 3 and 4, the case where no conflict occurs completely is described.
The shape of T can be applied to existing gate arrays irrespective of the shape.

[0040]

As described above, according to the present invention, it is possible to provide a level shift circuit having a low voltage, a high speed even with a large potential difference to be converted, and a low current consumption.

During the conversion operation, the P and N MOs are changed.
Since the circuit configuration does not compete between the SFETs, there is an effect that a combination of existing MOSFETs such as a gate array can be easily configured.

Therefore, there is an effect that a level shift circuit can be built in even an existing gate array, and it is possible to cope with multiple power supplies.

Further, since the circuit system can be realized by an existing gate array, there is an effect that various specifications can be dealt with only by changing the wiring layer.

Further, as compared with a case where a gate array is used in a conventional circuit system, the number of transistors is extremely small,
There is an effect that a level shift circuit having good characteristics can be provided.

During the conversion operation, the P and N MOs
Since the circuit configuration does not compete between the SFETs, the operation is stable, and there is an effect of being resistant to manufacturing variations.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a basic level shift circuit used in the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional level shift circuit.

FIG. 6 is a circuit diagram of a conventional level shift circuit.

FIG. 7 is a circuit diagram of a conventional level shift circuit.

[Explanation of symbols]

101, 102, 103, 104, 401, 402, 4
03, 404... Basic level shift circuit 105, 305, 318, 319, 320.
OS diode power supply circuit 106, 107, 108, 109, 201, 202, 2
04, 205, 410 ... P-type MOS diodes 110, 203, 206, 405, 406, 407, 4
08, 409: N-type MOSFETs 111, 112, 207, 411, 413: Input signal terminals 113, 208, 412: Inverted input signal terminals 114, 209, 415: Output signal terminals 115, 210 , 414 ... inverted output signal terminals 116, 416 ... first power supply 117, 211, 417 ... second power supply 118, 212, 418 ... ground (third power supply) 701, 702, 704, 705 ... P-type MOSFETs connected in series

Claims (4)

[Claims] 1. A multi-level having a first power supply having a first potential of a first polarity, a second power supply having a second potential of a first polarity, and a third power supply of a second polarity. A shift circuit having an input signal terminal and an inverted input signal terminal, and an output signal terminal and an inverted output signal terminal; receiving a low-voltage input signal at the input signal terminal and the inverted input signal terminal; It has a level conversion function of outputting a voltage signal to the output signal terminal and the inverted output signal terminal, and has an insulated gate field effect transistor (Metal Oxide Sem).
Icon Field Effect T
N (where N is an integer of 2 or more) basic level shift circuits, each of which is composed of a combination of transistors (hereinafter abbreviated as MOSFETs), and a MOS diode (hereinafter, referred to as a MOSFET) in which a gate electrode and a drain electrode of the first polarity MOSFET are connected to each other. N-1) MOS diode power supply circuits connected in series and taking out potentials from respective drain electrodes, respectively. The power supply side of the first basic level shift circuit of the N basic level shift circuits Is connected to a drain electrode in which (N-1) MOS diodes in the MOS diode power supply circuit are connected in cascade, a signal of a first power supply system is connected to an input signal terminal, and an inverted input signal terminal Is connected to the inverted signal of the above signal, and the K-th signal (2 ≦
The drain side of the MOS diode power supply circuit in which (N−K) MOS diodes are connected in cascade is connected to the power supply side of the basic level shift circuit of (K ≦ N−1). The output signal terminal of the (-1) th basic level shift circuit is connected, the inverted output signal terminal of the (K-1) th basic level shift circuit is connected to the inverted input signal terminal, and the Nth basic level shift circuit is connected. The second power supply is connected to the power supply side of the level shift circuit, the output signal terminal of the (N-1) th basic level shift circuit is connected to the input signal terminal, and the (N-
The inverted output signal terminal of the 1) th basic level shift circuit is connected, and the output signal terminal and the inverted output signal terminal of the Nth basic level shift circuit are the final output signal terminal and the inverted output signal terminal, respectively. A multistage level shift circuit characterized by the above-mentioned. 2. The multi-level level shift circuit according to claim 1, wherein said basic level shift circuit comprises: a first MOSFET having a first polarity, a second MOSFET having a first polarity, and a third MOSFET having a second polarity. And a fourth MOSFET having a first polarity and a first MOSFET connected in series.
And the fifth MOSFET having the second polarity and the sixth MO having the second polarity.
SFET and the first MOSFET are connected in series.
And the source electrode of the fourth MOSFET are connected to each other to form a power supply system of a first polarity, and
ET and the source electrode of the sixth MOSFET are connected to each other to form a second polarity power supply system, and the second M
The OSFET and the gate electrode of the third MOSFET are connected to each other to serve as an input signal terminal, and the fifth M
The OSFET and the gate electrode of the sixth MOSFET are connected to each other to become an inverted input signal terminal,
And the drain electrode of the third MOSFET are connected to each other to form an inverted output signal terminal, and the drain electrode of the fifth MOSFET and the sixth MOSFET are connected to each other to form an output signal terminal.
A multi-stage level shift circuit, wherein a gate electrode of the first MOSFET is connected to the output signal terminal, and a gate electrode of the fourth MOSFET is connected to the inverted output signal terminal. 3. The multi-stage level shift circuit according to claim 1, wherein a number N of said basic level shift circuits used, and a MOSFET of a first polarity used for said basic level shift circuit and a MOS diode. Wherein the product of the threshold voltage and the threshold voltage is larger than the difference between the potential of the second power supply and the potential of the first power supply. 4. The basic level shift circuit and the MOS diode power supply circuit in the multi-stage level shift circuit according to claim 1, each having the same size as a basic cell built in a gate array semiconductor device or a master slice semiconductor device. P-type or N-type MOS
A semiconductor device characterized by being realized using an FET.