JP4431319B2 - LCD drive circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal driving circuit for driving data electrodes of a liquid crystal display device.
[0002]
[Prior art]
The data electrode (common electrode) of the liquid crystal display device is driven by inverting the polarity for each frame of the image signal in order to extend the life of the liquid crystal.
[0003]
FIG. 5 is a block diagram showing a configuration example of a conventional liquid crystal driving circuit for driving data electrodes. 1 is a data signal input terminal, 2 and 3 are inverters, and 4 is a level shifter for converting a logic voltage into a liquid crystal drive voltage level. A drive control circuit 5 includes an inverter 51, an AND gate 52, NAND gates 53, 54, 55, and NOR gates 56, 57. 58 is an input terminal for the frame signal FR for selecting the polarity of the lighting level voltage and the non-lighting level voltage, and 59 is an input terminal for the display signal DISP for setting the output to high impedance. Reference numeral 6 denotes a switch circuit that outputs a PMOS transistor 61 that outputs a lighting level voltage VDD, a PMOS transistor 62 that outputs a non-lighting level voltage V2 (V2 <VDD), and a non-lighting level voltage V3 (V3 <V2). And an NMOS transistor 64 for outputting the lighting level voltage VSS. Reference numeral 7 denotes an output terminal for outputting a voltage to the data electrode (common electrode) of the liquid crystal display device.
[0004]
FIG. 6 is an operation waveform diagram of the circuit of FIG. When the data signal IN is input to the terminal 1, the data signal DATAb having the same phase as that of the data signal IN appears from the level shifter 4 and is input to the drive control circuit 5. In the drive control circuit 5, during the display operation, the frame signal FR of the terminal 58 repeats “H” and “L” every frame, and the display signal DISP of the terminal 59 continues to be “H”.
[0005]
Therefore, when the signal FR is “H”, when the signal DATAb is “H” and the signal DATA is “L”, the output P1 of the NAND gate 54 is “L”, the output P2 of the NAND gate 55 is “H”, and the NOR gate 56 57, the outputs P3 and P4 are "L", only the PMOS transistor 61 of the switch circuit 6 is turned on, and the voltage VDD is output to the output terminal 7.
[0006]
Next, when the signal DATAb becomes “L” and the signal DATA becomes “H”, the output P1 of the NAND gate 54 is “H”, the output P2 of the NAND gate 55 is “L”, and the outputs P3 and P4 of the NOR gates 56 and 57 are “ L ", only the PMOS transistor 62 of the switch circuit 6 is turned on, and the voltage V2 is output to the output terminal 7.
[0007]
Next, when the signal FR is “L”, when the signal DATAb is “H” and the signal DATA is “L”, the outputs P1 and P2 of the NAND gates 54 and 55 are “H”, and the output P3 of the NOR gate 56 is “H”, the output P 4 of the NOR gate 57 becomes “L”, and only the PMOS transistor 63 of the switch circuit 6 is turned on, and the voltage V 3 is output to the output terminal 7.
[0008]
Next, when the signal DATAb becomes “L” and the signal DATA becomes “H”, the outputs P1 and P2 of the NAND gates 54 and 55 are “H”, the NOR gate 56 output P3 is “L”, and the NOR gate 57 output P4 is “H”. Thus, only the PMOS transistor 64 of the switch circuit 6 is turned on, and the voltage VSS is output to the output terminal 7.
[0009]
Hereinafter, when the input signal IN and the signal FR repeat the same change, a voltage whose polarity is inverted every time the signal FR is output is output to the output terminal 7. However, if the timing of the signal IN and the signal FR is different, The timing of the polarity change is also different.
[0010]
[Problems to be solved by the invention]
However, in the liquid crystal drive circuit of FIG. 5, if the data signal DATAb and the data signal DATA output from the level shifter 4 are not in an accurate reverse phase relationship, a period in which the PMOS transistors 61 and 62 are simultaneously turned on occurs, or the NMOS transistor A period during which 63 and 64 are simultaneously turned on occurs, and a through current flows therethrough, which causes a problem of increasing power consumption.
[0011]
For example, when the data signal DATAb is delayed from the data signal DATA, a period in which the signals P1 and P2 are simultaneously “L” occurs at the timing a in FIG. 6 and the PMOS transistors 61 and 62 are simultaneously turned on. A through current flows through (FIG. 7A). Further, at timing b in FIG. 6, a period in which the signals P3 and P4 are simultaneously “H” occurs, and the NMOS transistors 63 and 64 are simultaneously turned on, and a through current flows between them (FIG. 7B).
[0012]
Further, in contrast to the above, when the data signal DATA is behind the data signal DATAb, there is a period in which the signals P1 and P2 are simultaneously “L” at the timing c in FIG. 6, and the PMOS transistors 61 and 62 are simultaneously connected. And a through current flows during that time (FIG. 7 (c)). Further, at timing d in FIG. 6, a period in which the signals P3 and P4 are simultaneously “H” occurs, and the NMOS transistors 63 and 64 are simultaneously turned on, and a through current flows between them (FIG. 7 (d)).
[0013]
An object of the present invention is to provide a liquid crystal driving circuit that reduces power consumption by preventing the above-described through current from flowing.
[0014]
[Means for Solving the Problems]
According to the first aspect of the present invention, the gate of the first NMOS transistor is connected to the output terminal of the first CMOS inverter in which the high potential power supply terminal is connected to the high potential power supply via the first inversion circuit, and the low potential power supply is connected. A second NMOS transistor is connected to the output side of the second CMOS inverter whose terminal is connected to the low-potential power supply via a first non-inverting circuit, and the low-potential power supply terminal of the first CMOS inverter is connected to the second CMOS inverter. Connected to the output terminal of the first CMOS inverter, the high potential power supply terminal of the second CMOS inverter is connected to the output terminal of the first CMOS inverter, and the input terminals of the first and second CMOS inverters are shared. connect, unlit level conductive to the other of the drain applied with a lighting level voltage to one of the drain of the first and second NMOS transistors It was applied, and was the source of the first and second NMOS transistors and a common connection to the output side, and a liquid crystal driving circuit, characterized in that.
[0015]
According to the second aspect of the present invention, the gate of the first PMOS transistor is connected to the output terminal of the third CMOS inverter in which the high potential power supply terminal is connected to the high potential power supply via the second non-inverting circuit, A second PMOS transistor is connected to the output side of the fourth CMOS inverter whose power supply terminal is connected to a low potential power supply via a second inverting circuit, and the low potential power supply terminal of the third CMOS inverter is connected to the fourth CMOS inverter. Connected to the output terminal of the CMOS inverter, the high-potential power supply terminal of the fourth CMOS inverter is connected to the output terminal of the third CMOS inverter, and the input terminals of the third and fourth CMOS inverters are shared. connect, unlit level conductive to the other of the drain applied with a lighting level voltage to one of the drain of the first and second PMOS transistors It was applied, and was the source of the first and second PMOS transistors and a common connection to the output side, and a liquid crystal driving circuit, characterized in that.
[0016]
According to a third aspect of the present invention, the first inversion circuit is composed of an odd number of inverter rows whose final stage is a first gate having an inverter function, and the first non-inversion circuit is an inverter at the final stage. 2. The liquid crystal driving circuit according to claim 1, wherein the liquid crystal driving circuit is configured by an even number of inverter rows serving as second gates having a function, and a data signal is input to input terminals of the first and second CMOS inverters. The second non-inverting circuit is composed of an even number of inverter rows whose final stage is a third gate having an inverter function, and the second inverting circuit is a final gate having a fourth gate having an inverter function. 3. The liquid crystal driving circuit according to claim 2, wherein the liquid crystal driving circuit is configured by an odd number of inverter rows and a data signal obtained by inverting the data signal is input to input terminals of the third and fourth CMOS inverters. And the first and second gate groups and the third and fourth gate groups are controlled so that one of them is alternately activated by a frame signal for selecting the polarity of the lighting level and the non-lighting level. The liquid crystal driving circuit is characterized by the above.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
FIG. 1A is a block diagram showing the configuration of the liquid crystal driving circuit according to the first embodiment of the present invention, which prevents a through current when the NMOS transistors 91 and 92 are driven. The drains of the transistors 91 and 92 are connected to the output terminal 93, and the output terminal 93 is connected to the data electrode of the liquid crystal display device. One of the source voltages Va and Vb of the transistors 91 and 92 is a lighting level voltage, and the other is a non-lighting level voltage.
[0018]
81 and 82 are CMOS inverters. The CMOS inverter 81 is composed of a PMOS transistor 81P and an NMOS transistor 81N each having a common gate and drain, and the CMOS inverter 82 is composed of a PMOS transistor 82P and an NMOS transistor 82N each having a common gate and drain. The source of the transistor 81P is connected to the power supply of the voltage VDD, the source of the transistor 81N is connected to the common drain node N2 of the transistors 82P and 82N, and the source of the transistor 82P is connected to the common drain node N1 of the transistors 81P and 81N. The source of the transistor 82N is connected to the power source of the voltage VSS.
[0019]
Reference numeral 83 denotes an odd-numbered inverter train (inverter circuit) in which CMOS inverters are cascaded in odd-numbered stages, connected between the nodes N1 and N3, and the node N3 is connected to the gate of the NMOS transistor 91. Reference numeral 84 denotes an even-numbered inverter train (non-inverting circuit) in which inverters are cascade-connected, and is connected between the node N2 and the node N4, and the node N4 is connected to the gate of the NMOS transistor 92.
[0020]
In the liquid crystal drive circuit shown in FIG. 1A, as shown in FIG. 1B, when the data signal IN input to the input terminal 1 ′ rises to “H”, the transistors 81N and 82N are turned on. The voltage of the node N1 at the drain of the transistor 81N is slightly delayed because the node N2 at the drain of the transistor 82N falls to “L” after falling to “L” (= VSS). When the signal IN input to the input terminal 1 ′ falls to “L”, the transistors 81P and 82P are turned on. The voltage at the drain node N2 of the transistor 81P is “H” at the drain node N1 of the transistor 82P. ”(= VDD) and then rises to“ H ”, so that there is a slight delay.
[0021]
Therefore, the voltages of the nodes N1 and N2 and the voltages of the nodes N3 and N4 via the inverter trains 83 and 84 have waveforms as shown in FIG. 1B. In particular, the voltages of the nodes N3 and N4 are “H”. There are no overlapping periods. For this reason, the NMOS transistors 91 and 92 are not simultaneously turned on, and the power consumption due to the through current can be reduced.
[0022]
[Second Embodiment]
FIG. 2A is a block diagram showing the configuration of the liquid crystal driving circuit according to the second embodiment of the present invention, in which a through current when the PMOS transistors 94 and 95 are driven is prevented. The drains of the transistors 94 and 95 are connected to the output terminal 96, and the output terminal 96 is connected to the data electrode of the liquid crystal display device. One of the source voltages Vc and Vd of the transistors 94 and 95 is a lighting level voltage, and the other is a non-lighting level voltage.
[0023]
Reference numerals 85 and 86 denote CMOS inverters, which have the same connection relationship as the CMOS inverters 81 and 82 described above. Reference numeral 87 denotes an even-numbered inverter row (non-inverting circuit) in which even-numbered CMOS inverters are connected in cascade, and is connected between nodes N5 and N7, and the node N7 is connected to the gate of the PMOS transistor 94. Reference numeral 88 denotes an odd-numbered inverter string (inverter circuit) in which CMOS inverters are cascade-connected to odd-numbered stages, connected between nodes N6 and N8, and the node N8 is connected to the gate of the PMOS transistor 95.
[0024]
As shown in FIG. 2B, the liquid crystal driving circuit shown in FIG. 2A is configured so that the data signal IN input to the input terminal 1 ′ rises to “H” and falls to “L”. The CMOS inverters 85 and 86 perform the same operation as the CMOS inverters 81 and 82, and the voltages at the nodes N5 and N6 have the same waveforms as the voltages at the nodes N1 and N2 of the liquid crystal driving circuit in FIG. The output nodes N7 and N8 of the inverter arrays 87 and 88 have a reverse relationship to the voltages at the nodes N3 and N4 in FIG. 1A, and there is no overlap between the “L” periods. For this reason, the PMOS transistors 63P and 64P are not simultaneously turned on, and the power consumption due to the through current can be reduced.
[0025]
[Third Embodiment]
FIG. 3 is a block diagram in which a circuit similar to the liquid crystal driving circuit described in FIG. 5 is configured by applying the liquid crystal driving circuit of FIGS. 1 (a) and 2 (a). Here, the PMOS transistors 61 and 62 correspond to the PMOS transistors 94 and 95 in FIG. 2A, the NMOS transistors 63 and 64 correspond to the NMOS transistors 91 and 92 in FIG. 1A, and the NAND gate 54 in FIG. 2A corresponds to the final-stage inverter of the even-numbered inverter train 87, the NAND gate 55 corresponds to the final-stage inverter of the odd-numbered inverter train 88 in FIG. 2A, and the NOR gate 56 corresponds to FIG. The NOR gate 57 corresponds to the odd-numbered inverter row 83, and the NOR gate 57 corresponds to the even-numbered inverter row 84 in FIG.
[0026]
As described above, even when the data signals DATAb and DATA output from the level shifter 4 are phase-shifted by incorporating the liquid crystal driving circuit shown in FIGS. 1 (a) and 2 (a), FIG. As shown in a), the data signals DATA1b and DATA1 input to the NAND gates 51 and 52 do not become “H” at the same time, so that the signals P1 and P2 do not become “L” at the same time. The PMOS transistors 61 and 62 are not turned on at the same time.
[0027]
Similarly, as shown in FIG. 4B, the data signals DATA2b and DATA2 input to the NOR gates 51 and 52 do not become “L” at the same time, so that the signals P3 and P4 become “H” at the same time. The NMOS transistors 63 and 64 of the switch circuit 6 are not simultaneously turned on. Therefore, power consumption due to the through current can be reduced.
[0028]
【The invention's effect】
As described above, according to the present invention, there is an advantage that it is possible to prevent a through current of a transistor constituting the switch circuit and to reduce power consumption.
[Brief description of the drawings]
1A is a block diagram of a liquid crystal driving circuit according to a first embodiment of the present invention, and FIG. 1B is an operation waveform diagram thereof.
2A is a block diagram of a liquid crystal driving circuit according to a second embodiment of the present invention, and FIG. 2B is an operation waveform diagram thereof.
FIG. 3 is a block diagram of a liquid crystal driving circuit according to a third embodiment of the present invention.
4A and 4B are operation waveform diagrams of the liquid crystal driving circuit of FIG.
FIG. 5 is a block diagram of a conventional liquid crystal driving circuit.
6 is an operation waveform diagram of the liquid crystal driving circuit of FIG. 5. FIG.
7 is a waveform diagram for explaining through current generated in the liquid crystal drive circuit of FIG. 5; FIG.
[Explanation of symbols]
1, 1 ': Data input terminal 2, 3: Inverter 4: Level shifter 5: Drive control circuit 6: Switch circuit 7: Output terminals 81, 82, 85, 86: CMOS inverters 83, 88: Odd stage inverter rows 84, 87 : Even-numbered inverter train

Claims (3)

The gate of the first NMOS transistor is connected to the output terminal of the first CMOS inverter having the high potential power supply terminal connected to the high potential power supply through the first inversion circuit,
A second NMOS transistor is connected to the output side of a second CMOS inverter having a low potential power supply terminal connected to the low potential power supply through a first non-inverting circuit;
A low potential power supply terminal of the first CMOS inverter is connected to an output terminal of the second CMOS inverter; a high potential power supply terminal of the second CMOS inverter is connected to an output terminal of the first CMOS inverter; And commonly connecting the input terminals of the first and second CMOS inverters;
A lighting level voltage is applied to one drain of the first and second NMOS transistors, a non-lighting level voltage is applied to the other drain, and the sources of the first and second NMOS transistors are connected in common. The output side
A liquid crystal drive circuit characterized by that. The gate of the first PMOS transistor is connected to the output terminal of the third CMOS inverter having the high potential power supply terminal connected to the high potential power supply through the second non-inverting circuit;
A second PMOS transistor is connected to the output side of the fourth CMOS inverter having the low-potential power supply terminal connected to the low-potential power supply through a second inversion circuit;
Connecting the low potential power supply terminal of the third CMOS inverter to the output terminal of the fourth CMOS inverter, connecting the high potential power supply terminal of the fourth CMOS inverter to the output terminal of the third CMOS inverter; And connecting the input terminals of the third and fourth CMOS inverters in common,
A lighting level voltage is applied to one drain of the first and second PMOS transistors, a non-lighting level voltage is applied to the other drain, and the sources of the first and second PMOS transistors are connected in common. The output side
A liquid crystal drive circuit characterized by that. The first inverting circuit is composed of an odd number of inverter rows whose final stage is a first gate having an inverter function, and the first non-inverting circuit is a second gate having an inverter function as a final stage. 2. The liquid crystal driving circuit according to claim 1, wherein the liquid crystal driving circuit is configured by an even number of inverter rows and a data signal is input to input terminals of the first and second CMOS inverters.
The second non-inverting circuit is composed of an even number of inverter rows whose final stage is a third gate having an inverter function, and the second inversion circuit is a final gate having an inverter function. 3. The liquid crystal driving circuit according to claim 2, wherein the liquid crystal driving circuit is configured by an odd number of inverter rows and a data signal obtained by inverting the data signal is input to input terminals of the third and fourth CMOS inverters,
Comprising
The first and second gate sets and the third and fourth gate sets are controlled so that one of them is alternately activated by a frame signal for selecting the polarity of the lighting level and the non-lighting level.
A liquid crystal drive circuit characterized by that.

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