JP4430117B2 - Data storage device - Google Patents

Description

  The present invention relates to a two-wire data communication method and system between a data storage device and a control device in a contact type data storage system, and a control device, system, control device and data storage device.

  The contact data storage system is used for component management of OA equipment and process management at the factory, etc. In order to reduce the size of the system in communication between the data storage device and the control device that composes it, two-wire data Some employ a communication method (see, for example, Patent Document 1).

  FIG. 13 is a voltage waveform diagram for explaining a conventional two-wire data communication method, and FIG. 14 is a block diagram showing a configuration example of a contact data storage system using the conventional two-wire data communication method. . In FIG. 14, the contact type data storage system includes a control device 1201 and a data storage device 1202.

  The control device 1201 includes a clock generation circuit 1205 that forms a clock pulse and its reverse phase pulse, a voltage level generation circuit 1203 that generates an amplitude level of the clock pulse, and a first that changes the amplitude of the clock pulse in accordance with the transmission signal. A transmission circuit 1204 and a first signal detection circuit 1206 for detecting an amplitude difference appearing in the clock pulse and its opposite phase pulse are provided.

  Further, the data storage device 1202 includes a rectifier circuit 1208 for full-wave rectification of the voltage from the clock pulse and its reverse phase pulse, a data demodulator circuit 1209 for detecting the amplitude difference of the clock pulse and reproducing the transmission signal, and a two-wire type A second transmission circuit 1210 that changes the voltage amplitude by changing the load impedance between the communication terminals according to the transmission signal, and a clock detection circuit 1211 that regenerates the clock pulse are provided.

  The voltage level generation circuit 1203 includes a resistor R1 connected to the power supply voltage + V and a resistor R2 connected in series with the resistor R1, and outputs a voltage Vout at a connection point between the resistor R1 and the resistor R2. The transmission circuit 1204 is composed of a MOS transistor in which a source and a drain are connected to the resistor R2 of the voltage level generation circuit 1203 and the reference potential GND, respectively, and a transmission signal is input to the gate, and the output level Vout of the voltage level generation circuit 1203 is obtained. decide.

  The clock generation circuit 1205 is composed of two inverters, and outputs in-phase and anti-phase clock pulses with respect to the clock signal input. The power supply terminal of each inverter is connected to the output Vout of the voltage level generation circuit 1203, and the transmission signal is superimposed on the clock pulse by changing the amplitude of the in-phase and anti-phase clock pulse outputs according to the output Vout. Communicate to data storage device 1202.

  In the data storage device 1202 that receives the clock pulse and its reverse phase pulse, the data demodulation circuit 1209 extracts a signal component superimposed on the voltage rectified by the rectifier circuit 1208. The clock detection circuit 1211 is composed of an inverter, reproduces a clock pulse regardless of the superimposed signal component, and uses it as a clock for the data storage device 1202.

  The second transmission circuit 1210 is configured by connecting a resistor and a switch in series between the two-wire communication terminals of the data storage device 1202, and changing the load impedance between the terminals according to the transmission signal, thereby controlling the control device. The amplitude of the clock pulse received from 1201 is changed. The signal detection circuit 1206 is connected to one of the two-wire communication terminals in the control device 1201, and detects a change in the amplitude of the clock pulse at these terminals as a received signal.

  FIG. 15 is a circuit diagram showing the data demodulation circuit 1209, and its operation will be described with reference to the voltage waveform diagram of FIG. First, a voltage waveform on which a signal as shown in FIG. 13E, which is the output of the rectifier circuit of the data storage device, is superimposed is input to the low-pass filter 1301, and noise caused by skew or the like is removed. Next, the high-pass filter 1302 detects rising and falling edges of the signal and removes the DC component of the signal as shown in FIG.

  Further, the comparator 1303 with hysteresis outputs the internal power supply voltage level, that is, the logic “H” when the output of the high-pass filter 1302 exceeds the high hysteresis level as shown in FIG. When the voltage is further lowered, the internal reference voltage level, that is, the logic “L” is output. Finally, the D flip-flop 1304 detects the output of the comparator 1303 at the falling edge of the output of the clock detection circuit as shown in FIG.

  As described above, the conventional data communication method performs data communication by superimposing a transmission signal component as a change in amplitude on a transmission clock. In this manner, signals are transmitted and received mutually, and at the same time, power and clock are supplied from the control device to the data storage device.

JP 2003-69653 A

  However, in the above conventional method, as shown in FIG. 13, when a timing skew exists between a clock pulse and its opposite phase pulse, noise is generated in the internal power supply voltage after rectification. At this time, if the operation of the internal circuit such as the built-in memory overlaps, the drop in power supply noise becomes large, and the data demodulating circuit performs erroneous data demodulation as shown in FIGS. 13 (e) to 13 (h). There was a thing.

  This phenomenon occurs more frequently as the timing skew between the clock pulse and the opposite-phase pulse increases, so that it is necessary to adjust the timing severely in the control device and the transmission line of the two-wire communication.

  Furthermore, since the data is superimposed on the clock pulse by amplitude modulation and transmitted from the control device, a ternary output voltage level is required, so that the circuit configuration of the control device is complicated and the internal circuit of the data storage device The burden of system design has become quite large, such as the need to adjust the output voltage level in consideration of variations in equivalent resistance.

  The present invention solves the above-described conventional problems. In the two-wire data communication in which data communication and clock and power supply are performed between the control device and the data storage device through the first and second signal lines, It is an object of the present invention to provide a two-wire data communication method, system, control device, and data storage device that enable stable communication without data demodulation errors due to the effect of inter-skew and reduce the design burden of the control device.

  The present invention is a data storage device for extracting data from a received clock, wherein a first input terminal to which a first signal, which is a clock pulse, is input, and data is input to a clock pulse having a phase opposite to that of the clock pulse. A second input terminal to which the superimposed second signal is input, and the first input terminal and the second input terminal are connected, and an internal power supply voltage is obtained from the first signal and the second signal. A data storage device comprising: a rectifying circuit to be generated; and a data demodulating circuit connected to the first input terminal and the second input terminal and extracting the data from the first signal and the second signal I will provide a.

  In the data storage device, the second signal is a full amplitude signal representing the data by the presence or absence of a clock pulse.

  In the data storage device, the second signal is a full amplitude signal representing the data with a plurality of delay times.

  In the data storage device, the second signal is a full amplitude signal representing the data with a plurality of duty ratios.

  In the data storage device, the second clock is a full amplitude signal representing the time position of the pulse signal on which the data is superimposed.

  The data storage device includes a smoothing capacitor connected to the rectifier circuit.

  As described above, according to the present invention, stable two-wire communication that does not cause data demodulation errors due to noise of the internal power supply voltage generated due to an increase in the skew between signals or the operation of the internal circuit of the data storage device can be achieved. Can be realized. Further, since the demodulator circuit of the data storage device can be easily configured, the cost merit is great. Furthermore, since the control device configuration does not require the three voltage values as in the conventional example, it is possible to reduce the design burden by eliminating the need for adjustment taking into account variations in the equivalent resistance of the data storage device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Since all the features of the present invention relate to communication at the time of data transmission from the control device to the data storage device, in the following embodiments, description of operations relating to data transmission from the data storage device to the control device is omitted. .

(Embodiment 1)
FIG. 1 is a voltage waveform diagram showing a two-wire data communication method according to Embodiment 1 of the present invention, and FIG. 2 is contact-type data using the two-wire data communication method according to Embodiment 1 of the present invention. It is a block diagram which shows the structural example of the data storage device in a storage system.

  The two-wire data communication method according to the present embodiment uses a first transmission signal that is a stable clock pulse shown in FIG. 1A and a data pulse superimposed on the clock pulse as shown in FIG. It consists of two transmission signals. In a section in which the transmission data has a certain logic ("1" in FIG. 1), the first transmission signal and the second transmission signal are in a relationship of clock pulses having opposite phases, and the transmission data is reversed. In the period of logic (“0” in FIG. 1), the clock pulse is not transmitted to the second transmission signal.

  In the data storage device that has received such a transmission signal, first, an internal operation voltage is generated from the first and second transmission signals by full-wave rectification, and a stable internal operation clock is generated based on the first transmission signal. Extract. Next, by detecting the presence or absence of the clock pulse of the second transmission signal using this internal operation clock, data demodulation can be easily performed as shown in FIG.

  The data storage device shown in FIG. 2 includes a rectifier circuit 208 for generating an internal power supply voltage from first and second transmission signals, a data demodulation circuit 211 for extracting received data from a control device, an internal power supply And a second transmission circuit 210 that is used when data is transmitted from the data storage device to the control device.

  The data demodulation circuit 211 extracts a stable clock pulse (FIG. 1 (a)) based on the first transmission signal and uses it as an operation clock to generate the second transmission signal (FIG. 1 (b)). Is directly latched in the D flip-flop to extract the demodulated data (FIG. 1 (e)).

  In order to simplify the description, the first and second transmission signals are directly input to the D flip-flop of the data demodulating circuit 211 in FIG. 2, but the first and second transmission signals are actually input. Therefore, an adjustment circuit for adjusting the voltage level and polarity and reproducing the signal is required. It goes without saying that a timing adjustment circuit may be required so as not to cause a hold error due to clock skew.

  Since the data demodulating circuit, which is a feature of the present embodiment, detects the presence / absence of a clock pulse of the second transmission signal as data using the first transmission signal as an internal operation clock, the first and second It is also possible to adopt a circuit configuration in which combinational logic data such as exclusive OR of the transmission signals is used as an input signal to the D flip-flop of the data demodulating circuit 211.

  Since the internal power supply voltage is generated by full-wave rectification in the rectifier circuit 208, when the data is “0” logic in the above embodiment, no pulse is transmitted to the second transmission signal, and power is supplied in a half cycle of the clock. A section that cannot be supplied occurs. Therefore, it is necessary to insert the smoothing capacitor 212 into the internal power supply circuit and maintain the power in this section.

As shown in FIG. 1D, the power supply voltage inside the data storage device when the first and second transmission signals are out of phase with each other is VDD, the interval during which power cannot be supplied is t0, and the internal circuit of the data storage device Assuming that the equivalent resistance value of R is R and the capacitance value of the internal power supply circuit is C, the power supply voltage value VDD1 after the elapse of t0 is given by
VDD1 = VDD × (exp (−t0 / RC))

  Therefore, the capacitance value C may be determined so that VDD1 does not fall below the minimum operating voltage of the internal circuit. When this value is small, there is a case that it can be covered only by the parasitic capacitance of the internal circuit without particularly inserting a capacitive element.

  Since the prior art was a demodulation method in which the edge of the signal was detected because the data was a small amplitude signal, there was a possibility that a demodulation error could easily occur due to fluctuations in the internal power supply voltage due to the skew between the signals. In this embodiment, since the data signal is a full-amplitude signal that represents the presence or absence of a clock pulse, it can be demodulated by a logic circuit without the need for an edge detection type demodulation method, and is affected by skew between signals. There is almost no possibility of demodulation error due to.

  In addition, the demodulating circuit of the data storage device can be easily configured as compared with the prior art, so that the cost merit is great. Furthermore, the configuration of the control device can also generate a second transmission signal with a simple logic circuit if there is a basic clock and transmission data, and data storage is not required because a ternary voltage value is not required as in the conventional example. The design burden can be reduced by eliminating the need for adjustments taking into account variations in the equivalent resistance of the device.

(Embodiment 2)
FIG. 3 is a voltage waveform diagram showing the two-wire data communication method according to the second embodiment of the present invention, and FIG. 6 is a contact data using the two-wire data communication method according to the second embodiment of the present invention. It is a block diagram which shows the structural example of the control apparatus in a storage system.

  The two-wire data communication method according to the present embodiment uses a first transmission signal that is a stable clock pulse shown in FIG. 3A and a data pulse superimposed on the clock pulse as shown in FIG. It consists of two transmission signals. The first transmission signal and the second transmission signal are in a relationship of clock pulses having opposite phases. When the transmission data has a certain logic ("1" in FIG. 3), the first transmission signal When the “H” pulse of the second transmission signal is advanced by the time td1 with respect to the “L” pulse and the transmission data has the reverse logic (“0” in FIG. 3), the second The “H” pulse of the transmission signal is a signal advanced by time td2.

  In the data storage device that has received such a transmission signal, first, an internal operation voltage is generated from the first and second transmission signals by full-wave rectification, and a stable internal operation clock is generated based on the first transmission signal. Extract. Next, by detecting a change in the delay time of the second transmission signal as a data signal using this internal operation clock, data demodulation can be easily performed as shown in FIG.

  The operation during this period will be further described with reference to FIGS. FIG. 4 is an example of a full-wave rectifier circuit for generating an internal operating voltage from the first and second transmission signals, and is composed of PchMOS transistors M1 to M4. FIG. 5 is a voltage waveform diagram for explaining the internal operation when the internal power source generated using the full-wave rectifier circuit having the configuration of FIG. 4 is used as a reference.

  First, in the full-wave rectifier circuit of FIG. 4, when an “H” voltage is applied to the second transmission signal input terminal and an “L” voltage is applied to the first transmission signal input terminal, the second transmission signal input terminal A current flows into the internal VDD through M2, and a current flows out from the internal Vss through the M3 to the first transmission signal input terminal. At this time, M1 and M4 are off.

  Next, when the voltage applied to the second transmission signal input terminal changes from “H” to “L”, the internal VDD potential is clamped to the second transmission signal terminal through M2, so the first, It is almost the same potential as the second transmission signal input terminal voltage (there is a difference of about Vt voltage of the M2 transistor). Since the voltage between the internal VDD and Vss is held for a certain period by the smoothing capacitor between the power supplies, the internal Vss potential is also lowered in accordance with the change in the voltage applied to the second transmission signal input terminal. For this reason, when the voltage change of the first and second transmission signal input terminals is seen with reference to the internal Vss potential, the first transmission signal input waveform changes from “L” to “H”. The second transmission signal input waveform remains “H”. Next, when the first transmission signal input terminal voltage changes from “L” to “H”, the second transmission signal input waveform when the internal Vss is used as a reference changes from “H” to “L”. Change.

  Next, from the state where the first transmission signal input terminal voltage is “H” and the second transmission signal input terminal voltage is “L” (M1 and M4 are on, and M2 and M3 are off), the second When the transmission signal input terminal voltage changes from "L" to "H", the internal VDD potential is clamped to the first transmission signal input terminal voltage through M1, and is almost the same potential (as much as the Vt voltage of the M1 transistor). Therefore, the second transmission signal input waveform when the internal Vss is used as a reference also changes from “L” to “H” as the terminal voltage changes. When the first transmission signal input terminal voltage changes from “H” to “L” from that state, the internal VDD potential is clamped to the second transmission signal input terminal voltage through M2, so that the internal Vss. As a reference, the first transmission signal input waveform also changes from “H” to “L”.

  FIG. 5 is a waveform diagram showing the operation described above. Signal waveforms when the first transmission signal waveform (a) and the second transmission signal waveform (b) are viewed with the internal Vss as a reference are (d) and (e), respectively. Here, the operation clock (g) is obtained by shaping the internal signal (d), and the demodulated data (h) is latched by latching the signal (f) obtained by delaying the internal signal (e) by Δd at this falling timing. ) Can be obtained. The delay time Δd may be set so that td1−Δd satisfies the setup time of the latch flip-flop, and | td2−Δd | (−td2 + Δd when td2 is a negative value) satisfies the hold time.

  In FIG. 5, the falling timing of the extracted operation clock (g) is synchronized with the falling timing of the first transmission signal waveform (a), but the falling timing of the signal waveform (e) and the first timing are the same. Since the rising timing of the transmission signal (a) is also synchronized, an operation clock may be generated from this signal waveform (e). In this case, demodulated data can be obtained at the rising timing of the first transmission signal (a) by latching a signal obtained by delaying the signal waveform (d) by Δd as data.

  In this embodiment, the rectifier circuit having the configuration shown in FIG. 4 is used. However, by changing the configuration of the rectifier circuit, the first transmission signal waveform (d) or the second waveform with reference to the internal Vss is used. Since the change timing of the transmission signal waveform (e) may differ from the present description, it is necessary to adjust the method of extracting each internal signal according to the configuration of the rectifier circuit.

  The circuit configuration of the data storage device in the present embodiment may be basically the same as that of the data storage device in the first embodiment shown in FIG. Data demodulation can be performed by latching the second transmission signal in the D flip-flop at the falling edge of the clock pulse, which is the transmission signal. Further, as described in the operation description of FIG. 5, a circuit for delaying the input signal to the D flip-flop by Δd is necessary.

  The control device shown in FIG. 6 generates a first transmission signal (FIG. 3A) by serially connecting three stages of inverter circuits with respect to the reference clock, and also has two stages of inverters with respect to the reference clock. Transistor for switching the wiring load of the inverter circuit to generate the second transmission signal (FIG. 3B) by connecting the circuits in series and to delay the second transmission signal by the logic of the data to be transmitted A switch 401 and a delay capacitor 402 are provided.

  In the control device configured as described above, first, a clock pulse that has passed through three stages of inverter circuits from the reference clock is output to the first transmission signal line. When the transmission data is logic “1”, the “L” voltage is applied to the gate of the transistor switch 401 to turn off the transistor switch 401, and the second transmission signal line passes through the inverter circuit in two stages from the reference clock. Clock pulse is output. At this time, the second transmission signal is output earlier by one inverter circuit (td1 in FIG. 3) than the first transmission signal.

  Next, when the transmission data is logic “0”, the “H” voltage is applied to the gate of the transistor switch 401, the transistor switch 401 is turned on, and the output wiring load of the first inverter circuit from the reference clock input is Increased by the delay capacitor 402. As a result, the output signal to the second transmission signal line is delayed by the delay capacitor 402 (corresponding to the time td1-td2 in FIG. 3), so that it is output earlier by td2 time than the first transmission signal output. Will be. In this way, the first transmission signal (a) and the second transmission signal (b) in FIG. 3 are generated.

  In this embodiment, the wiring load is changed by the transistor switch and the delay capacitor. However, the load by the wiring resistance or the load by the combination of the wiring resistance and the delay capacitor is switched by the transistor switch. May be.

  The time td1-Δd in FIG. 3 may be determined so as to satisfy the time specification of the setup time of the D flip-flop of the data demodulating circuit 211 in FIG. 2, and | td2-Δd | may be satisfied so as to satisfy the hold time of the D flip-flop. .

  Next, as compared with the first and second transmission signal generation by the normal logic circuit, the transmission signal is generated by the change of the signal delay time due to the change of the wiring load of the intermediate node of the signal as in the present embodiment Explain that there are advantages.

  The data storage device generates an internal operating power source by full-wave rectifying the first and second transmission signals. Therefore, when the first and second transmission signals are temporarily stopped with the same polarity, that is, when the signals are stopped in the state of the skews td1 and td2 in FIG. 3, the power supply voltage of the internal circuit is reduced. After that, even if the signal transmission is resumed, the process cannot be continued and it is necessary to start the process from the beginning.

  For example, when the first and second transmission signals are generated at the microcomputer output port and directly output, the microcomputer interrupt process occurs and the transmission signal to the data storage device is stopped for a certain period of time. Although it is often possible to restart the process, it is necessary to impose a condition that the first and second transmission signals must be stopped with opposite polarities when the process is temporarily stopped. growing.

  With the configuration of the control device of the present invention, even if the reference clock is stopped in the middle of communication, the first and second transmission signals are stopped with reverse polarity in the steady state after the signal delay time. Since the processing can be continued after the reference clock is restarted without the internal power supply voltage of the apparatus being lowered, there is an advantage that it is not necessary to place an extra burden on the microcomputer processing or the like.

  Since the internal power supply voltage is generated by full-wave rectification, time (td1, td2) during which power cannot be supplied due to the skew between the signals occurs. For this reason, it is necessary to maintain the power in this section by inserting a smoothing capacitor into the internal power supply. The method of determining the capacitance value of the smoothing capacitor is as described in the first embodiment, but in this embodiment, the signal-to-signal skew (whichever is greater between td1 and td2) compared to the time t0 in the first embodiment. Therefore, since the time can be shorter, the capacitance value can be realized with a smaller value.

  Since the prior art was a demodulation method in which the edge of the signal was detected because the data was a small amplitude signal, there was a possibility that a demodulation error could easily occur due to fluctuations in the internal power supply voltage due to the skew between the signals. In this embodiment, since the data signal is a signal having a full amplitude represented by a change in the delay time of the clock pulse, it can be demodulated by a logic circuit without requiring an edge detection type demodulation method. Data extraction can be performed without being affected by internal power supply noise due to timing skew between transmission signals.

  In addition, the demodulating circuit of the data storage device can be easily configured as compared with the prior art, so that the cost merit is great. Furthermore, the design of the control device can also reduce the design burden because, for example, a three-value voltage value as in the conventional example is not required, and therefore, an adjustment taking into account variations in equivalent resistance of the data storage device is not required.

(Embodiment 3)
FIG. 7 is a voltage waveform diagram showing a two-wire data communication method according to the third embodiment of the present invention, and FIG. 8 is a contact-type data using the two-wire data communication method according to the third embodiment of the present invention. It is a block diagram which shows the structural example of the data storage device in a storage system.

  The two-wire data communication method of the present embodiment is the reverse of the first transmission signal that is a stable clock pulse shown in FIG. 7A and the first transmission signal as shown in FIG. 7B. The phase clock pulse is composed of a second transmission signal in which the duty ratio of the clock pulse is changed by the logic of the transmission data.

  In the data storage device that has received such a transmission signal, first, an internal operation voltage is generated from the first and second transmission signals by full-wave rectification, and a stable internal operation clock is generated based on the first transmission signal. Extract. Next, by extracting the change in the duty ratio of the clock pulse of the second transmission signal using this internal operation clock, data demodulation can be easily performed as shown in FIG.

  The data storage device shown in FIG. 8 includes a rectifier circuit 608 for generating an internal power supply voltage from the first and second transmission signals, a data demodulation circuit 611 for extracting received data from the control device, and an internal power supply. And a second transmission circuit 610 used when transmitting data from the data storage device to the control device.

  The data demodulating circuit 611 extracts a stable clock pulse (FIG. 7A) based on the first transmission signal and uses it as an operation clock at the falling edge of the second transmission signal (FIG. 7B). ) Is directly latched in the D flip-flop to extract the demodulated data (FIG. 7E). Since the demodulation mechanism is basically the same as that of the above-described (Embodiment 2), detailed description is omitted.

  In this embodiment, the duty ratio of the clock pulse of the second transmission signal is set to 3: 7 when the transmission data logic is “1” and 5: 5 when the transmission data logic is “0”. In order to detect this difference, a signal obtained by delaying the second transmission signal by Δd at the falling edge of the first transmission signal is latched. The ratio of the duty ratio may be set so as to sufficiently satisfy the specifications of the setup time and hold time of the D flip-flop when the second transmission signal is latched using the first transmission signal as a clock.

  In order to simplify the explanation, the first and second transmission signals are directly input to the D flip-flop of the data demodulation circuit 611 in FIG. 8, but the first and second transmission signals are actually input. Therefore, an adjustment circuit for adjusting the voltage level and polarity and reproducing the signal is required. Further, as described in the second embodiment, a circuit for delaying the input signal to the D flip-flop by Δd is necessary.

  In addition, the data demodulating circuit which is a feature of the present embodiment detects the change in the duty ratio of the clock pulse of the second transmission signal as data using the first transmission signal as an internal operation clock, and therefore the first It is also possible to adopt a circuit configuration in which combination logic data such as an exclusive OR of the second transmission signal and the second transmission signal is used as an input signal to the D flip-flop of the data demodulation circuit 611.

  In addition, since the internal power supply voltage is generated by full-wave rectification, an interval in which power cannot be supplied by the difference between the duty ratios of the clock pulses of the first transmission signal and the second transmission signal (first and second transmission signals) Are not in opposite phase). Therefore, it is necessary to insert the smoothing capacitor 612 into the internal power supply and maintain the power in this section. Since the method for determining the capacitance value is basically the same as that described in the first embodiment, the description thereof is omitted.

  Since the prior art was a demodulation method in which the edge of the signal was detected because the data was a small amplitude signal, there was a possibility that a demodulation error could easily occur due to fluctuations in the internal power supply voltage due to the skew between the signals. In this embodiment, since the data signal is a signal having a full amplitude represented by a change in the duty ratio of the clock pulse, it is possible to perform a demodulation process in a logic circuit without requiring an edge detection type demodulation method. Data extraction can be performed without being affected by internal power supply noise due to timing skew between transmission signals.

  In addition, the demodulating circuit of the data storage device can be easily configured as compared with the prior art, so that the cost merit is great. Furthermore, since the control device is not a ternary voltage value as in the conventional example but a signal having a full amplitude, it can be easily configured with a logic circuit and has a low design burden.

(Embodiment 4)
FIG. 9 is a voltage waveform diagram showing the two-wire data communication method according to the fourth embodiment of the present invention, and FIG. 10 is a contact-type data using the two-wire data communication method according to the fourth embodiment of the present invention. It is a block diagram which shows the structural example of the data storage device in a storage system.

  The two-wire data communication method of the present embodiment is the reverse of the first transmission signal that is a stable clock pulse shown in FIG. 9A and the first transmission signal as shown in FIG. 9B. A second clock pulse representing a logic data of “H” or “L” corresponding to the superposition of the pulse signal having a small time width t0 on the signal polarity “H” or “L”. It consists of a transmission signal.

  In the data storage device that has received such a transmission signal, first, an internal operation voltage is generated from the first and second transmission signals by full-wave rectification, and a stable internal operation clock is generated based on the first transmission signal. Extract. Next, a pulse signal with a small time width t0 superimposed on the second transmission signal is extracted by the exclusive OR of the first and second transmission signals, and this is the polarity of the clock pulse of the first transmission signal. It is possible to easily perform data demodulation by detecting whether it is superimposed and processing this with the internal operation clock extracted based on the first transmission signal.

  The data storage device shown in FIG. 10 includes a rectifier circuit 808 for generating an internal power supply voltage from the first and second transmission signals, a data demodulation circuit 811 for extracting received data from the control device, and an internal power supply. And a second transmission circuit 810 used when transmitting data from the data storage device to the control device.

  The data demodulating circuit 811 extracts an exclusive OR signal of the first and second transmission signals (FIG. 9D), and uses the signal as a clock to send the first transmission signal to the first stage D flip-flop. Latch (FIG. 9 (e)). Further, the output of the first stage D flip-flop is latched by the next stage D flip-flop with a clock pulse extracted based on the first transmission signal to obtain a demodulated data signal (FIG. 9 (f)). )).

  In order to simplify the description, in FIG. 10, the first and second transmission signals are directly input to the D flip-flop and the logic gate of the data demodulation circuit 811. An adjustment circuit for adjusting the voltage level and polarity from the two transmission signals and reproducing the signal is required. In addition, since a minute pulse (whisker) is generated due to the skew between the signals in the exclusive OR of the first and second transmission signals, a filter circuit is actually required. However, here, the description is simplified. Is omitted.

  Note that since the internal power supply voltage is generated by full-wave rectification, power cannot be supplied during the small time interval t0 of the pulse signal superimposed on the second transmission signal. Therefore, it is necessary to insert the smoothing capacitor 812 into the internal power supply and maintain the power in this section. Since the method for determining the capacitance value is basically the same as that described in the first embodiment, the description thereof is omitted.

  Since the prior art was a demodulation method in which the edge of the signal was detected because the data was a small amplitude signal, there was a possibility that a demodulation error could easily occur due to fluctuations in the internal power supply voltage due to the skew between the signals. In this embodiment, since the data signal is a signal having the full amplitude represented by the time position of the superimposed pulse signal, it is possible to perform a demodulation process by a logic circuit without requiring an edge detection type demodulation method. Thus, data extraction can be performed without being affected by internal power supply noise due to timing skew between the transmission signals.

  In addition, the demodulating circuit of the data storage device can be easily configured as compared with the prior art, so that the cost merit is great. Furthermore, the design of the control device can also reduce the design burden because, for example, a three-value voltage value as in the conventional example is not required, and therefore, an adjustment taking into account variations in equivalent resistance of the data storage device is not required.

(Embodiment 5)
FIG. 11 is a voltage waveform diagram showing the two-wire data communication method according to the fifth embodiment of the present invention, and FIG. 12 is contact data using the two-wire data communication method according to the fifth embodiment of the present invention. It is a circuit diagram which shows the structural example of the data demodulation circuit in the data storage device of a storage system.

  The two-wire data communication method of the present embodiment includes a first transmission signal (FIG. 11 (a)) that is a clock pulse whose duty ratio changes according to the data logic to be transmitted (FIG. 11 (c)), and the first It consists of a second transmission signal (FIG. 11B) that is a clock pulse that is always in reverse phase to the transmission signal.

  In the data storage device that has received such a transmission signal, first, an internal operating voltage is generated from the first and second transmission signals by full-wave rectification. An internal operation clock is extracted based on the first or second transmission signal. In this case, the duty ratio of the first or second transmission signal is changed, but the clock period t is kept constant, so that it can be used as an internal operation clock unless it is set to an extreme duty ratio. Next, data is extracted by a data demodulating circuit having a time determination function for extracting the change in the duty ratio. The change rate of the duty ratio is determined in consideration of the variation range of the time determination function.

  Since the data storage device of the present embodiment has the same configuration as that of the data storage device of FIG. 2 described in Embodiment 1 except for the data demodulation circuit, description thereof is omitted. The data demodulating circuit in the data storage device of the present embodiment shown in FIG. 12 is a charge / discharge circuit 1001 for time determination, which is composed of a transistor switch, a resistance element, and a capacitance element that are turned on / off according to the signal polarity of the second transmission signal. And a comparator 1002 that compares the output of the charge / discharge circuit with the internal reference voltage, and a two-stage D flip-flop that latches the output with a clock pulse extracted based on the first transmission signal.

  First, when the signal polarity of the second transmission signal is “H”, the transistor switch is turned on, and the capacitive element of the charge / discharge circuit 1001 is charged from the internal VDD. At this time, since the capacitive element is charged to a voltage close to the internal VDD, the voltage becomes higher than the internal reference voltage, and the output of the comparator 1002 becomes “H”.

  Next, when the signal polarity of the second transmission signal is “L”, the transistor switch is turned off, and the charge charged in the capacitor element is discharged through the resistance element. When the voltage falls below the internal reference voltage, the output of the comparator 1002 becomes “L” (FIGS. 11D and 11E).

  Therefore, if the values of the resistive element and the capacitive element are determined so that the discharge time until the output of the charge / discharge circuit 1001 falls below the internal reference voltage is about half of the clock rate, the change in the duty ratio of the clock pulse can be reduced over time. Can be determined. Note that in this embodiment mode, the electric charge charged in the capacitor element is discharged through the resistor element; however, the transistor element can be discharged instead of the resistor element.

  After that, the output of the comparator 1002 is latched at the falling edge of the first transmission signal by the D flip-flop (FIG. 11 (f)), and the output is latched at the rising edge of the first transmission signal for time shaping. Demodulated data can be extracted (FIG. 11 (g)).

  In the present embodiment, since there is no time to intentionally make the first and second transmission signals have the same polarity, the smoothing capacity of the internal power supply of the data storage device can be configured with a slight capacity value. .

  In the conventional technique, since the data is a small amplitude signal, it is a demodulation method for detecting the edge of the signal change point. Therefore, there is a possibility that a demodulation error may easily occur due to fluctuation of the internal power supply voltage due to a skew between signals. In this embodiment, since the data signal is a signal having a full amplitude represented by the duty ratio of the clock pulse, it can be demodulated by a logic circuit without requiring an edge detection type demodulation method, and a two-wire transmission signal It is possible to perform data extraction without being affected by internal power supply noise due to timing skew between them.

  In addition, since the control device configuration does not require the three voltage values as in the conventional example, it is not necessary to make adjustments that take into account variations in the equivalent resistance of the data storage device.

  A first two-wire data communication method is a two-wire data communication method in which data communication, clock and power supply are performed between a control device and a data storage device through first and second signal lines, A positive-phase clock pulse is transmitted through the first signal line, and a negative-phase clock pulse modulated according to the logic of the transmission data is transmitted through the second signal line.

  According to the first two-wire data communication method, a positive-phase clock pulse is extracted on the basis of the first signal line, and the modulated anti-phase signal transmitted on the second signal line using the clock pulse is extracted. Since the signal extracted from the clock pulse can be determined, by performing appropriate modulation, the demodulation process can be performed by the logic circuit without using the edge detection type demodulation method. It is possible to avoid demodulation errors due to. Further, the demodulation can be simplified as compared with the prior art, and the cost merit is great. Furthermore, since the control device does not require a three-valued voltage value as in the prior art, the design burden can be reduced by eliminating the need for adjustment taking into account variations in the equivalent resistance of the data storage device.

  The second two-wire data communication method is the two-wire data communication method according to claim 1, wherein a reverse-phase clock pulse transmitted through the second signal line is pulsed according to the logic of the transmission data. Modulated with or without

  According to the second two-wire data communication method, the modulated signal is a full-amplitude signal that represents a logical value depending on the presence or absence of a clock pulse, and therefore is demodulated by a logic circuit without requiring an edge detection type demodulation method. It is possible to perform processing, and it is possible to perform data demodulation with almost no demodulation error due to the influence of inter-signal skew or the like.

  The third two-wire data communication method is the two-wire data communication method according to claim 1, wherein a reverse-phase clock pulse transmitted through the second signal line is generated according to the logic of the transmission data. It is generated by modulating the delay time with respect to the positive phase clock pulse.

  According to the third two-wire data communication method, since the modulated signal is a signal having a full amplitude that represents a logical value due to a change in the delay time of the clock pulse, the edge detection type demodulation method is not required and the logic The circuit can perform demodulation processing, and data can be extracted without being affected by internal power supply noise due to timing skew between two-line transmission signals.

  The fourth two-wire data communication method is the two-wire data communication method according to claim 1, wherein a reverse-phase clock pulse transmitted through the second signal line is duty cycled according to the logic of the transmission data. Modulated with ratio change.

  According to the fourth two-wire data communication method, since the modulated signal is a signal having a full amplitude that represents a logical value by a change in the duty ratio of the clock pulse, the edge detection type demodulation method is not required and the logic The circuit can perform demodulation processing, and data can be extracted without being affected by internal power supply noise due to timing skew between two-line transmission signals.

  The fifth two-wire data communication method is the two-wire data communication method according to claim 1, wherein the opposite-phase clock pulse transmitted through the second signal line is opposite in accordance with the logic of the transmission data. It is generated by modulating at the position of the pulse signal superimposed with polarity.

  According to the fifth two-wire data communication method, since the modulated signal is a signal having a full amplitude representing a logical value at the position of the pulse superimposed on the clock pulse of the opposite phase, the edge detection type demodulation is performed. It is possible to perform demodulation processing by a logic circuit without requiring a method, and it is possible to perform data extraction without being affected by internal power supply noise due to timing skew between two-line transmission signals.

  6. The two-wire data communication method according to claim 1, wherein the positive-phase clock pulse transmitted on the first signal line and the reverse phase transmitted on the second signal line are the two-wire data communication method according to claim 1. The clock pulse is generated by modulating with a change in the duty ratio according to the logic of the transmission data.

  According to the sixth two-wire data communication method, since the modulated signal is a signal having a full amplitude that represents a logical value with the duty ratio of the clock pulse, the edge detection type demodulation method is not required and the logic circuit is used. Demodulation is possible, and data extraction can be performed without being affected by internal power supply noise due to timing skew between two-line transmission signals.

  A first two-wire data communication system is a two-wire data communication system that performs data communication, a clock, and power supply by using first and second signal lines between a control device and a data storage device. The control device includes: means for generating positive-phase and negative-phase clock pulses; means for transmitting the positive-phase clock pulse to the first signal line; and the negative-phase clock pulses according to the logic of transmission data. And a means for modulating the signal with the presence or absence of a pulse and transmitting the modulated signal to the second signal line, wherein the data storage device rectifies the voltages of the first and second signal lines and supplies power to the data storage device. Means for supplying a voltage; means for extracting an internal clock based on the first signal line; and a reverse-phase clock pulse transmitted on the second signal line using the internal clock. And a data demodulation means for detecting free.

  According to the first two-wire data communication system, the modulated signal is a full-amplitude signal that represents a logical value depending on the presence or absence of a clock pulse, and therefore is demodulated by a logic circuit without requiring an edge detection type demodulation method. It is possible to perform processing, and it is possible to perform data demodulation with almost no demodulation error due to the influence of inter-signal skew or the like. In addition, the demodulating circuit of the data storage device can be easily configured as compared with the prior art, so that the cost merit is great. Furthermore, since the control device does not require a three-valued voltage value as in the prior art, the design burden can be reduced by eliminating the need for adjustment taking into account variations in the equivalent resistance of the data storage device.

  The second two-wire data communication system is a two-wire data communication system that performs data communication, clock and power supply between the control device and the data storage device via the first and second signal lines. The control device includes: means for generating positive-phase and negative-phase clock pulses; means for transmitting the positive-phase clock pulse to the first signal line; And a means for modulating the data with a change in a delay time with respect to the positive-phase clock pulse and transmitting the modulated signal to the second signal line, wherein the data storage device includes voltages on the first and second signal lines. Means for supplying a power supply voltage to the data storage device, means for extracting an internal clock based on the first signal line, and the second using the internal clock And a data demodulation means for detecting a change of the clock pulse delay time of the reverse phase to be transmitted by the Route.

  According to the second two-wire data communication system, since the modulated signal is a signal having a full amplitude that represents a logical value due to a change in the delay time of the clock pulse, the edge detection type demodulation method is not required and the logic The circuit can perform demodulation processing, and data can be extracted without being affected by internal power supply noise due to timing skew between two-line transmission signals. In addition, the demodulating circuit of the data storage device can be easily configured as compared with the prior art, so that the cost merit is great. Furthermore, since the control device does not require a three-valued voltage value as in the prior art, the design burden can be reduced by eliminating the need for adjustment taking into account variations in the equivalent resistance of the data storage device.

  A third two-wire data communication system is a two-wire data communication system that performs data communication, a clock, and power supply through a first signal line and a second signal line between a control device and a data storage device, The control device includes: means for generating positive-phase and negative-phase clock pulses; means for transmitting the positive-phase clock pulse to the first signal line; The data storage device rectifies the voltages of the first and second signal lines and modulates the data with the duty ratio change, and transmits the data to the second signal line. Means for supplying a power supply voltage to the device; means for extracting an internal clock based on the first signal line; and a clock parameter transmitted on the second signal line using the internal clock. And a data demodulation means for detecting a change in the duty ratio of the scan.

  According to the third two-wire data communication system, since the modulated signal is a signal having a full amplitude that represents a logical value by a change in the duty ratio of the clock pulse, the edge detection type demodulation method is not required and the logic The circuit can perform demodulation processing, and data can be extracted without being affected by internal power supply noise due to timing skew between two-line transmission signals. In addition, the demodulating circuit of the data storage device can be easily configured as compared with the prior art, so that the cost merit is great. Furthermore, since the control device does not require a three-valued voltage value as in the prior art, the design burden can be reduced by eliminating the need for adjustment taking into account variations in the equivalent resistance of the data storage device.

  A fourth two-wire data communication system is a two-wire data communication system that performs data communication, a clock, and power supply through a first signal line and a second signal line between a control device and a data storage device, The control device includes: means for generating positive-phase and negative-phase clock pulses; means for transmitting the positive-phase clock pulse to the first signal line; And means for modulating at the pulse position with the opposite polarity and transmitting to the second signal line, and the data storage device rectifies the voltages of the first and second signal lines. Means for supplying a power supply voltage to the data storage device, means for extracting an internal clock based on the first signal line, and transmission to the second signal line using the internal clock And a data demodulation means for detecting the pulse position which overlaps with the polar.

  According to the fourth two-wire data communication system, since the modulated signal is a full-amplitude signal representing a logical value at the time position of a narrow-width pulse superimposed on a reverse-phase clock pulse, It is possible to perform demodulation processing by a logic circuit without requiring an edge detection type demodulation method, and it is possible to extract data without being affected by internal power supply noise due to timing skew between two-line transmission signals. In addition, the demodulating circuit of the data storage device can be easily configured as compared with the prior art, so that the cost merit is great. Furthermore, since the control device does not require a three-valued voltage value as in the prior art, the design burden can be reduced by eliminating the need for adjustment taking into account variations in the equivalent resistance of the data storage device.

  A fifth two-wire data communication system is a two-wire data communication system that performs data communication, a clock, and power supply by using first and second signal lines between a control device and a data storage device, The control device modulates the first and second phase clock pulses with a change in duty ratio in accordance with a logic of transmission data with respect to the positive phase and negative phase clock pulses according to a logic of transmission data. Means for respectively transmitting to a second signal line, wherein the data storage device rectifies the voltages of the first and second signal lines and supplies a power supply voltage to the data storage device; A means for extracting an in-device clock based on one signal line; and a change in duty ratio of a reverse-phase clock pulse transmitted on the second signal line using the in-device clock. And a data demodulation means for knowledge.

  According to the fifth two-wire data communication system, since the modulated signal is a signal having a full amplitude that represents a logical value with the duty ratio of the clock pulse, the edge detection type demodulation method is not required and the logic circuit is used. Demodulation is possible, and data extraction can be performed without being affected by internal power supply noise due to timing skew between two-line transmission signals. In addition, the demodulating circuit of the data storage device can be easily configured as compared with the prior art, so that the cost merit is great. Furthermore, since the control device does not require a three-valued voltage value as in the prior art, the design burden can be reduced by eliminating the need for adjustment taking into account variations in the equivalent resistance of the data storage device.

  The first control device is a control device for performing data communication, clock and power supply with the data storage device by the first and second signal lines, and means for generating clock pulses of normal phase and reverse phase And means for transmitting the positive-phase clock pulse to the first signal line, and modulating the negative-phase clock pulse with the presence or absence of a pulse according to the logic of the transmission data to the second signal line. Means for transmitting.

  According to the first control device, since the modulated signal is a full-amplitude signal that represents a logical value by the presence or absence of a clock pulse, the logic circuit performs demodulation processing without requiring an edge detection type demodulation method. Therefore, it is possible to perform data demodulation with almost no demodulation error due to the influence of signal-to-signal skew or the like. Further, since the three-value voltage value as in the prior art is not required, the design burden can be reduced, for example, the adjustment considering the variation in equivalent resistance of the data storage device is not required.

  The second control device is a control device for performing data communication, clock and power supply with the data storage device via the first and second signal lines, and means for generating normal-phase and reverse-phase clock pulses. And a means for transmitting the positive phase clock pulse to the first signal line, and a change in a delay time with respect to the positive phase clock pulse in accordance with a logic of transmission data with respect to the negative phase clock pulse. Means for modulating and transmitting to the second signal line.

  According to the second control device, since the modulated signal is a signal having a full amplitude that represents a logical value due to a change in the delay time of the clock pulse, the logic circuit performs a demodulation process without requiring an edge detection type demodulation method. It is possible to perform data extraction without being affected by internal power supply noise due to timing skew between transmission signals of two lines. Further, since the three-value voltage value as in the prior art is not required, the design burden can be reduced, for example, the adjustment considering the variation in equivalent resistance of the data storage device is not required.

  The third control device is a control device for performing data communication, clock and power supply with the data storage device via the first and second signal lines, and means for generating clock pulses of normal phase and reverse phase And means for transmitting the positive-phase clock pulse to the first signal line, and modulating the second-phase clock pulse with a change in duty ratio according to the logic of transmission data according to the logic of transmission data. Means for transmitting to the signal line.

  According to the third control device, since the modulated signal is a signal having a full amplitude that represents a logical value by a change in the duty ratio of the clock pulse, the logic circuit performs a demodulation process without requiring an edge detection type demodulation method. It is possible to perform data extraction without being affected by internal power supply noise due to timing skew between transmission signals of two lines. Further, since the three-value voltage value as in the prior art is not required, the design burden can be reduced, for example, the adjustment considering the variation in equivalent resistance of the data storage device is not required.

  The fourth control device is a control device for performing data communication, clock and power supply with the data storage device by the first and second signal lines, and means for generating clock pulses of normal phase and reverse phase And means for transmitting the positive-phase clock pulse to the first signal line, and modulating the opposite-phase clock pulse at a pulse position that is superimposed with an opposite polarity according to the logic of transmission data. Means for transmitting to the second signal line.

  According to the fourth control device, since the modulated signal is a signal having a full amplitude that represents a logical value at a time position of a narrow-width pulse superimposed on a reverse-phase clock pulse, the edge detection type Demodulation can be performed by a logic circuit without requiring a demodulation method, and data extraction can be performed without being affected by internal power supply noise due to timing skew between two-line transmission signals. Further, since the three-value voltage value as in the prior art is not required, the design burden can be reduced, for example, the adjustment considering the variation in equivalent resistance of the data storage device is not required.

  The fifth control device is a control device for performing data communication, clock and power supply with the data storage device via the first and second signal lines, and means for generating normal-phase and reverse-phase clock pulses. And a means for modulating the forward-phase clock pulse and the reverse-phase clock pulse with a change in duty ratio according to the logic of transmission data, and transmitting the modulated pulses to the first and second signal lines, respectively.

  According to the fifth control device, since the modulated signal is a signal having a full amplitude that represents a logical value with the duty ratio of the clock pulse, the logic circuit can perform demodulation processing without requiring an edge detection type demodulation method. Thus, data extraction can be performed without being affected by internal power supply noise due to timing skew between transmission signals of two lines. Further, since the three-value voltage value as in the prior art is not required, the design burden can be reduced, for example, the adjustment considering the variation in equivalent resistance of the data storage device is not required.

  The first data storage device is a data storage device that performs data communication, clock and power supply with the control device through the first and second signal lines, and the voltage of the first and second signal lines. Means for supplying a power supply voltage to the data storage device, means for extracting an in-device clock based on the first signal line, and transmission on the second signal line using the in-device clock Data demodulating means for detecting the presence / absence of a reverse-phase clock pulse.

  According to the first data storage device, since the modulated signal is a full-amplitude signal that represents a logical value by the presence or absence of a clock pulse, the logic circuit performs demodulation processing without requiring an edge detection type demodulation method. Therefore, it is possible to perform data demodulation with almost no demodulation error due to the effect of skew between signals. Further, the demodulating circuit can be easily configured as compared with the prior art, so that the cost merit is great.

  The second data storage device is a data storage device that performs data communication, clock and power supply with the control device through the first and second signal lines, and the voltage of the first and second signal lines. Means for supplying a power supply voltage to the data storage device, means for extracting an in-device clock based on the first signal line, and transmission on the second signal line using the in-device clock And a data demodulating means for detecting a change in the delay time of the reverse-phase clock pulse.

  According to the second data storage device, since the modulated signal is a signal having a full amplitude that represents a logical value by a change in the delay time of the clock pulse, it is demodulated by a logic circuit without requiring an edge detection type demodulation method. Processing is possible, and data can be extracted without being affected by internal power supply noise due to timing skew between transmission signals of two lines. Further, the demodulating circuit can be easily configured as compared with the prior art, so that the cost merit is great.

  The third data storage device is a data storage device that performs data communication, clock and power supply with the control device through the first and second signal lines, and the voltage of the first and second signal lines. Means for supplying a power supply voltage to the data storage device, means for extracting an in-device clock based on the first signal line, and transmission on the second signal line using the in-device clock Data demodulating means for detecting a change in the duty ratio of the clock pulse.

  According to the third data storage device, since the modulated signal is a signal having a full amplitude that represents a logical value by a change in the duty ratio of the clock pulse, it is demodulated by a logic circuit without requiring an edge detection type demodulation method. Processing is possible, and data can be extracted without being affected by internal power supply noise due to timing skew between transmission signals of two lines. Further, the demodulating circuit can be easily configured as compared with the prior art, so that the cost merit is great.

  The fourth data storage device is a data storage device that performs data communication, clock and power supply with the control device through the first and second signal lines, and the voltage of the first and second signal lines. Means for supplying power supply voltage to the data storage device, means for extracting an internal clock based on the first signal line, and transmission to the second signal line using the internal clock And a data demodulating means for detecting a pulse position to be superimposed with the opposite polarity.

  According to the fourth data storage device, since the modulated signal is a signal having a full amplitude that represents a logical value at the time position of a narrow-width pulse superimposed on a reverse-phase clock pulse, the edge detection type Thus, it is possible to perform demodulation processing by a logic circuit without requiring the above demodulation method, and it is possible to extract data without being affected by internal power supply noise due to timing skew between two-line transmission signals. Further, the demodulating circuit can be easily configured as compared with the prior art, so that the cost merit is great.

  The fifth data storage device is a data storage device that performs data communication, clock and power supply with the control device through the first and second signal lines, and the voltage of the first and second signal lines. Means for supplying a power supply voltage to the data storage device, means for extracting an in-device clock based on the first signal line, and transmission on the second signal line using the in-device clock Data demodulating means for detecting a change in the duty ratio of the reverse-phase clock pulse.

  According to the fifth data storage device, since the modulated signal is a signal having a full amplitude that represents a logical value by the duty ratio of the clock pulse, the logic circuit can perform the demodulation process without requiring an edge detection type demodulation method. It is possible to perform data extraction without being affected by internal power supply noise due to timing skew between transmission signals of two lines. Further, the demodulating circuit can be easily configured as compared with the prior art, so that the cost merit is great.

Voltage waveform diagram showing a two-wire data communication method according to the first embodiment of the present invention The block diagram which shows the structural example of the data storage device in the contact-type data storage system using the two-wire data communication method which concerns on Embodiment 1 of this invention Voltage waveform diagram showing a two-wire data communication method according to Embodiment 2 of the present invention Block diagram showing a full-wave rectifier circuit for generating an internal operating voltage from the first and second transmission signals Voltage waveform diagram showing the generated internal operating voltage The block diagram which shows the structural example of the control apparatus in the contact-type data storage system using the two-wire data communication method which concerns on Embodiment 2 of this invention. Voltage waveform diagram showing a two-wire data communication method according to Embodiment 3 of the present invention The block diagram which shows the structural example of the data storage apparatus in the contact-type data storage system using the two-wire data communication method which concerns on Embodiment 3 of this invention. Voltage waveform diagram showing a two-wire data communication method according to Embodiment 4 of the present invention The block diagram which shows the structural example of the data storage device in the contact-type data storage system using the two-wire data communication method which concerns on Embodiment 4 of this invention Voltage waveform diagram showing a two-wire data communication method according to Embodiment 5 of the present invention The circuit diagram which shows the structural example of the data demodulation circuit in the data storage device of the contact-type data storage system using the two-wire data communication method which concerns on Embodiment 5 of this invention Voltage waveform diagram for explaining a conventional two-wire data communication method Block diagram showing a configuration example of a contact data storage system using a conventional two-wire data communication method A circuit diagram showing a data demodulating circuit in a data storage device of a contact data storage system using a conventional two-wire data communication method

Explanation of symbols

208, 608, 808, 1208 Rectifier circuit 210, 610, 810, 1210 Second transmission circuit 211, 611, 811, 1209 Data demodulation circuit 212, 612, 812, 1212 Smoothing capacitor 401 Transistor switch 402 Delay capacitor 1001 Charging / discharging Circuit 1002 Comparator 1201 Control device 1202 Data storage device 1203 Voltage level generation circuit 1204 First transmission circuit 1205 Clock generation circuit 1206 First signal detection circuit 1211 Clock detection circuit 1301 Low-pass filter 1302 High-pass filter 1303 Comparator 1304 D flip flop

Claims (6)

A data storage device that extracts data from a received clock,
A first input terminal to which a first signal that is a clock pulse is input;
A second input terminal to which a second signal in which data is superimposed on a clock pulse having a phase opposite to that of the clock pulse is input;
A rectifier circuit connected to the first input terminal and the second input terminal for generating an internal power supply voltage from the first signal and the second signal;
A data storage device comprising: a data demodulating circuit connected to the first input terminal and the second input terminal and extracting the data from the first signal and the second signal.   The data storage device according to claim 1, wherein the second signal is a full-amplitude signal representing the data by the presence or absence of a clock pulse.   The data storage device according to claim 1, wherein the second signal is a full amplitude signal representing the data by a plurality of delay times.   The data storage device according to claim 1, wherein the second signal is a full-amplitude signal representing the data with a plurality of duty ratios.   2. The data storage device according to claim 1, wherein the second clock is a full-amplitude signal representing the time position of a pulse signal on which the data is superimposed.   The data storage device according to claim 1, further comprising a smoothing capacitor connected to the rectifier circuit.

Images