JP2006165708A - Data communication circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a 2-wire data communication apparatus for enabling 2-way data communication the operating voltage of which is stabilized and that is not susceptible to the effect of noise. <P>SOLUTION: In the 2-wire transmission, DC power is transmitted at an average level of a clock signal and signal superimposition information is transmitted in terms of clock inverting information. At a receiver side, a full wave rectifier circuit extracts the DC power. In the information reception, the clock transmitted for a prescribed period is delayed and the transmitted data are reproduced by capturing the data using the clock. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a contact-type data communication circuit connected by two lines for performing data communication.

  In conventional contact-type data communication, in order to perform communication, it is necessary to provide a power source, a ground, a bidirectional transmission / reception signal, and a total of four contacts. For this reason, there is a limit to downsizing due to the physical size of the four contacts.

  In order to further reduce the number of contacts of the contact-type data communication circuit, as described in Patent Document 1, in a system in which the control device 300 and the data carrier device 301 perform data communication, the power and Proposals have been made to enable two-way data communication.

  This two-wire data communication apparatus will be described with reference to FIG.

  A control device 300 includes a clock generation circuit 304 that generates a clock pulse and a reverse-phase pulse of the clock pulse, a voltage level generation circuit 302 that generates an amplitude level of the clock pulse, and a detection circuit 305 that detects an amplitude difference. Has been.

  The voltage level generation circuit 302 is constituted by a series connection of a resistor R1 and a resistor R2 connected to a power supply voltage, and outputs a voltage between the resistors. The transmission circuit 303 connects the FET to the resistor R2 of the voltage level generation circuit, and determines the output voltage Vo of the voltage level generation circuit 302 based on the signal level input to the gate. The clock generation circuit 304 connects the power supply terminal of the inverter to the output of the voltage level generation circuit 302, and transmits signals by changing the amplitude of the in-phase and anti-phase clock pulses. The signal detection circuit 305 is connected to one of the two contacts of the data carrier device 301 and detects a change in the load of the data carrier device 301 as viewed from the control device 300 as a signal.

  The operation of the conventional two-wire data communication will be described below. First, data transmission from the control device 300 to the data carrier device 301 will be described. A DATA pulse is input to the clock generation circuit, and a differential signal having a pulse in phase with the input pulse and a pulse in reverse phase are output to the output A and output B of the clock generation circuit 304, respectively. Further, the amplitude of the output pulse at that time is changed according to the transmission signal DATA, so that data is transmitted to the data carrier device 301 by changing the amplitude of the clock pulse.

  Next, data transmission from the data carrier device 301 to the control device 300 will be described. The input impedance of the data carrier device 301 changes depending on the voltage level of the transmission signal DATA2 of the data carrier device 301, and the amplitude of the output pulse is modulated. Similarly to the above, the control device 300 receives data by the amplitude change.

As described above, in the conventional two-wire data communication device, the data voltage is superimposed on the operating voltage supplied to the data carrier device 301 in communication between both devices, so that only two contact points are used. The power supply to the data carrier device 301 and the data communication are realized.
JP 2003-069653 A JP 2003-169002 A Japanese Patent Laid-Open No. 2003-110470

  However, in the conventional two-wire data communication apparatus, data is received by detecting the difference in signal amplitude, but the voltage level for detecting the signal amplitude differs depending on the transmission / reception communication direction. That is, even when the voltage level condition that allows data communication in one direction when the variation of various components such as equivalent resistance is large, a sufficient amplitude difference cannot be secured in the reverse direction, and data communication cannot be performed. There was a problem.

  In order to solve this problem, a proposal has been made to secure a voltage level necessary for bidirectional communication by adding a circuit for switching an operating voltage at the time of transmission and reception, as described in Patent Document 3.

  However, by adding a new transmission / reception switching signal, the control becomes complicated, the data is erroneously detected when noise is applied to the differential clock, and the amplitude is modulated, so that the signal is supplied. There is a problem that the operating voltage fluctuates, and further improvement is desired. In addition, the device for performing data communication by changing the pulse width described in Patent Document 1 arranges a plurality of resistors in series, switches between conduction and non-conduction, and changes the voltage level. Therefore, there is a demerit that makes it difficult to select parts of the receiving circuit section. In addition, there is a method of lowering the output impedance by reducing the resistance, but conversely has a demerit that loss is increased. As a further problem, since the clock generation means is provided after the rectifier circuit, there is a problem that the clock pulses.

  In order to solve the above-described conventional problems, the object of the first invention according to the present application is to combine a clock inverted to a clock supplied to the first contact or a predetermined level signal. An object of the present invention is to provide a two-wire data communication apparatus that is configured to transmit data to two contact points and realizes bidirectional data communication that is less susceptible to noise and stable operation voltage.

  In addition, an object of the second invention according to the present application is to realize a stable power supply to one transmission / reception unit.

  A first invention according to the present invention includes a first transmission / reception device and a second transmission / reception device, and performs two-wire data communication for performing data communication between the transmission / reception devices via first and second contacts. The first transmitting / receiving device supplies a clock having a predetermined cycle to the first contact and receives a clock inverted from the clock supplied to the first contact or a predetermined level signal. A clock generation means for supplying to the other contact; a first control means for controlling the first transmission / reception device; and a current detection means for detecting a current flowing through the first or second contact, The second transmitting / receiving device includes a storage unit for storing the transmitted predetermined information, a power generation unit for generating an operating voltage from the signals received at the first and second contacts, and a clock transmitted at a predetermined cycle. Delay to delay A stage, a data receiving means for capturing data in synchronization with the output clock of the delay means, and a second control means for changing the impedance between the first and second contacts in accordance with the transmission signal, Data is transmitted to the second contact by combining a clock inverted with respect to the clock supplied to the contact or a predetermined level signal.

  According to a second aspect of the present invention, in the data communication circuit according to the first aspect, the power generation means is a circuit that performs full-wave rectification between the first and second contacts. To do.

  According to the first invention of the present application, since data is transmitted to the second contact by combining a clock inverted with respect to the clock supplied to the first contact or a predetermined level signal, amplitude modulation is performed. In comparison, a wide operating voltage can be secured. In addition, a voltage drop can be suppressed as much as possible by supplying a high on-duty clock to two contacts and performing full-wave rectification of the voltage between the two points. Therefore, even if a power supply drop occurs due to a skew or overshoot of a signal transmitted between two points, a stable power supply that does not fall below the operating voltage is possible.

  Further, regarding data reception, since data is received by detecting current instead of amplitude difference, data communication that is less susceptible to overshoot or undershoot due to noise or the like is also possible.

  Further, according to the second invention of the present application, full-wave rectification is performed between the first and second contacts to generate an operating voltage, so that stable power supply can be realized. .

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to examples.

  FIG. 1 shows a typical two-wire data communication circuit according to the first embodiment of the present invention. In this data communication circuit, two first transmission / reception units 100 and two second transmission / reception units 200 are provided. Data communication can be performed via the contacts A and B. First, the configuration of the data communication system according to the first embodiment will be described with reference to FIG.

  The first transmission / reception unit 100 includes a control unit 101 that controls the transmission / reception unit 100, a clock generation unit 102 that clocks transmission data from the control unit 101 to transmit to the transmission / reception unit 200, and resistors 103 to 106. A comparator 107 for comparing the current flowing through the resistor 104 is configured.

  On the other hand, the second transmission / reception unit 200 includes a control unit 201 that controls the transmission / reception unit 200, a full-wave rectification circuit 202 for rectifying the voltage between the contacts A and B and supplying power to the control unit 201, A smoothing capacitor 203 for smoothing and storing the signal rectified by the full-wave rectifier circuit 202, a resistor 204, a switch 205 for terminating the resistor 204 to two signal lines, a buffer 206, and a delay circuit 207 The D flip-flop 208 is configured.

  Next, the operation of this embodiment will be described. First, data transfer from the first transmission / reception unit 100 to the second transmission / reception unit 200 is performed as follows.

  In the first transmission / reception unit 100, the control unit 101 transmits data to be transmitted to the transmission / reception unit 200 to the clock generation unit 102. The clock generation unit 102 that has received the data analyzes the logic of the received data and generates a clock according to the analyzed contents. At this time, the clock generation unit 102 transmits a clock with a large on-duty constant cycle to the line on the contact A side, and transmits a high level to the line on the contact B side when the clock transmitted to the contact A side is transmitted. The inverted clock is transmitted in synchronization with the clock transmitted to the contact A side, and when transmitting the low level, the low level is transmitted as it is.

  In the second transmission / reception unit 200 that receives these signals, first, full-wave rectification is performed on the voltage between the contact A and the contact B through the full-wave rectification circuit 202, and then the voltage rectified by the smoothing capacitor 203 is smoothed. The operating voltage of the control unit 201 is assumed. The reason for transmitting a clock with a large on-duty to the second transmission / reception unit 200 is to take as much voltage as possible when full-wave rectification is performed so that the voltage to the control unit 201 can be stably supplied. Data communication speed can be increased by reducing the duty of data transmitted from the first transmission / reception unit 100 to the second transmission / reception unit 200 as the power consumption of the control unit 201 decreases.

  The data transmitted from the first transmission / reception unit 100 to the contacts A and B is waveform-formed by the buffer 206, and only the signal passing through the contact A is transmitted to the D flip-flop 208 via the delay circuit 207. FIG. 2 is a diagram specifically showing the flow of signals from the contacts A and B to the D flip-flop 208. Hereinafter, a method for receiving transmission data will be described with reference to FIG.

  A and B represent data transmitted to the contacts A and B, respectively, and a clock with a constant cycle with a large on-duty is transmitted to A. When B is high in signal logic, it is transmitted to A. When the signal logic is low level, a low level is transmitted. Since the clock transmitted to the contact A is delayed by the delay circuit 207, the output (207 output) is input to the clock terminal of the D flip-flop 208 slightly later than the clock transmitted to the contact A. Therefore, when the clock terminal of the D flip-flop 208 falls, the signal level of the contact B input to the D terminal can be determined. Therefore, the data transmitted from the first transmission / reception unit 100 can be reproduced.

  Next, an operation when the first transmission / reception unit 100 receives transmission data from the second transmission / reception unit 200 will be described.

  Data from the control unit 201 can be switched on / off of the resistor 204 formed between the contacts A and B by turning on / off the switch 205.

  When the data from the control unit 201 is at a high level, the switch 205 is turned on and the resistor 204 is turned on. Therefore, since the input impedance of the second transmission / reception unit 200 is reduced, the current flowing through the resistors 103 and 104 is increased. On the other hand, when the data from the control unit 201 is at a low level, the switch 205 is turned off and the resistor 204 is disabled. Therefore, since the input impedance of the second transmission / reception unit 200 increases, the current flowing through the resistors 103 and 104 decreases.

  As described above, the value of the current flowing through the resistors 104 and 105 changes according to the ON / OFF state of the switch 205.

  By detecting this, the logical level of the transmission data can be determined, and communication from the second transmission / reception unit 200 to the first transmission / reception unit 100 becomes possible.

  In the first embodiment, as shown in FIG. 1, the voltage across the resistor R104 is input to the comparator 107 to detect the current. Next, the operation in this configuration will be specifically described with reference to FIG.

  FIG. 3 is an operation timing chart when the first transmission / reception unit 100 receives data from the second transmission / reception unit 200. When the switch 205 is on, as described above, since the input impedance is low, the current flowing through the resistor 104 is increased, and the voltage difference input to the comparator 107 is increased due to the voltage drop, thereby detecting the signal level. It becomes possible. For example, when the switch 205 is in an on state and a high level is output to the contact A and a low level is output to the contact B, the voltage of the inverting input terminal of the comparator 107 is lower than that of the non-inverting input terminal. Output high level. When the low level is output to the contact A and the high level is output to the contact B, the voltage of the inverting input terminal of the comparator 107 is higher than that of the non-inverting input terminal, so the comparator 107 outputs a low level. That is, when the switch 205 is on, the output of the comparator 107 follows the timing of the contact A. Since the output from the comparator 107 continues to be output as long as the switch 205 is on, the control unit 101 monitors whether the clock is continuously output from the comparator 107, so that the second transmission / reception unit It can be determined that the transmission signal from 200 is at a high level.

  On the other hand, when the switch 205 is off, the input impedance increases and the current flowing through the resistor 104 decreases, so that almost no voltage drop occurs. Therefore, the voltage input to the comparator 107 is determined by the combination of the resistors 105 and 106. In the case of FIG. 1, since the inverting input terminal is pulled up and the non-inverting input terminal is pulled down, the output from the comparator 107 is always output. Become low level.

  As described above, transmission data from the second transmission / reception unit 200 can be confirmed by detecting the current flowing through the resistor by the comparator 107.

  In the conventional method, since data transmission is performed by amplitude modulation, it is necessary to make the operating voltage sufficient to detect the voltage difference always swing and voltage drop due to skew, undershoot, etc. Power supply was difficult. However, according to the present embodiment, since the operating voltage range can be widened, a two-wire data communication circuit capable of supplying stable power can be realized. In addition, since data transfer is possible even when the operating voltage is set to be small, the operating voltage can be set as small as possible and power consumption can be suppressed.

  In the first embodiment, when data transmitted from the first transmission / reception unit is at a high level, a clock that is inverted with respect to a clock of a predetermined cycle is transmitted, and when data transmitted from the first transmission / reception unit is at a low level Low level was output and data communication was performed.

  Conversely, when the data transmitted from the first transmission / reception unit is at a high level, a low level is output. When the data transmitted from the first transmission / reception unit is at a low level, the data is inverted with respect to a clock having a predetermined cycle. It goes without saying that data communication can be performed by transmitting the clock.

  Needless to say, if the clock is output from the clock generator in anticipation of the delay time in the delay circuit, the delay circuit can be omitted.

Representative two-wire data communication circuit according to the first embodiment Timing chart during data transmission operation of first transmission / reception unit Timing chart of the second transceiver unit when receiving data Conventional representative 2-wire data communication circuit

Explanation of symbols

100 first transmission / reception unit 101 control unit 102 clock generation unit 103 resistor 104 resistor 105 resistor 106 resistor 107 comparator 200 second transmission / reception unit 201 control unit 202 full-wave rectifier circuit 203 smoothing capacitor 204 resistor 205 switch 206 buffer 207 delay circuit 208 D flip-flop 300 Control device 301 Data carrier device 302 Voltage level generation circuit 303 Data transmission circuit 304 Clock generation circuit 305 Signal detection circuit 306 LSI equivalent resistance

Claims (2)

  Two-wire data communication having a first transmission / reception device and a second transmission / reception device and performing data communication between the transmission / reception devices via first and second contacts, wherein the first transmission / reception device Is a clock generating means for supplying a clock having a predetermined period to the first contact and for inverting the clock supplied to the first contact or for supplying a predetermined level signal to the other contact And a first control means for controlling the first transmission / reception apparatus, and a current detection means for detecting a current flowing through the first or second contact, while the second transmission / reception apparatus is transmitted. Storage means for storing predetermined information; power supply generation means for generating an operating voltage from signals received at the first and second contacts; delay means for delaying a clock transmitted at a predetermined period; Means output black Data receiving means for capturing data in synchronization with the second clock, and second control means for changing the impedance between the first and second contacts according to the transmission signal, and for the clock supplied to the first contact A data communication circuit characterized by transmitting data to the second contact by combining a clock inverted or a predetermined level signal.   2. The data communication circuit according to claim 1, wherein the power generation means is a circuit that performs full-wave rectification between the first and second contacts.

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