JP2006173707A - Data communication circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a 2-wire data communication apparatus for realizing two-way data communication by detecting signal reception on the basis of a difference in a frequency or a duty. <P>SOLUTION: In the 2-wire data communication employing first and second transmitter-receivers, the first transmitter-receiver sets a duty of a clock in response to a first transmission signal, transmits a pulse generated thereon and a pulse in the inverted relation to the pulse to the second transmitter-receiver, and includes a current detection means for detecting a current as a received signal from the second transmitter-receiver. On the other hand, the second transmitter-receiver includes: a comparison means for integrating the transmitted signal and comparing the integrated signal with a reference voltage; a data reception means for the first transmitter-receiver for capturing data synchronously with the transmission clock; and a second control means for changing the impedance between the two wires toward the first transmitter-receiver in response to a second transmission signal. The data communication circuit is characterized in that the circuit transmits the data by changing the duty of the clock. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a contact-type data communication circuit connected by two lines for performing data communication.

  Conventional data communication is not suitable for miniaturization because it is necessary to provide four contacts of a power source, a ground, and a transmission / reception signal in order to perform communication. In order to solve this problem, in a system in which the control device 300 and the data carrier device 301 perform data communication, proposals have been made to enable power and bidirectional data communication with two contact points (Patent Literature). 1).

  This two-wire data communication apparatus will be described with reference to FIG. The control device 300 includes a clock generation circuit 304 that generates a clock pulse and a reverse-phase pulse of the clock pulse, a voltage level generation circuit 302 that generates an amplitude level of the clock pulse, and a detection circuit 305 that detects an amplitude difference. .

  The voltage level generation circuit is constituted by a series connection of a resistor R1 and a resistor R2 connected to a power supply voltage, and outputs a voltage between the resistors. The transmission circuit 303 connects the FET to the resistor R2 of the voltage level generation circuit, and determines the output voltage Vo of the voltage level generation circuit 302 based on the signal level input to the gate. The clock generation circuit 304 connects the power supply terminal of the inverter to the output of the voltage level generation circuit 302, and transmits signals by changing the amplitude of the in-phase and anti-phase clock pulses. The signal detection circuit 305 is connected to one of the two contacts of the data carrier device 301 and detects a change in the load of the data carrier device 301 as viewed from the control device 300 as a signal.

  The operation of the conventional two-wire data communication will be described below. First, data transmission from the control device 300 to the data carrier device 301 will be described. A DATA pulse is input to the clock generation circuit, and a differential signal having a pulse in phase with the input pulse and a pulse in reverse phase are output to the output A and output B of the clock generation circuit 304, respectively. Further, the amplitude of the output pulse at that time is changed according to the transmission signal DATA, so that data is transmitted to the data carrier device 301 by changing the amplitude of the clock pulse.

  Next, data transmission from the data carrier device 301 to the control device 300 will be described. The input impedance of the data carrier device 301 changes depending on the voltage level of the transmission signal DATA2 of the data carrier device 301, and the amplitude of the output pulse is modulated. Similarly to the above, the control device 300 receives data by the amplitude change.

  As described above, in the conventional two-wire data communication device, the data voltage is superimposed on the operating voltage supplied to the data carrier device 301 in communication between both devices, so that only two contact points are used. The power supply to the data carrier device 301 and the data communication are realized.

In addition, as shown in FIG. 9, two-wire data communication in which the pulse width is changed has been proposed (Patent Document 2).
JP 2003-069653 A JP 2003-169002 A Japanese Patent Laid-Open No. 2003-110470

  However, in the conventional two-wire data communication apparatus, data is received by detecting the difference in signal amplitude, but the voltage level for detecting the signal amplitude differs depending on the transmission / reception communication direction. That is, even when the voltage level condition that allows data communication in one direction when the variation of various components such as equivalent resistance is large, a sufficient amplitude difference cannot be secured in the reverse direction, and data communication cannot be performed. There was a problem.

  In order to solve this problem, as described in Patent Document 3, a proposal has been made to secure a voltage level necessary for bidirectional communication by adding a circuit for switching an operating voltage during transmission and reception.

  However, by adding a new transmission / reception switching signal, the control becomes complicated, the data is erroneously detected when noise is applied to the differential clock, and the amplitude is modulated, so that the signal is supplied. There is a problem that the operating voltage fluctuates, and further improvement is desired.

  Further, the device that performs data communication by changing the pulse width described in Patent Document 2 arranges a plurality of resistors in series, switches between conduction and non-conduction, and changes the voltage level. Therefore, the output impedance is large. Therefore, there is a demerit that makes it difficult to select parts of the receiving circuit section. In addition, there is a method of lowering the output impedance by reducing the resistance, but conversely has a demerit that loss is increased. As a further problem, since the clock generation means is provided after the rectifier circuit, there is a problem that the clock pulses.

  In order to solve the above-described various problems of the prior art, the object of the present invention is to detect one signal reception by using a pulse before the rectifier circuit, by detecting a difference in frequency or duty, not by the amplitude of the clock. It is an object of the present invention to provide a two-wire data communication apparatus that realizes bidirectional data communication that is stable in operation voltage and is not easily affected by noise with an easy configuration.

  A first invention according to the present invention includes a first transmission / reception device and a second transmission / reception device, and performs two-wire data communication between the transmission / reception devices through first and second contacts. The first transmission / reception device includes a first power generation unit that generates an operating voltage, a first clock supply unit that supplies a pulse to the first or second contact, and a duty of the clock. As a first received signal, a duty setting means capable of setting a plurality of pulses, a second clock supply means for supplying a pulse having an inverted relationship to the pulse to the other contact point supplied by the clock generating means, The second transmission / reception apparatus includes a storage unit that stores predetermined information transmitted thereto, a first detection unit, a second storage unit, and a second detection unit that detects a current flowing through the first or second contact. Received to contact A second power source generating means for generating an operating voltage from the signal, a delay means for delaying the signal at the first or second contact, a comparing means for comparing with a reference voltage, and in synchronization with the transmitted clock. , Data receiving means for capturing data, and second control means for changing the impedance between the first and second contacts according to the second transmission signal, and changing the duty of the clock to obtain the data Two-wire data communication to be transmitted.

  According to a second aspect of the present invention, in the data communication circuit according to the first aspect, the power supply generation unit includes a circuit that performs full-wave rectification between the first and second contacts.

  A third invention according to the present invention has a first transmission / reception device and a second transmission / reception device, and meets the first and second contacts to perform data communication between the running reception devices. In the data communication, the first transmission / reception device includes: a first power generation unit that generates an operating voltage; a first clock supply unit that supplies a pulse to the first or second contact; A frequency setting means capable of setting a plurality of frequencies; a second clock supply means for supplying a pulse having an inversion relationship with the pulse to the other contact provided by the clock generation means; A current detection means for detecting a current flowing through the first or second contact as a received signal is provided, while the second transmission / reception device includes a storage means for storing transmitted predetermined information, Signal received at the second contact In synchronization with the transmitted clock, the second power generation means for generating the operating voltage, the delay means for delaying the signal of the first or second contact, the comparison means for comparing with the reference voltage, Data receiving means for capturing data, and second control means for changing the impedance between the first and second contacts in accordance with the second transmission signal, and transmitting data by changing the frequency of the clock 2-wire data communication.

  According to a fourth aspect of the present invention, in the data communication circuit according to the third aspect of the present invention, the power generation means includes a circuit that performs full-wave rectification between the first and second contacts.

  According to a fifth aspect of the present invention, in the data communication circuit according to the third to fourth aspects of the present invention, the clock supplied by the clock supply means has an extremely long duty setting as compared with the L level during the H level. Shall.

  According to a sixth aspect of the present invention, in the data communication means according to the third to fourth aspects of the present invention, the data communication means includes a duty setting means capable of setting a plurality of clock duties supplied by the clock supply means. When the frequency is high, the L level period is set longer than the H level, and when the supplied clock frequency is low, the H level period is set longer than the L level. Suppose that

  According to the first invention, since data transmission is performed by changing the duty, the operating voltage range can be wider than that of amplitude modulation, so that both stable power supply and accurate data transmission can be achieved.

  According to the second invention, since the full-wave rectification is performed between the first and second contacts to generate the operating voltage, stable power supply can be realized.

  According to the third aspect of the invention, since data transmission is performed by changing the frequency, the operating voltage range can be made wider than amplitude modulation, so that stable power supply and accurate data transmission can both be achieved.

  According to the fourth aspect of the present invention, since full-wave rectification is performed between the first and second contacts to generate an operating voltage, stable power supply can be realized.

  According to the fifth aspect, since the “H” level time is set to be long, charges can be accumulated as much as possible, and “H” level and “L” level can be detected even if the frequency is not so low. It becomes possible to do. Therefore, the communication time can be advanced.

  According to the sixth aspect of the invention, since the duty is changed according to the clock frequency to be transmitted, the “H” level and the “L” level can be detected more easily and erroneous detection can be eliminated. it can. Therefore, a two-wire data communication apparatus that can reliably transmit and receive data can be realized.

  As described above, according to the present invention, since data is transmitted by duty modulation, a wider operating voltage can be secured compared to amplitude modulation. Moreover, the voltage drop is suppressed as much as possible by supplying the clocks in an inverted relationship to the two contacts and performing full-wave rectification of the voltage between the two points. Therefore, even if a power supply drop occurs due to a skew or an overshoot of the differential clock transmitted between the two points, a stable power supply that does not fall below the operating voltage becomes possible.

  Further, regarding data reception, since data is received by detecting current instead of amplitude difference, data communication that is less susceptible to overshoot or undershoot due to noise or the like is also possible.

  Further, since the above problem can be solved, even if the operating voltage is set low, data transfer is possible, and the operating voltage can be set as low as possible. Accordingly, power consumption can be suppressed.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to examples.

  FIG. 1 shows a typical two-wire data communication circuit according to the first embodiment of the present invention. In this data communication circuit, two first transmission / reception units 100 and two second transmission / reception units 200 are provided. Data communication can be performed via the contacts A and B. First, the configuration of the data communication system according to the first embodiment will be described with reference to FIG. The first transmission / reception unit 100 includes a clock generation circuit 101 that can change a clock duty, a clock generation unit 101 that generates a clock pulse signal composed of inverter elements 104a to 104c and a clock pulse of the opposite phase, and a reception The current detection circuit 105 detects the direction of the current flowing through the resistor as a signal.

  On the other hand, the second transmission / reception unit 200 compares the full-wave rectification circuit 202 that rectifies the voltage between the contacts A and B, the integration circuit 205 composed of a resistor and a capacitor, and the voltage at the point C and the reference voltage. A comparator 206; a D flip-flop circuit 207 that captures input data at point D in synchronization with the transmitted clock; a control circuit 203 that controls a control signal that changes impedance as a transmission signal and communicates with a memory; The memory 204 is used as a storage means.

  Next, the operation of this embodiment will be described. First, data transfer from the first transmission / reception unit 100 to the second transmission / reception unit 200 is performed as follows. In the first transmission / reception unit 100, an operation clock for communication is generated by the ASIC 103 and transmitted to the second transmission / reception unit 200. The ASIC 103 is supplied with a reference clock and transmission data, and the duty of an operation clock generated from the reference clock can be changed according to the transmission data. Further, it is desirable that the duty ratios of the clock pulses differ greatly. The operation clock generated in this way is divided into two systems, one system passes the inverter element 104c through one stage, and the other is passed through two stages of the inverter elements 104a and 104b, thereby reversing the clock pulse in phase with the operation clock. Phase clock pulses are output and transmitted to the second transmitting / receiving unit 200 through two contacts.

  In the second transmitting / receiving unit 200, first, full-wave rectification is performed on the voltage between the point A and the point B to generate an operating voltage. Next, a method for detecting the magnitude of the duty from the voltage at the point A will be described with reference to FIG. FIG. 2 shows a timing chart at the time of transmission and reception according to the first invention. In the first embodiment, an integrating circuit 205 made of RC is used to delay the signal. In the integrating circuit 205, when the potential at the point A becomes “H” level, the charge is slowly accumulated by a curve determined by the time constant R6 × C2, and when the potential becomes “L” level, the charge is not accumulated. Works to escape. That is, as the duty is changed and the “H” level time is longer, more charges are accumulated at the point C, and as the “L” level time is longer, charges are not accumulated at the point C. Further, when the potential at the point C is switched from the “H” level to the “L” level, the diode and the resistor are connected in parallel so that the charge accumulated at the point C is easily released.

  Next, by comparing the potential accumulated at the point C with the reference voltage Vref by the comparator 206, it is possible to detect the potential difference caused by the difference in duty. When it is higher than the reference voltage Vref, it outputs “H” level, and when it is lower, it outputs “L” level. The D flip-flop 207 captures data in synchronism with the output potential of the point C output in this manner. In addition, when the point B, which is in reverse phase to the operation clock, is connected to the clock of the D flip-flop 207, the data may be taken in synchronization with the rising edge. This makes it possible to capture the change in duty as transmission data. That is, the second transmission / reception unit 200 can receive transmission data from the first transmission / reception unit 100.

  Next, an operation when the first transmission / reception unit 100 receives data from the second transmission / reception unit 200 will be described. Based on the second transmission signal DATA2 from the control circuit 203, the switching of the switching element 202 is switched ON / OFF of the resistor R5.

When the switching element 202 is turned on, R5 becomes conductive and the input impedance of the second transmitting / receiving unit 200 decreases, so that the terminal voltage between the contacts A and B decreases from V _H to V _Load , and the current flowing through the resistor R2 The value changes. By detecting this, an ON / OFF signal that is transmission data can be received, and communication from the second transmission / reception unit 200 to the first transmission / reception unit 100 becomes possible.

  In the first embodiment, as illustrated in FIG. 1, the receiving circuit unit 105 is configured to detect a potential difference between both ends by a comparator 106 with a current flowing through a resistor R2. Next, the operation in this configuration will be specifically described with reference to FIG. FIG. 3 is an operation timing chart when the first transmission / reception unit 100 receives data from the second transmission / reception unit 200. When the switching element 202 is turned on, as described above, since the input impedance becomes low, the current flowing through the resistor R5 increases, and the output signal RD2 of the comparator 106 is “H” at the same timing as the operation clock. The level and “L” level are switched. The CPU 101 takes in the output signal RD2 in synchronization with the rising edge of the operation clock. As a result, the CPU 101 can read the period in which the output signal RD2 is at the “H” level, and thus can determine the “H” level. Therefore, the first transmission / reception unit 100 can receive data “H” from the second transmission / reception unit 200.

  On the other hand, when the switching element 202 is turned OFF, the input impedance becomes high, and the output signal RD2 of the comparator 106 remains at the “L” level. The CPU 101 takes in the output signal RD2 in synchronization with the rising edge of the operation clock. Thus, the CPU 101 can determine the “L” level, and the first transmission / reception unit 100 can receive the data “L” from the second transmission / reception unit 200.

  As described above, the transmission data from the second transmission / reception unit 200 can be realized by detecting the current flowing through the resistor.

  A representative two-wire data communication apparatus according to the second embodiment is shown in FIG. Only the signal delay circuit unit 211 different from the first embodiment will be described below. As shown in FIG. 4, the second embodiment is composed of an open drain buffer 209, a constant current source 210, and a capacitor C2. The operation will be described below. First, since the buffer 209 is open drain, the output becomes high impedance when the point A is at “H” level, and when the point A is at “L” level, the “L” level is output as it is. Therefore, when the output becomes high impedance, a circuit is formed in which the constant current source 210 and the capacitor C2 are simply connected in series, and charges are gradually accumulated from the constant current source 210 to the capacitor C2. On the other hand, when the point A is at the “L” level, the output is also at the “L” level, so that the charge accumulated in the capacitor and the new charge from the constant current source 210 escape in the direction of the arrow. Become. That is, since the second signal delay circuit 211 performs the same operation as the integration circuit 205 from RC, the same reception method as that of the first embodiment can be realized by replacing the integration circuit 205 of the first embodiment. In addition, since the other circuit configurations are completely the same, description thereof is omitted.

  Since the third embodiment differs from the first embodiment only in the data transfer method from the first transmission / reception unit 100 to the second transmission / reception unit 200, only the data transfer method will be described here. The second embodiment is characterized in that the frequency of the operation clock is changed according to transmission data, and can be realized by connecting a frequency divider circuit 107 that changes the frequency division ratio according to transmission data as shown in FIG. it can. FIG. 6 shows a timing chart at the time of transmission / reception according to the third embodiment, and the operation at the time of transmission / reception will be described based on this timing chart.

  In the third embodiment, the operation clock operates at a constant duty. When the transmission data is “H” level, the frequency is lowered, and when the transmission data is “L” level, the frequency is increased, so that the transmission data is reduced. decide. By controlling in this way, data can be received by the same receiving circuit 208 as in the first embodiment. As described in the first embodiment, this receiving circuit detects data by the amount of charge accumulated at the point C. Further, since the amount of charge accumulated at the point C can be controlled by the length of the period during which the potential at the point A is at “H” level and the RC time constant, if the time constant is made constant, The received data is determined. Therefore, even if the duty is not changed, the “H” level period is adjusted just by adjusting the frequency, and data can be transmitted and received.

  Further, here, the signal delay circuit is constituted by an integrating circuit made of RC shown in FIG. 5, but a signal delay circuit as in the second embodiment may be used.

  The fourth embodiment is characterized in that the duty and the frequency are changed in accordance with the transmission data. FIG. 7 shows a timing chart during transmission / reception according to the fourth embodiment, and a data transmission method will be described based on this timing chart. First, as shown in FIG. 7, the first transmission / reception unit 100 has two types of clock pulses: a clock pulse with a long “L” level period when the frequency is high, and a clock pulse with a long “H” level period when the frequency is low. Send the clock. That is, the two types of clocks are switched according to the transmission data, and the clocks are transmitted to the second transmission / reception unit 200. This causes a sufficient difference in the “H” level period between the two types of clocks.

  As already described, the charge accumulation amount at point C is determined in the “H” level period at point A if the RC time constant is constant. Therefore, it is possible to give a wide range to the amount of charge accumulated by properly using the two clocks. Accordingly, a sufficient potential difference (Va, Vb) from the reference voltage Vref can be secured, and erroneous detection can be suppressed. Here, the receiving circuit 208 is the same as in the first and second embodiments, and is omitted.

Typical 2-wire data communication circuit according to the first embodiment Timing chart during data transmission operation of first transmission / reception unit Timing chart of the second transceiver unit when receiving data Typical 2-wire data communication circuit according to the second embodiment Typical 2-wire data communication circuit according to the third embodiment Timing chart at the time of data transmission operation in the third embodiment Timing chart at the time of data transmission operation in the fourth embodiment Conventional representative 2-wire data communication circuit Conventional representative two-wire data communication circuit 2

Explanation of symbols

100 First transmission / reception unit 101 Clock generation unit 102 CPU
103 ASIC
104a to 104c Inverter element 105 Current detection circuit (first receiving circuit)
106 first comparator 107 frequency divider circuit 200 second transmission / reception unit 201 full wave rectifier circuit 202 switching element 203 control circuit unit 204 storage medium 205 integrating circuit (first signal delay circuit)
206 Second comparator 207 D flip-flop 208 Second reception circuit 209 Open drain buffer 210 Constant current source 211 Second signal delay circuit 300 Control device 301 Data carrier device 302 Voltage level generation circuit 303 Data transmission circuit 304 Clock generation circuit 305 Signal detection circuit 306 LSI equivalent resistance

Claims (6)

  Two-wire data communication having a first transmission / reception device and a second transmission / reception device and performing data communication between the transmission / reception devices via first and second contacts, wherein the first transmission / reception device Includes a first power supply generation unit that generates an operating voltage, a first clock supply unit that supplies a pulse to the first or second contact, and a duty setting unit that can set a plurality of clock duties. The second clock supply means for supplying a pulse having an inversion relation with the pulse to the other contact supplied by the clock generation means, and the first reception signal flows to the first or second contact. Current detection means for detecting current is provided. On the other hand, the second transmitting / receiving device generates an operating voltage from storage means for storing the transmitted predetermined information and signals received at the first and second contacts. Do Two power generation means, a delay means for delaying the signal of the first or second contact, a comparison means for comparing with a reference voltage, and a data receiving means for capturing data in synchronization with the transmitted clock And second control means for changing the impedance between the first and second contacts according to the second transmission signal, and transmitting data by changing the duty of the clock. Communication circuit.   2. The data communication circuit according to claim 1, wherein the power generation means is a circuit that performs full-wave rectification between the first and second contacts.   Two-wire data communication having a first transmission / reception device and a second transmission / reception device and performing data communication between the transmission / reception devices via first and second contacts, wherein the first transmission / reception device Includes first power generation means for generating an operating voltage, first clock supply means for supplying a pulse to the first or second contact, and frequency setting means capable of setting a plurality of clock frequencies. And a second clock supply means for supplying a pulse having an inverted relationship to the pulse to the other contact supplied by the clock generation means, and a first reception signal as a first reception signal. Current detection means for detecting a flowing current, while the second transmission / reception device stores an operating voltage from storage means for storing the transmitted predetermined information and signals received at the first and second contacts. Second to generate A source generating means, a delay means for delaying the signal of the first or second contact, a comparing means for comparing with a reference voltage, a data receiving means for capturing data in synchronization with a transmitted clock, And a second control means for changing the impedance between the first and second contacts according to the second transmission signal, and transmitting data by changing the frequency of the clock. .   4. The data communication circuit according to claim 3, wherein the power generation means is a circuit that performs full-wave rectification between the first and second contacts.   5. The data communication circuit according to claim 3, wherein the clock supplied by the clock supply means has a duty setting that is extremely long compared to the L level during the H level.   5. The data communication means according to claim 3, further comprising: a duty setting means capable of setting a plurality of clock duties supplied by the clock supply means, and when the supplied clock frequency is high, the data communication means has an L level. A data communication circuit characterized in that the period is set to a longer duty than the H level and the period of the H level is set to a longer duty than the L level when the frequency of the clock to be supplied is low.

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