JP2014207512A - Transmission device, reception device, transmission apparatus, transmission method and reception method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem in a conventional open collector type circuit or open drain type circuit in which when a period of a low voltage on a data line is long, the power consumption gets larger.SOLUTION: A transmission device 125 includes: a microcomputer 102 that generates a data signal having a transmission waveform in which a period of Low-voltage time is shorter than a period of High-voltage time, and a clock signal having a transmission waveform in which a first rising timing is a central timing of the High time of the data signal, and a first falling timing is a timing when the voltage of the data signal is a timing the voltage begins to lower from the High-time; a pull-up resistor 103 that pulls up the voltage of the data signal; a data transmitting transistor 105 that outputs the generated data signal to the data line; and a clock transmission CMOS transistor 106 the outputs the generated clock signal to the clock line.

Description

  The present invention relates to a transmission device, a reception device, a transmission apparatus, a transmission method, and a reception method that perform wired communication using an open collector type circuit or an open drain type circuit.

  As an interface for connecting devices such as ICs in the transmission apparatus or between devices, a system using an open collector (Open-Collector) type circuit or an open drain (Open-drain) type circuit is mainly used. .

  This is because voltage levels can be easily converted when communicating between ICs of different power supply voltages, and excessive current may flow even when a plurality of ICs transmit signals simultaneously on a bus line (Bus Line). There is no such thing. However, since current flows through the pull-up resistor, there is a demerit that current consumption is larger than that of a CMOS (Complementary Metal-Oxide Semiconductor) type circuit.

  One specific example of such an interface is I2C (Inter-Integrated Circuit) (for example, Patent Document 1). An example of the configuration of the I2C is shown in FIG.

  The I2C includes a power line 201, a data line 202 (SDA, Serial Data line), a clock line 203 (SCL, Serial Clock line), two pull-up resistors 204 and 205, a first device 206, a first device 206, And a second device 207.

  The first device 206 includes a clock input buffer 208, a clock output transistor 209, a data input buffer 210, and a data output transistor 211. The second device 207 includes a clock input buffer 212, a clock output transistor 213, a data input buffer 214, and a data output transistor 215.

  When the voltage level of the data line 202 is Low, a current flows through the pull-up resistors 204 and 205. If the value of the pull-up resistor is increased, the current decreases. However, since the pull-up resistor is determined from the transmission speed and the capacitance of the bus line, the current cannot be freely changed.

  An equivalent circuit of an I2C transistor and a pull-up resistor is shown in FIGS. 2 (FIG. 3) shows a power supply line 301 (401), a pull-up resistor 302 (402), a transistor 303 (403), a transistor internal resistor 304 (404), a switch 305 (405), and a capacitor 306. (406).

  Here, the transistor 303 is expressed as an equivalent circuit in which an internal resistor 304 and a switch 305 are connected in series. The transistor 303 corresponds to the clock output transistors 209 and 213 and the data output transistors 211 and 215 in FIG. Capacitor 306 represents the capacitance of the bus line.

  FIG. 2 shows the transition state at the moment when the switch 305 is turned on, and the discharge current 307 shows the current that flows when the capacitor 306 is discharged.

  On the other hand, FIG. 3 shows the transition state at the moment when the switch 405 is turned off, and the discharge current 407 shows the current that flows when the capacitor 306 is charged. Other portions of FIG. 3 are the same as those of FIG.

  Hereinafter, the case where the pull-up resistor is 10 kΩ, the transistor internal resistance is 100Ω, the capacitor is 0.01 uF, and the power supply voltage is 3 (V) will be described in detail.

  In FIG. 2, since the capacitor 306 is discharged through the internal resistance 304 of the transistor 303, the time constant is 100 (Ω) × 0.01 (uF) = 1 (usec). On the other hand, in FIG. 3, since the capacitor 406 is charged through the pull-up resistor 402, the time constant is 10 (kΩ) × 0.01 (uF) = 100 (usec).

  Therefore, in the case of FIG. 3, the time constant is 100 times that of FIG. 2, and it can be seen that charging is slower than discharging.

  Transmission waveform (voltage waveform at both ends of capacitor 306 (or capacitor 406)) when switch 305 in FIG. 2 (or switch 405 in FIG. 3) repeats ON / OFF in a predetermined cycle (here, 400 (usec)) An example of the consumption current waveform is shown in FIG. As shown in FIG. 4, the time when the switch is turned on and the time when it is turned off are the same length.

  As the value of the pull-up resistor increases, the time constant increases, and as a result, the rising waveform of the transmission waveform becomes smoother. Therefore, a clear rise of the transmission waveform cannot be obtained, and there is a possibility that the high level is overlooked in the receiving apparatus.

  As a method for solving this problem, in order to secure a time until the transmission waveform sufficiently rises (high level time in the transmission waveform), the switch switching period is longer (in the case of FIG. 4, longer than 400 usec). By doing so, the high level and the low level of the transmission waveform can be distinguished more accurately in the receiving apparatus.

JP 2010-39803 A

  However, in the conventional open collector type circuit or open drain type circuit, current flows through the pull-up resistor when the voltage level of the data line is low. Therefore, there is a problem that the longer the switching period of the switch, the longer the time for which the voltage level becomes Low (the time of the Low level in the transmission waveform), and the greater the consumption of electric current (according to power).

  An object of the present invention is to reduce current consumption in an open collector type circuit or an open drain type circuit without changing the time (High time) when the data waveform is at a high level.

The transmitting device is configured such that the length of Low time when the voltage is Low is H and the voltage is High.
A data signal having a transmission waveform shorter than the length of the high time, the first rising timing is a timing at the center of the high time of the data signal, and the first falling timing is the voltage of the data signal. A microcomputer that generates a clock signal having a transmission waveform that begins to fall from time to Low, a pull-up resistor that pulls up the voltage of the data signal, and data that outputs the generated data signal to a data line A transmission transistor; and a clock transmission CMOS transistor for outputting the generated clock signal to a clock line.

  The receiving device includes a data signal having a transmission waveform in which the length of the low time when the voltage is low is shorter than the length of the high time when the voltage is high, and the first rising timing is the center of the high time of the data signal And a clock signal having a transmission waveform in which the first falling timing is a timing at which the voltage of the data signal starts to fall from the High time to Low, and the received unit And a microcomputer that decodes the received data signal based on a clock signal.

  According to the present invention, current consumption in an open collector type circuit or an open drain type circuit can be reduced without changing the high time of the data waveform.

The figure which shows an example of a structure of I2C Equivalent circuit diagram of I2C transistor and pull-up resistor when switch 305 is ON Equivalent circuit diagram of I2C transistor and pull-up resistor when switch 405 is OFF The figure which shows an example of the transmission waveform and consumption current waveform when a switch repeats ON / OFF with a predetermined period The figure which shows the basic composition of the device for transmission and the device for reception in 1st embodiment of this invention The figure which shows the structure of the transmission apparatus in 1st embodiment of this invention. The figure which shows an example of the transmission waveform and consumption current waveform when Low time is shorter than High time The figure which shows an example of the transmission waveform of the transmission apparatus in 1st embodiment of this invention The figure which shows an example of a structure of the communication circuit using an asynchronous process The figure which shows an example of the data frame format used by the communication using an asynchronous method The figure which shows an example of the transmission waveform of the transmission apparatus in 2nd embodiment of this invention The figure which shows the basic composition of the device for transmission in 2nd embodiment of this invention, and the device for reception The figure which shows the structure of the transmission apparatus in 2nd embodiment of this invention. Diagram showing the transmission waveform divided into small parts The flowchart figure of the decoding algorithm in 2nd embodiment of this invention The figure which shows an example of the transmission apparatus comprised by the circuit of the open collector type which communicates using a bus line between apparatuses.

The transmitting device according to the present invention includes a data signal having a transmission waveform in which the length of the low time when the voltage is low is shorter than the length of the high time when the voltage is high, and the first rising timing is the high time of the data signal And a microcomputer that generates a clock signal having a transmission waveform in which the first falling timing is a timing at which the voltage of the data signal starts to fall from High time to Low, and a voltage of the data signal A pull-up resistor for pulling up, a data transmission transistor for outputting the generated data signal to the data line, and a clock transmission CMOS transistor for outputting the generated clock signal to the clock line are included.

  With the transmission device of the present invention, current consumption in an open collector type circuit or an open drain type circuit can be reduced without changing the high time of the data waveform.

  In the transmitting device of the present invention, the clock signal has a second rising timing at the center of the low time of the data signal, and a second falling timing is the timing at which the voltage of the data signal starts to rise from the low time to high. It is good also as having the transmission waveform which is.

  As a result, in addition to the effect of the first invention, the falling time for changing from the High level to the Low level is short, so even if the Low time is shorter than the High time, the data is captured (in other words, the transmission waveform in the receiving device). The time required to distinguish the low level) can be ensured, and therefore errors during data capture can be suppressed.

  The transmission apparatus of the present invention includes a first device having the transmitting device of the present invention, a second device having a receiving device including a receiving unit and a microcomputer for receiving a data signal transmitted from the first device, and ,including.

  With the transmission device of the present invention, current consumption in a transmission device using an open collector type circuit or an open drain type circuit can be reduced without changing the High time of the data waveform.

  The receiving device of the present invention includes a data signal having a transmission waveform in which the length of the low time when the voltage is low is shorter than the length of the high time when the voltage is high, and the first rising timing is the high time of the data signal A receiving unit for receiving a clock signal having a transmission waveform at which the first falling timing is a timing at which the voltage of the data signal starts to fall from High time to Low, and a received clock And a microcomputer for decoding the received data signal based on the signal.

  With the receiving device of the present invention, current consumption in an open collector circuit or an open drain circuit can be reduced without changing the high time of the data waveform.

  In the transmitting device of the present invention, when the length of one data frame format is L, the length of the Low time when the voltage is Low is equal to or less than 1 / L of the length of the High time when the voltage is High. A microcomputer that generates a data signal having a certain transmission waveform, a pull-up resistor that pulls up the voltage of the data signal, and a data transmission transistor that outputs the generated data signal to a data line are included.

  The transmission device of the present invention eliminates the need for a clock line, so that it is possible to reduce the time and labor of connecting cables and the like, and an open collector circuit or an open drain circuit without changing the high time of the data waveform. The current consumption in can be reduced.

In the receiving device of the present invention, when the length of one data frame format is L, the length of the Low time when the voltage is Low is less than 1 / L of the length of the High time when the voltage is High. A reception unit that receives a data signal having a certain transmission waveform, and a transmission waveform of the received data signal is divided into a plurality of small parts based on the falling timing of the transmission waveform, and each of the divided small parts The first process and the second process are performed, and the first process includes a high time included in the small part, which is a value obtained by dividing the time of the small part by the high time included in the small part and rounded down the decimal point of the quotient. The value obtained by dividing the quotient obtained by dividing the remainder M obtained by dividing the time of the small part by the High time included in the small part by the Low time included in the small part is calculated as the number of bits in the middle Included in the part This is a process of calculating the number of bits during the Low time. The second process is a process of outputting “0” s of the bits during the Low time and subsequently outputting “1” s of the bits during the High time. And a microcomputer that outputs “0” and “1”, which are output by repeatedly performing the first process and the second process as many as a plurality of small parts, as digital data of one data frame.

  The receiving device of the present invention eliminates the need for a clock line, so that it is possible to reduce the time and labor of connecting cables and the like, and an open collector type circuit or an open drain type circuit without changing the high time of the data waveform. The current consumption in can be reduced. In addition, data can be correctly decoded from a data signal having a transmission waveform in which Low time and High time having different lengths of time are mixed in random order.

  The transmission apparatus of the present invention includes a first device having the transmitting device of the present invention and a second device having the receiving device of the present invention.

  The transmission device of the present invention eliminates the need for a clock line, so that it is possible to reduce the trouble of connecting cables and the like, and an open collector type circuit or an open drain type circuit can be obtained without changing the high time of the data waveform. Current consumption in the used transmission apparatus can be reduced. In addition, data can be correctly decoded from a data signal having a transmission waveform in which Low time and High time having different lengths of time are mixed in random order.

  The transmission method of the present invention includes a data signal having a transmission waveform in which the length of Low time when the voltage is Low is shorter than the length of High time when the voltage is High, and the first rising timing is the High time of the data signal And a clock signal having a transmission waveform in which the first falling timing is a timing at which the voltage of the data signal starts to fall from High time to Low, and the generated data signal is used as data. This is a method of outputting to a line and outputting the generated clock signal to the clock line via a CMOS type transistor.

  With the transmission method of the present invention, current consumption in an open collector type circuit or an open drain type circuit can be reduced without changing the high time of the data waveform.

  According to the receiving method of the present invention, a data signal having a transmission waveform in which the length of the low time when the voltage is low is shorter than the length of the high time when the voltage is high, and the first rising timing is the high time of the data signal And a clock signal having a transmission waveform in which the first falling timing is a timing at which the voltage of the data signal starts to fall from High time to Low, and based on the received clock signal A method of decoding a received data signal.

  With the reception method of the present invention, current consumption in an open collector circuit or an open drain circuit can be reduced without changing the high time of the data waveform.

In the transmission method of the present invention, when the length of one data frame format is L, the voltage is L
generating a data signal having a transmission waveform in which the length of the low time being ow is 1 / L or less of the length of the high time being high in voltage, and outputting the generated data signal to the data line; Is the method.

  The transmission method of the present invention eliminates the need for a clock line, so that it is possible to reduce the time and labor of connecting cables and the like in an open collector circuit or an open drain circuit without changing the high time of the data waveform. Current consumption can be reduced.

  In the receiving method of the present invention, when the length of one data frame format is L, the length of the Low time when the voltage is Low is equal to or less than 1 / L of the length of the High time when the voltage is High. A data signal having a transmission waveform is received, the transmission waveform of the received data signal is divided into a plurality of small parts based on the falling timing of the transmission waveform, and the first processing is performed for each of the divided plurality of small parts. The second process is performed, and the first process is the number of bits in the high time included in the small part obtained by dividing the value of the quotient obtained by dividing the time of the small part by the high time included in the small part. And the remainder obtained by dividing the time of the small part by the High time included in the small part and the quotient obtained by dividing the remainder M by the Low time included in the small part is included in the small part. During Low time The second process is a process of outputting “0” of the number of bits during the Low time, and subsequently outputting “1” of the number of bits during the High time. In this method, “0” and “1” output by repeatedly performing the first process and the second process for several small portions are output as digital data of one data frame.

  The receiving method of the present invention eliminates the need for a clock line, so that it is possible to reduce the time and labor of connecting a cable and the like in an open collector type circuit or an open drain type circuit without changing the high time of the data waveform. Current consumption can be reduced. In addition, data can be correctly decoded from a data signal having a transmission waveform in which Low time and High time having different lengths of time are mixed in random order.

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the present invention is not limited by this embodiment, and those skilled in the art can easily understand that it can be expressed using similar terms or similar descriptions in the same field. I will.
(Embodiment 1)
FIG. 5 is a diagram showing a basic configuration of the transmitting device and the receiving device in the first embodiment of the present invention.

  The transmitting device 125 shown in FIG. 5 includes a data signal having a transmission waveform in which the length of Low time when the voltage is Low is shorter than the length of High time where the voltage is High, and the first rising timing is the data signal. A microcomputer 102 that generates a clock signal having a transmission waveform that is a timing at the center of the high time and a first falling timing is a timing at which the voltage of the data signal starts to fall from the high time to low, and data A pull-up resistor 103 that pulls up the voltage of the signal; a data transmission transistor 105 that outputs the generated data signal to the data line; and a clock transmission CMOS transistor 106 that outputs the generated clock signal to the clock line; ,including.

  The receiving device 126 shown in FIG. 5 includes a data signal having a transmission waveform in which the length of Low time when the voltage is Low is shorter than the length of High time when the voltage is High, and the first rising timing is the data signal. A receiving unit 115 for receiving a clock signal having a transmission waveform that is a timing at the center of the high time and a first falling timing is a timing at which the voltage of the data signal starts to fall from the high time to low, And a microcomputer 114 that decodes the received data signal based on the received clock signal.

  With these structures, current consumption in an open collector circuit or an open drain circuit can be reduced without changing the High time of the data waveform.

  FIG. 6 is a diagram illustrating the configuration of the transmission apparatus according to the first embodiment of the present invention. As shown in FIG. 6, the transmission apparatus of the present invention includes a first device 101 having a transmitting device 125 and a second device 113 having a receiving device 126. The first device 101 and the second device 113 are connected from a data signal cable 122 corresponding to a data line, a clock signal cable 123 corresponding to a clock line, and a ground cable 124 corresponding to a ground line. .

  The first device 101 includes a microcomputer 102, a data line pull-up resistor 103, a power line 104, a data transmission transistor 105, a clock transmission CMOS transistor 106, a data line 107, and a clock line 108. , A ground line 109, a data connector 110, a clock connector 111, and a ground connector 112.

  The second device 113 includes a microcomputer 114, a receiving unit 115, a data line 116, a clock line 117, a ground line 118, a data connector 119, a clock connector 120, and a ground connector 121.

  FIG. 7 shows an example of a transmission waveform and a consumption current waveform when the Low time is shorter than the High time. Since the internal resistance of the transistor is usually smaller than that of the pull-up resistor, the fall time of the transmission waveform is shorter than the rise time as shown in FIG. In the open collector type circuit or the open drain type circuit, the current consumption is large only during the low time during which the current flows through the pull-up resistor. Considering these, the current consumption can be reduced by shortening only the Low time without changing the High time.

  Also, since the fall time for changing from the High level to the Low level is short, even if the Low time is shorter than the High time, it is necessary to capture data (in other words, to identify the Low level of the transmission waveform in the receiving device). Since time can be ensured, errors in capturing data can be suppressed.

  When the above method for reducing the Low time to be shorter than the High time is applied to the transmission apparatus that transmits the data signal and the timing signal (here, the clock signal), the falling of the clock signal is caused during the Low time of the data signal. There must be.

  Therefore, the clock signal circuit is not an open collector type circuit or an open drain type circuit having a large time constant for rising of the transmission waveform, but a CMOS type circuit. 5 and 6, a clock transmission CMOS transistor 106 is provided as a CMOS type clock transmission transistor.

  FIG. 8 shows an example of a transmission waveform of the transmission device according to the first embodiment of the present invention. As shown in FIG. 8, the microcomputer 102 generates a data signal whose Low time is shorter than the High time. Then, the generated data signal is transmitted to the second device 113 via the data connector 110.

The microcomputer 102 generates a clock signal whose rising timing is the center of each bit of the data signal. More specifically, as shown in FIG. 8, the microcomputer 102 determines that the first rising timing is the timing at the center of the high time of the data signal, and the first falling timing is the voltage of the data signal being high. A clock signal having a transmission waveform that is a timing at which the time starts to fall from time to low is generated.

  The clock signal has a transmission waveform in which the second rising timing is the timing at the center of the low time of the data signal, and the second falling timing is the timing at which the voltage of the data signal starts to rise from the low time to high. . Then, the generated clock signal is transmitted to the second device 113 via the clock connector 111.

  In this way, the current consumption can be reduced by transmitting the data signal whose data signal low time is shorter than the high time. The High time is set as a time required for the rise of the waveform corresponding to the time constant to exceed the threshold level used for digital value determination on the receiving side.

Furthermore, by transmitting a clock signal that rises at the center of the bit of the data signal, the interval between the front data and the rear data necessary for capturing data on the receiving side is provided without any bias, and the influence of noise, etc. It is possible to suppress errors at the time of taking in data.
(Embodiment 2)
When connecting devices with cables or the like, it is required to perform communication with as few lines as possible in order to save the trouble of connecting cables and the like. As a method of reducing the number of lines, there is a method of performing communication by reducing clock lines by eliminating the need for timing signals (here, clock signals) using an asynchronous method.

  An example of the configuration of a communication circuit using the start / stop synchronization method is shown in FIG. 9, and an example of a data frame format used in communication using the start / stop synchronization method is shown in FIG.

  The circuit shown in FIG. 9 includes a power supply line 801, a data line 802, a pull-up resistor 803, a first device 804, and a second device 805.

  The first device 804 includes a data input buffer 806 and a data output transistor 807, and the second device 805 includes a data input buffer 808 and a data output transistor 809.

  The data frame format shown in FIG. 10 includes a start bit (ST) 901, 8-bit data bits (b0, b1, b2, b3, b4, b5, b6, b7) 902, and a parity bit (P) 903. , And stop bits (SP) 904. Reference numeral 905 denotes the falling timing of the start bit 901, 906 denotes the center timing of the first data bit b0, and 907 denotes the center timing of the second data bit b1.

  As a method of synchronization on the receiving side when using the start-stop synchronization method, synchronization is performed by estimating the center timing of each bit from the falling edge of the start bit.

  As an example, a description will be given with reference to FIG. First, the center timing 906 of the first data bit b0 is the timing when 1.5 times the time width of 1 bit has elapsed since the falling timing 905 of the start bit 901. In the second device 805, the first data bit b0 is captured at the center timing 906 of the first data bit b0.

Thereafter, the timing at which 1 bit has elapsed from the center timing 906 of the first data bit b0 is the center timing of the second data bit b1. Second device 80
5, the second data bit b1 is captured at the center timing 907 of the second data bit b1. Thereafter, in the second device 805, the data bits b2, b3, b4, b5, b6, b7 after the second data bit b1 are sequentially fetched at the center timing of each data bit every time 1 bit elapses. .

  FIG. 11 shows an example of a transmission waveform of the transmission apparatus according to the second embodiment of the present invention. As shown in the upper part of FIG. 11, if the high time and the low time are the same in the transmission waveform of the data signal, the receiving side can be synchronized using the synchronization method described above. However, as shown in the lower part of FIG. 11, when the time length differs between the Low time and the High time in the transmission waveform of the data signal, the center timing of each data bit is estimated from the falling edge of the start bit. The method cannot be used.

  Therefore, a decoding algorithm for correctly decoding data bits from a waveform of a data signal in which Low time and High time having different lengths are mixed in random order needs to be newly installed in the microcomputer.

  FIG. 12 is a diagram showing a basic configuration of a transmitting device and a receiving device in the second embodiment of the present invention.

  In the transmitting device 1019 shown in FIG. 12, when the length of one data frame format is L, the length of the Low time when the voltage is Low is equal to L times the length of the High time when the voltage is High. A microcomputer 1002 that generates a data signal having a transmission waveform equal to or less than 1, a pull-up resistor 1003 that pulls up the voltage of the data signal, and a data transmission transistor 1005 that outputs the generated data signal to the data line. Including.

  This eliminates the need for a clock line, thus reducing the time and effort required to connect cables and the like, and reducing current consumption in an open collector circuit or open drain circuit without changing the high time of the data waveform. can do.

  In the receiving device 1020 shown in FIG. 12, when the length of one data frame format is L, the length of the Low time when the voltage is Low is equal to L times the length of the High time when the voltage is High. The receiving unit 1012 that receives a data signal having a transmission waveform that is less than or equal to 1, and the transmission waveform of the received data signal is divided into a plurality of small parts based on the falling timing of the transmission waveform, and the divided plurality The first process and the second process are performed for each small part of the first part. The first process is obtained by dividing the value obtained by dividing the time of the small part by the High time included in the small part and rounding off the decimal part of the quotient. And the quotient obtained by dividing the remainder M obtained by dividing the time of the small part by the High time contained in the small part by the Low time contained in the small part. Four This is a process of calculating the five-valued value as the number of bits in the low time included in the small part, and the second process outputs several “0” bits in the low time, and subsequently, the bits in the high time This is a process of outputting several “1” s, and the “0” and “1” output by repeating the first process and the second process for a number of small portions are digital data of one data frame. And a microcomputer that outputs as

  This eliminates the need for a clock line, thus reducing the time and effort required to connect cables and the like, and reducing current consumption in an open collector circuit or open drain circuit without changing the high time of the data waveform. can do. In addition, data can be correctly decoded from a data signal having a transmission waveform in which Low time and High time having different lengths of time are mixed in random order.

FIG. 13 is a diagram illustrating a configuration of a transmission apparatus according to the second embodiment of the present invention. FIG.
As shown in FIG. 1, the transmission apparatus of the present invention includes a first device 1001 having a transmitting device and a second device 1010 having a receiving device. The first device 1001 and the second device 1010 are connected from a data signal cable 1017 corresponding to the data line and a ground cable 1018 corresponding to the ground line.

  The first device 1001 includes a microcomputer 1002, a data line pull-up resistor 1003, a power supply line 1004, a data transmission transistor 1005, a data line 1006, a ground line 1007, a data connector 1008, and a ground connector 1009. It consists of.

  The second device 1010 includes a microcomputer 1011, a receiving unit 1012, a data line 1013, a ground line 1014, a data connector 1015, and a ground connector 1016.

  Hereinafter, the decoding algorithm of the present invention implemented in the microcomputer will be described. Here, let L be the length (or the number of bits) of one character (data frame). For example, in the data frame format as shown in FIG. 10, since the start bit is 1 bit, the data bit is 8 bits, the parity bit is 1 bit, and the stop bit is 1 bit, L = 1 + 8 + 1 + 1 = 11. The length of the Low time is set to 1 / L or less of the length of the High time. Table 1 shows an example of the relationship between the configuration of other characters (data frame format) and L.

  In the decoding algorithm of the present invention, for example, the transmission waveform of a data signal having a data frame format as shown in FIG. 10 is divided into a plurality of small parts based on the falling timing of the transmission waveform. FIG. 14 shows how the transmission waveform is divided into small parts. The length of time of each small part is obtained by measuring the difference between a certain falling timing and the next falling timing. This measurement is easily realized by, for example, a method of recording the count value of the counter.

The small portion is composed of a first half portion consisting of a continuous low level of 1 bit or more and a second half portion consisting of a continuous high level of 1 bit or more. One small part is defined as a section from one fall timing to the next fall timing. That is, one small part always starts from the Low level and ends at the High level.

  On the receiving side, in order to determine the low level and high level from the transmission waveform and determine the digital value, for each small portion, how many bits of the first low level portion and how many bits of the second high level portion are included You need to get it. For this purpose, the receiving side microcomputer calculates the number of bits in the Low time and the number of bits in the High time using the decoding algorithm described below for the transmission waveform, and the digital value for one character (data frame) is calculated. It is determined.

  FIG. 15 shows a flowchart of the decoding algorithm in the second embodiment of the present invention. Here, the variable R is the number of bits stored in the memory, and the variable C is a counter variable that measures the time from when the fall of the received transmission waveform is detected until the next fall is detected (that is, 1 Two sub-portions), TH is High time, and TL is Low time.

  Hereinafter, each process in the microcomputer 1011 will be described with reference to FIG.

  When the transmission waveform is received via the receiving unit 1012, the microcomputer 1011 starts processing of the decoding algorithm (1301).

  First, a variable R indicating the number of bits stored in the memory is initialized to zero (1302). Next, as a start bit wait process (1303), it is determined whether or not the falling edge of the transmission waveform is detected (1304). If a falling edge is detected, the process 1305 is continued and the falling edge is not detected. If so, the process 1304 is repeated.

  When the falling edge of the transmission waveform is detected, the counter variable C is initialized to zero (1305). Then, as a transmission waveform fall waiting process (1306), the counter variable C is incremented by 1 (1307), and it is determined whether the next fall of the transmission waveform is detected (1308). As a result of the determination, if a falling edge is detected, the process 1309 is continued. If a falling edge is not detected, the process returns to the process 1307 to continue the process.

  By repeatedly performing the processing 1307 and the processing 1308, the time of one small portion is measured, and the counter number is stored in the variable C as the time of one small portion. One counter corresponds to a predetermined unit time (for example, 1 (usec)).

  Next, the number of bits of the first half level and the number of bits of the second half level included in one small part are calculated (1309). Specifically, a value obtained by dividing the counter variable C by the high time TH and rounded down the decimal point of the quotient is calculated as the number of high-level bits NH in the latter half. Further, a value obtained by rounding a remainder obtained by dividing the counter variable C by the high time TH and further dividing a quotient obtained by dividing the counter variable C by the low time is calculated as the number of bits NL of the low level in the first half.

  Here, the counter variable C includes Low time and High time included in one small part. However, in the above calculation, a value obtained by dividing the counter variable C by only the high time TH and rounded down the decimal point of the quotient is calculated as the number of bits of the high level. This is because, as described above, the Low time is set to 1 / L or less of the High time, and therefore the total of all the Low times does not exceed the 1-bit High time.

  Even if the start bit, the data bit, and the parity bit fixed at the Low level in the data frame format of FIG. 10 are all at the Low level, the 1-bit High time is not exceeded. In this case, the quotient when the time of all low level data frames (counter variable C) is divided by the high time TH is less than 1, and the number of bits of the high level obtained by rounding off the decimal part of this quotient is 0 ( bit).

  The number of bits in the first half level and the number of bits in the second half level calculated by the processing 1309 are recorded in a memory (not shown). At that time, NL “0” s are written in an area free from the LSB side of the memory, and subsequently NH “1” s are written in an empty area. Further, a value obtained by adding NL and NH to the variable R is substituted for R (1310).

  Next, it is determined whether all bits included in one character (data frame) have been recorded in the memory (1311). Specifically, it is determined whether or not the variable R is equal to the number of bits L of one character (data frame) (1312). If R is not equal to L, the process returns to 1305, and the processes from 1305 to 1312 are repeated for the next small part. On the other hand, when R is equal to L, it means that the digital value for one character (data frame) has been determined, and the processing 1313 is continued.

  “0” or “1” data for one character (data frame) is read from the memory as a determined digital value (1313), and the decoding process for one character (data frame) is completed. Then, the process returns to the process 1302 again, and when the start bit of the next character (data frame) is received, the decoding process is performed.

  Hereinafter, specific numerical examples will be described. For example, when the start bit is 1 bit, the data bit is 8 bits, the parity bit is 1 bit, and the stop bit is 1 bit, the bit number L of 1 character (data frame) is 1 + 8 + 1 + 1 = 11 (bits). Further, it is assumed that High time TH = 110 (μsec) and Low time TL = 10 (μsec).

  At this time, the first small portion shown in FIG. 14 is composed of the start bit ST and the first bit B0 of the data bit, and the time of the first small portion obtained from the counter variable C is 120 (μsec).

  The number of high-level bits NH is C / TH = 120/110 = 1.0909..., And the fractional part of the quotient 1.0909 is rounded down to obtain NH = 1 (bit). Further, the remainder of 120 ÷ 110 is M = 10 (μsec). The number of bits NL at the Low level is M / TL = 10/10 = 1.0, and NL = 1 (bit) is obtained by rounding off the decimal point of the quotient 1.0.

  For data recording, digital data “0” is written to NL = 1 (bit) in an area free from the LSB side of the memory, and digital data “1” is subsequently written to NH = 1 (bit) in an empty area. It is. At this stage, the value written in the memory is {0, 1, X, X, X, X, X, X, X, X, X} (R = 2 ≠ L) with the LSB side on the left. . X represents an area not yet written.

  Next, the second small portion from the left shown in FIG. 14 is composed of the second to fifth bits B1, B2, B3 and B4 of the data bits, and the second small portion from the left obtained from the counter variable C. Is 240 (μsec).

  The number of high-level bits NH is C ÷ TH = 240 ÷ 110 = 2.1818..., And the fractional part of the quotient 2.1818 is rounded down to obtain NH = 2 (bits). The remainder of 240 ÷ 110 is M = 20 (μsec). The number of bits NL at the Low level is M / TL = 20/10 = 2.0, and NL = 2 (bits) is obtained by rounding off the decimal point of the quotient 2.0.

  As data recording, digital data “0” is NL = 2 (bits) in an area vacant from the LSB side of the memory (in this case, immediately after digital data “1” written by the decoding process for the first small portion). Then, the digital data “1” is written in the vacant area with NH = 2 (bits). At this stage, the value written in the memory is {0, 1, 0, 0, 1, 1, X, X, X, X, X} (R = 6 ≠ L) with the left as the LSB side. .

  Next, the third small portion from the left shown in FIG. 14 is composed of the sixth to eighth bits B5, B6 and B7 of the data bits, the parity bit P, and the stop bit SP, and is obtained from the counter variable C. The time of the third small part from the left is 450 (μsec).

  The number of high-level bits NH is C ÷ TH = 450 ÷ 110 = 4.0909..., And the fractional part of the quotient 4.0909 is rounded down to obtain NH = 4 (bits). The remainder of 450 ÷ 110 is M = 10 (μsec). The number of bits NL at the Low level is M / TL = 10/10 = 1.0, and NL = 1 (bit) is obtained by rounding off the decimal point of the quotient 1.0.

  As data recording, digital data “0” is NH = 4 in an area vacant from the LSB side of the memory (in this case, immediately after digital data “1” written by the decoding process for the second small portion from the left). (Bit) is written, and subsequently, digital data “1” is written to NH = 1 (bit) in an empty area. At this stage, the value written in the memory is {0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1} (R = 11 = L) with the LSB side on the left. .

  Here, since R = 11 is equal to L, it is determined that a digital value for one character (data frame) has been determined, and the decoding process for this character (data frame) is terminated. In this way, digital values {0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1} can be obtained from the received transmission waveform.

  By implementing the decoding algorithm of the present invention in a microcomputer, data can be correctly decoded from a transmission waveform in which Low time and High time having different lengths are mixed in random order. Therefore, the Low time of the transmission waveform can be made shorter than the High time, and the current consumption corresponding to the shortened Low time can be reduced.

  Here, a case where a plurality of devices are connected to the bus line by an open collector type circuit will be described. If a pull-up resistor is simply installed in the device, current flows through many pull-up resistors as the number of devices connected to the bus line increases. Will increase. Therefore, usually, the number of devices provided with the pull-up resistor is often limited to one.

  As an example of a transmission apparatus to which this limitation is applied, one of a plurality of devices is determined as a master device, and only one determined master device has a pull-up resistor, and other devices have a pull-up resistor. A transmission apparatus that is configured not to have a device is conceivable.

  Further, as another example of the transmission apparatus to which the above limitation is applied, all devices have pull-up resistors, and a switch is provided between the bus line and the pull-up resistors to perform transmission among a plurality of devices 1 A transmission apparatus configured such that only one device turns on the switch and connects a pull-up resistor is conceivable.

  FIG. 16 shows an example of a transmission apparatus configured by an open collector circuit that performs communication between devices using a bus line. The transmission apparatus shown in FIG. 16 includes a first device 1401 having a transmitting device and a second device 1412 having a receiving device. The first device 1401 and the second device 1412 are connected from a data signal cable 1423 corresponding to the data line and a ground cable 1424 corresponding to the ground line.

  The first device 1401 includes a microcomputer 1402, a pull-up resistor 1403, a power supply line 1404, a transistor 1405, a receiving unit 1406, a transistor 1407, a data line 1408, a ground line 1409, a data connector 1410, And a ground connector 1411.

  The second device 1412 includes a microcomputer 1413, a pull-up resistor 1414, a power supply line 1415, a transistor 1416, a receiver 1417, a transistor 1418, a data line 1419, a ground line 1420, a data connector 1421, And a ground connector 1422.

  When data is transmitted from the first device 1401 to the second device 1412, first, the transistor 1405 in the first device 1401 is turned on, the data line 1408 is pulled up, and the voltage level changes from low to high. To do. At the same time, the voltage level of the data line 1419 in the second device 1412 similarly changes from Low to High. At that time, the transistor 1416 in the second device 1412 remains OFF.

  When the transistor 1407 in the first device 1401 is turned on, the voltage level of the data line 1408 becomes Low, so that the digital signal “0” is transmitted. When the transistor 1407 is turned off, the voltage level of the data line 1408 is transmitted. Becomes “High”, so that the digital signal “1” is transmitted.

  In addition, by implementing the decoding algorithm of the present invention in the microcomputer of each device with respect to the transmission apparatus shown in FIG. 16, from the transmission waveform in which Low time and High time having different lengths are mixed in random order. Data can be correctly decrypted. Therefore, the Low time of the transmission waveform can be made shorter than the High time, and the current consumption corresponding to the shortened Low time can be reduced.

  As described above, the device, the device, the transmission apparatus, and the communication method according to the present invention are applied to communication between devices such as an IC inside the device, communication between devices when the devices are connected with a cable or the like. Can do.

101, 1001, 1401 First device 102, 114, 1002, 1011, 1402, 1413 Microcomputer 103, 1003 Pull-up resistor 104, 201, 301, 401, 801, 1004, 1404, 1415 Power line 105, 1005 For data transmission Transistor 106 CMOS transistor for clock transmission 107, 116, 202, 802, 1006, 1013, 1408, 1419 Data line 108, 117, 203 Clock line 109, 118, 1007, 1014, 1409, 1420 Ground line 110, 119, 1008 1015, 1410, 1421 Data connector 111, 120 Clock connector 112, 121, 1009, 1016, 1411, 1422 Ground connector 113, 1010 1412 Second device 115, 1012, 1406, 1417 Reception unit 122, 1017, 1423 Data signal cable 123 Clock signal cable 124, 1018, 1424 Ground cable 125, 1019 Transmission device 126, 1020 Reception device 204, 205, 302 402, 803, 1403, 1414 Pull-up resistors 206, 804 First device 207, 805 Second device 208, 212 Clock input buffer 209, 213 Clock output transistors 210, 214, 806, 808 Data input buffers 211, 215 , 807, 809 Data output transistors 303, 403, 1405, 1407, 1416, 1418 Transistors 304, 404 Internal resistors 305, 405 Switches 306, 40 6 Capacitors 307, 407 Discharge current

Claims (11)

A data signal having a transmission waveform in which the length of the low time when the voltage is low is shorter than the length of the high time when the voltage is high, and the first rising timing is a timing at the center of the high time of the data signal, And a microcomputer that generates a clock signal having a transmission waveform in which the first falling timing is a timing at which the voltage of the data signal starts to fall from the High time to Low,
A pull-up resistor for pulling up the voltage of the data signal;
A data transmission transistor for outputting the generated data signal to a data line;
A clock transmitting CMOS transistor for outputting the generated clock signal to a clock line;
Including sending devices. The clock signal has a transmission waveform in which the second rising timing is a timing at the center of the low time of the data signal, and the second falling timing is a timing at which the voltage of the data signal starts to rise from the Low time to High. Having
The transmission device according to claim 1. A first device comprising the transmitting device according to claim 1;
A second device having a receiving device including a receiving unit and a microcomputer for receiving a data signal transmitted from the first device;
Including transmission equipment. A data signal having a transmission waveform in which the length of the low time when the voltage is low is shorter than the length of the high time when the voltage is high, and the first rising timing is a timing at the center of the high time of the data signal, And a reception unit that receives a clock signal having a transmission waveform in which the first falling timing is a timing at which the voltage of the data signal starts to fall from the High time to Low,
A microcomputer that decodes the received data signal based on the received clock signal;
Including receiving devices. When the length of one data frame format is L, a data signal having a transmission waveform in which the length of the Low time when the voltage is Low is 1 / L or less of the length of the High time when the voltage is High A microcomputer to generate,
A pull-up resistor for pulling up the voltage of the data signal;
A data transmission transistor for outputting the generated data signal to a data line;
Including sending devices. When the length of one data frame format is L, a data signal having a transmission waveform in which the length of the Low time when the voltage is Low is 1 / L or less of the length of the High time when the voltage is High A receiving unit for receiving;
Based on the falling timing of the transmission waveform, the transmission waveform of the received data signal is divided into a plurality of small parts,
The first process and the second process are performed for each of the divided small parts,
The first process calculates a value obtained by dividing the time of the small part by the High time included in the small part and rounded down the decimal point of the quotient as the number of bits in the High time included in the small part, The Low time included in the small portion is a value obtained by rounding off the quotient obtained by dividing the remainder M obtained by dividing the time of the small portion by the High time included in the small portion and the Low time included in the small portion. It is a process to calculate as the number of bits in,
The second process is a process of outputting several “0” bits during the Low time, and subsequently outputting several “1” bits during the High time,
A microcomputer that outputs "0" and "1" output by repeatedly performing the first process and the second process for a number of the plurality of small portions as digital data of one data frame;
Including receiving devices.   A transmission apparatus comprising: a first device having the transmission device according to claim 5; and a second device having the reception device according to claim 6. A data signal having a transmission waveform in which the length of the low time when the voltage is low is shorter than the length of the high time when the voltage is high, and the first rising timing is a timing at the center of the high time of the data signal, And a clock signal having a transmission waveform in which the first falling timing is a timing at which the voltage of the data signal starts to fall from the High time to Low, and
Outputting the generated data signal to a data line;
A transmission method for outputting the generated clock signal to a clock line via a CMOS transistor. A data signal having a transmission waveform in which the length of the low time when the voltage is low is shorter than the length of the high time when the voltage is high, and the first rising timing is a timing at the center of the high time of the data signal, And a clock signal having a transmission waveform in which the first falling timing is a timing at which the voltage of the data signal starts to fall from the High time to Low, and
A receiving method for decoding the received data signal based on the received clock signal. When the length of one data frame format is L, a data signal having a transmission waveform in which the length of the Low time when the voltage is Low is 1 / L or less of the length of the High time when the voltage is High Generate
A transmission method for outputting the generated data signal to a data line. When the length of one data frame format is L, a data signal having a transmission waveform in which the length of the Low time when the voltage is Low is 1 / L or less of the length of the High time when the voltage is High Receive
Based on the falling timing of the transmission waveform, the transmission waveform of the received data signal is divided into a plurality of small parts,
The first process and the second process are performed for each of the divided small parts,
The first process calculates a value obtained by dividing the time of the small part by the High time included in the small part and rounded down the decimal point of the quotient as the number of bits in the High time included in the small part, The Low time included in the small portion is a value obtained by rounding off the quotient obtained by dividing the remainder M obtained by dividing the time of the small portion by the High time included in the small portion and the Low time included in the small portion. It is a process to calculate as the number of bits in,
The second process is a process of outputting several “0” bits during the Low time, and subsequently outputting several “1” bits during the High time,
A receiving method in which the first process and the second process are repeated for the number of the plurality of small portions, and “0” and “1” output are output as digital data of one data frame.

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