JP2003208583A - Contact type data carrier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a contact type data carrier that can eliminate erroneous demodulation even when a skew occurs between signals applied to connection terminals VA and VB. <P>SOLUTION: The contact type data carrier rectifies signal components of opposite phases applied to the first and second connection terminals VA and VB to cover electric power for internal circuits, generates an internal processing clock signal from the opposite phase signal components, and demodulates a received signal component. An internal impedance regulating means 120 switches the impedance of the internal circuits to a high level when the opposite phase signal components are changed, and the internal circuit impedance to a low level when a data signal is demodulated. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to power, clock,
The present invention relates to a contact-type data carrier that communicates with a reader / writer unit by transmitting three signals of data with a two-wire interface.

[0002]

2. Description of the Related Art FIG. 8 shows a conventional contact type data carrier. 501 is a rectifier circuit, 502 is a received signal demodulation circuit, 5
03 is a clock generation circuit, 504 is a logic circuit, 50
5 is a non-volatile memory, 506 is a transmission signal modulation circuit, 50
Reference numerals 7 and 508 denote external connection terminals, which will be referred to as connection terminals VA and VB, respectively, in the following description.

A reader / writer unit (not shown) (hereinafter,
A signal input from the R / W) to the connection terminals VA and VB is rectified by the rectifier circuit 501 to generate the internal power supply Vdd and the internal ground Vss. At this time, the signal component is still multiplexed in the internal power supply Vdd, and the received signal demodulation circuit 502 extracts the signal component and demodulates it, whereby digital received data 513 is obtained.

The received data 513 is transferred to the logic circuit 50.
4 to perform protocol processing, and exchange data with the non-volatile memory 505 as necessary. The clock generation circuit 503 extracts a clock from the signals input to the connection terminals VA and VB, and generates an internal processing clock signal.

When transmitting data from the data carrier to the R / W, the signal is transmitted to the R / W via the connection terminals VA and VB after being modulated into a predetermined shape by the transmission signal modulation circuit 506. To do. At this time, generally, as a load switch method, a method is often used in which the impedance between the connection terminals VA and VB is switched by a switch according to transmission data, and the change in impedance is read by the R / W to perform transmission.

FIG. 9 shows an example of a concrete signal waveform when a signal is received from the R / W. As shown in the figure, the connection terminals VA, V
The waveforms of the signals applied to B are clock signals of opposite phases, and the amplitude-modulated received signal components are multiplexed and transmitted. Therefore, when the received data signal is "0" logic, the amplitude is the modulation voltage component ΔV. The waveform is lowered only by. Further, it is assumed that the timing of the change point of the received data signal is defined in the communication specifications so that it occurs in the stable "H" period of the connection terminal VA or the connection terminal VB.

From such an applied signal, an internal processing clock signal 514 is extracted by the clock generation circuit 503 of FIG. 8 as shown in the figure and provided as an operation clock of the logic circuit 504.

Further, the internal V rectified by the rectifying circuit 501
As a waveform of dd511, when the internal Vss is used as a reference, as shown in the figure, when the received data is a “0” logic, the waveform is lowered by ΔV. Further, since the voltage between the connection terminals VA and VB once drops at the clock switching point, a small noise is generated according to the impedance of the internal circuit. When this waveform is demodulated by the demodulation circuit 502, demodulated reception data 513 is obtained. Demodulation circuit 502
Is an edge detection type that detects a voltage change of a signal waveform and performs demodulation. As shown in the figure, a logical voltage "0" is detected by detecting the falling edge of the modulation voltage ΔV, and a logical edge is detected by detecting the rising edge. Outputs "1".

[0009]

SUMMARY OF THE INVENTION In the above conventional method,
When the skew between the signals applied to the connection terminals VA and VB becomes large, the noise generated in the internal Vdd 511 after rectification increases, and the signal component may be erroneously demodulated. The mechanism in this case will be described with reference to FIG.

In the figure, when skew occurs between the signals applied to the connection terminals VA and VB, the voltage drop ΔVts due to noise in the waveform of the internal Vdd 511 is the voltage drop time between the connection terminals VA and VB due to the skew, and It is determined by the discharge time constant due to the impedance of the circuit.

The demodulation characteristic of the demodulation circuit 502 is basically largely determined by the slope of the voltage change and the magnitude of the changed voltage value. However, the slope of the fall due to noise and the fall due to the signal component Both slopes are equal and are determined by the impedance of the internal circuit.

Therefore, when the voltage drop ΔVts approaches the signal modulation voltage component ΔV due to the increase of the skew Δts, the noise causes the demodulation circuit 502 to erroneously demodulate. When the impedance of the internal circuit is increased in order to suppress the increase of ΔVts, the characteristics of the demodulation circuit deteriorate, and this adversely affects the demodulation of a normal received signal.

In FIG. 10, the demodulated received data 51
3 is due to the noise due to the skew of the internal Vdd 511,
Since the logical "1" is demodulated to the logical "0", it indicates that the originally correct received data is erroneously demodulated. To prevent this, the connection terminals VA,
It is necessary to suppress the signal skew between VB, and
There is a problem that the design constraint of the circuit of W or the transmission path from the R / W to the connection terminals VA and VB becomes considerably strict and the design burden and cost burden increase.

An object of the present invention is to provide a contact type data carrier which can eliminate erroneous demodulation even when a skew occurs between the signals applied to the connection terminals VA and VB.

[0015]

According to the present invention, the R / W
It is characterized in that the impedance of the internal circuit is adjusted to be high when the clock signal changes from 0 to 1, and the impedance of the internal circuit is adjusted to be low when the signal voltage amplitude changes.

The contact type data carrier according to claim 1 of the present invention rectifies the signal components of opposite phases applied to the first and second connection terminals to cover the electric power of the internal circuit.
In the contact-type data carrier for creating an internal processing clock signal to be used in the internal circuit from the opposite phase signal component and demodulating a received signal component multiplexed with the opposite phase signal component, the opposite phase signal component Is provided with an internal impedance adjusting means for increasing the impedance of the internal circuit, the impedance of the internal circuit is increased when the signal component of the opposite phase changes, and the impedance of the internal circuit is switched low when the data signal is demodulated. It is characterized by

The contact type data carrier according to claim 2 of the present invention rectifies the signal components of opposite phases applied to the first and second connection terminals (to rectify the electric power of the internal circuit and to In a contact-type data carrier that creates an internal processing clock signal to be used in the internal circuit from a phase signal component and demodulates a received signal component multiplexed with the opposite phase signal component, depending on the polarity of the internal processing clock signal. Internal impedance adjusting means for increasing the impedance of the internal circuit is provided, and the impedance of the internal circuit is switched to high when the clock signal input from the outside changes, and the impedance of the internal circuit is switched to low when demodulating a data signal. And

The contact type data carrier according to claim 3 of the present invention rectifies the signal components of opposite phases applied to the first and second connection terminals to supply the electric power of the internal circuit.
In the contact-type data carrier that creates an internal processing clock signal to be used in the internal circuit from the opposite-phase signal component and demodulates the received signal component multiplexed in the opposite-phase signal component, The internal processing clock signal is generated based on a result of detecting the phase and a clock signal input from the outside, and a transmission clock having a higher frequency than the internal processing clock signal based on the clock signal input from the outside , A counter for counting the transmission clock to detect a change point of the data signal within the rate of the internal processing clock signal, and an internal circuit for switching the impedance of the internal circuit according to the count value of the counter. Impedance adjusting means is provided, and the count value of the counter causes the data signal To predict the reduction points, characterized in that for switching the impedance of the internal circuit.

According to a fourth aspect of the present invention, in the contact type data carrier according to any one of the first to third aspects, the element for determining the low impedance of the internal impedance adjusting means is a variable element, and the variable. The output impedance of the element is changed based on the initial setting data read from the memory.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. In addition, FIG. 8 showing a conventional example
Those having the same operation as the above will be described with the same reference numerals.

(Embodiment 1) FIGS. 1 and 2 show a contact type data carrier according to (Embodiment 1) of the present invention, in which an internal impedance adjusting means 120 is added, which is shown in FIG. Is different from. The data carrier including the internal impedance adjusting means 120 is LS.
It is configured as I.

Internal impedance adjusting means 1 for switching the impedance of the internal circuit according to the required timing
20 is a resistance element 121 and a control transistor 122,
And 123.

In this embodiment, Vdd-Vs
A resistance element 121 connected between s and control transistors 122 and 123 as switching elements detect a voltage drop between the connection terminals VA and VB due to switching of the clock signal from the R / W to control transistor. By turning off both 122 and 123, Vdd of the internal circuit
Increase the equivalent resistance between −Vss.

The internal impedance adjusting operation of the contact type data carrier configured as described above will be described below. In addition to the modulation component of the data signal, noise generated when there is a skew between the clock signals input from the R / W to the connection terminals VA and VB is superimposed on the Vdd rectified by the rectification circuit 501. Has been done. When the voltage drop due to noise increases, it becomes difficult for the reception signal demodulation circuit 502 to distinguish it from the fall due to the modulation voltage of the data signal, and erroneously demodulates from logic “1” to logic “0”.

Since the magnitude of the voltage drop due to noise is determined by the skew time and the impedance (discharge time constant) of the internal circuit, the impedance of the internal circuit may be increased to reduce the effect of the skew. In that case, since the demodulation characteristics of the received data signal are adversely affected, the impedance of the internal circuit may be lowered when demodulating the data signal, and the impedance may be raised when the input clock is switched.

In FIG. 1, except when the input clock signals to the connection terminals VA and VB are switched, for example, when the connection terminal VA has a high voltage and the connection terminal VB has a low voltage, the transistor 122 is turned on. Vdd-
Since the resistance element 121 is connected between Vss and the equivalent resistance value is low, the demodulation circuit 502 is in an advantageous state for demodulating the data signal. Here, the connection terminal V
When the switching of the input clock signal to A, VB occurs, when the connection terminal VA that has been a high voltage drops to a low voltage, the rectified voltage of Vdd is based on Vss, the internal circuit Although it slowly drops due to the discharge time constant, when the connection terminal VB is used as a reference, it drops sharply following the voltage of the connection terminal VA that drops.
Therefore, the gate voltage of the PMOS-structured transistor 122 (coincident with the connection terminal VB) is turned off because there is no potential difference with Vdd. Similarly, since 123 is also in the off state, the resistance element 121 is separated from between Vdd and Vss, the equivalent resistance of the internal circuit increases, and the increase in noise generated in Vdd can be suppressed.

The operation during this period will be described in more detail with reference to FIG. In FIG. 2, as an example of the rectifier circuit 501, PMOS transistors 102a, 103a, 10
4a and 105a. Reference numeral 106a denotes an impedance equivalent circuit of the entire internal circuit excluding the rectifying circuit 501 and the internal impedance adjusting means 120, and is specifically represented by the internal equivalent resistance 107a and the internal power supply capacity 108a.

When the connection terminal VA has a high potential and the connection terminal VB has a low potential, a current is supplied from the connection terminal VA to Vdd through the transistor 103a and a current flows from Vss to the connection terminal VB through the transistor 104a. . The potential difference between Vdd and Vss is determined by the connection terminal VA-
The voltage value is obtained by subtracting the voltage drop due to the ON resistance of the transistors 103a and 104a from the potential difference between VB. Here, when the input voltage of the connection terminal VA decreases, the potential of Vdd based on the potential of the connection terminal VB is clamped by the transistor 103a between the connection terminals VA and Vdd, and thus the potential of the connection terminal VA. Will fall following. The voltage between Vdd and Vss is the internal power supply capacity 108a.
Momentarily held by the transistor 104
The gate-source voltage of a decreases and 104a is turned off. As a result, when the connection terminal VA decreases to the same potential as the connection terminal VB, Vdd also decreases to the same potential as the connection terminal VB. At this time, as the operation of the internal impedance adjusting means 120, first, the connection terminal VA has a high potential and the potential of Vdd is sufficiently higher than the potential of the connection terminal VB, so that the transistor 122 is in the ON state,
The transistor 123 is off. here,
When the connection terminal VA is lowered to a low potential, the potential of the connection terminal VB is relatively high potential (V
dd potential), the transistor 122 is turned off at this time, and no current flows through the resistance element 121. Therefore, the equivalent resistance between Vdd and Vss is higher than that in the previous state. Therefore, when the input clock is switched and the voltage between the connection terminals VA and VB is reduced due to the skew, the equivalent resistance value of the internal circuit becomes high. Next, the connection terminal V by the modulation voltage of the data signal
When the voltage between A and VB decreases, the modulation voltage of the signal is about 10% or more of the amplitude of the voltage between the connection terminals VA and VB in the example currently used.
Even if A is lowered to that extent, the potential of Vdd is still sufficiently higher than the potential of the connection terminal VB, and the transistor 122 is not turned off. Therefore, in this case, Vd
The equivalent resistance between d and Vss can be kept low.

Although the description has been made by controlling the resistance value, the demodulation characteristic is determined by the discharge time constant of the internal circuit. Therefore, the method of adjusting the capacitance between internal power supplies instead of the internal resistance can also be realized.

Further, although the potentials of the connection terminals VA and VB are directly detected by the control transistor and switched, a reference potential is created in the internal circuit by the reference voltage generation circuit, and the potentials of the connection terminals VA and VB are changed. It is also possible to adopt a configuration in which the above are compared and switching is performed according to the result.

According to this structure, since the impedance of the internal circuit is high with respect to the noise due to the skew, the noise voltage can be suppressed to a low level and the risk of erroneous demodulation can be reduced. The impedance can be lowered to maintain good demodulation characteristics, and an LSI with good demodulation characteristics that is resistant to skew can be obtained.
The load on the system can be reduced.

Further, when the signal of the input clock from the R / W is switched, it is detected by a simple analog circuit and the impedance of the internal circuit is increased, so that the demodulation circuit malfunctions due to the influence of the skew between the input signals. Can be prevented and the system design load can be reduced.

(Embodiment 2) FIGS. 3 and 4 show a contact type data carrier according to (Embodiment 2) of the present invention, in which an internal impedance adjusting means 220 is added, which is shown in FIG. Is different from. The data carrier including the internal impedance adjusting means 220 is LS.
It is configured as I.

The internal impedance adjusting means 220 is configured to switch the equivalent resistance of the internal circuit by directly switching the switch element 201 by the internal processing clock signal 514.

The switch element 201 is turned on when the internal processing clock signal 514 is "H", and operates so as to reduce the equivalent resistance between Vdd and Vss. As shown in FIG. 9, the signal specifications are such that the change of the amplitude voltage due to the modulation voltage of the received data signal occurs in the “H” voltage section of the connection terminal VA. Therefore, the internal processing clock signal 5 that has the same polarity as the input clock of the connection terminal VA
By generating 14 in the clock generation circuit 503, it is possible to switch the equivalent resistance low during the "H" period of the clock in which the demodulation of the data signal occurs, and switch the equivalent resistance high during the other periods.

However, the internal processing clock signal 51
If 4 is simply made equal to the input clock characteristic of the connection terminal VA, the equivalent resistance becomes high at one of the input clocks when switching, but the equivalent resistance becomes low at the other, so the internal processing clock signal 514 It is necessary to devise it when generating. The waveform of the internal processing clock signal 514 generated will be described with reference to FIG.

The internal processing clock signal 514 is supplied to the connection terminal VB when the connection terminal VA is in the "H" period as shown in FIG.
Is "H" only during the "L" period, and the opposite case and the overlapping section due to the skew are "L". By using this signal as a control signal for the switch element 201, it is possible to control the internal equivalent resistance to be low when demodulating the data signal and to be high when switching the input clock.

Although the description has been made by controlling the resistance value, the demodulation characteristic is determined by the discharge time constant of the internal circuit, so that it can be realized by a method of adjusting the capacitance between internal power supplies instead of the internal resistance.

With this configuration, it is possible to easily change the impedance when the clock signal changes and when the received modulation signal changes by digital control, prevent erroneous demodulation due to skew, and reduce the system load. Can be reduced.

(Third Embodiment) FIGS. 5 and 6 show a contact type data carrier according to the third embodiment of the present invention, in which a control signal for driving the internal impedance adjusting means 220 is obtained from the output of the counter 301. Point is (Embodiment 2)
Is different from.

The internal impedance adjusting means 2
The data carrier including 20 and the counter 301 is configured as an LSI. Further, it is intended for communication specifications in which the frequency of the input clock from the R / W is also a multiple (twice or more) relationship with the transmission rate of the data signal received from the R / W.

The clock generation circuit 503 of this embodiment
Generates the internal processing clock signal 514 based on the result of detecting the phase of the input data signal and a clock signal input from the outside, and also performs the internal processing based on the clock signal input from the outside. The transmission clock 302 having a frequency higher than that of the clock signal 514 is output.

Specifically, the transmission clock 302 is a clock extracted from the signals input from the connection terminals VA and VB or a signal obtained by dividing the clock, and the internal processing clock signal 514 is a signal obtained by dividing the transmission clock 302. Is.

The counter 301 counts the transmission clock 302 and counts the transmission clock 302 in order to predict the timing at which the demodulation operation of the data signal occurs within the clock rate used for the internal operation. A control signal 303 for controlling the internal impedance adjusting circuit 220 is generated.

The internal impedance adjusting operation will be described with reference to the waveform example of FIG. In FIG. 6, is the R
/ W is an input signal waveform from the connection terminals VA and VB to the logic circuit 5 generated by the clock generation circuit 503.
04 is a signal waveform of an internal processing clock signal 514, is a signal waveform of a transmission clock 302 of the same frequency extracted from the clock input from the R / W, is a count value of a counter 301, is a counter 3
The signal waveform of the control signal 303 generated in 01 is V
The Vdd waveform with ss as a reference is the data value of the demodulated received data 513.

Here, an example is shown in which the transmission clock rate and the data signal rate are 1: 4. The clock generation circuit 503 adjusts the phase of the generated internal processing clock signal 514 so that the data change point of the received data signal has a constant timing.

As a result, it can be seen that the change point of the data signal occurs in the first half of the count value of the counter 301 of "1", so that the control signal 30
3 is generated and the switch element 201 of the internal impedance adjusting circuit 220 is controlled to be turned on.

In this way, it is possible to control the equivalent resistance of the internal circuit to be low at the timing of demodulating the received data signal by the reception signal demodulation circuit 502 and to increase the equivalent resistance in other periods.

Although the explanation has been made by controlling the resistance value, since the demodulation characteristic is determined by the discharge time constant of the internal circuit, it can be realized by a method of adjusting the capacitance between internal power supplies instead of the internal resistance.

According to this structure, it can be applied to a communication protocol in which the clock frequency is many times faster than the transmission rate of the data signal, and the impedance is changed by limiting the voltage amplitude change due to the data signal to some extent. LSI with good demodulation characteristics that can withstand skew
Is obtained. Further, since the period for changing the impedance can be limited to some extent, there is an advantage that extra power consumption can be reduced.

Therefore, according to the present embodiment, the counter predicts the period in which a change in the data signal occurs, lowers the impedance of the internal circuit, and raises the other periods to prevent erroneous demodulation due to skew. It can prevent and reduce the burden on the system.

(Fourth Embodiment) FIG. 7 shows a contact type data carrier according to the fourth embodiment of the present invention. Although the resistance element 121 in (Embodiment 1) is fixed, in the internal impedance adjusting means 420 in this (Embodiment 4), the portion corresponding to the resistance element 121 in (Embodiment 1) has a variable resistance element 401. Is different from that of the first embodiment in that the resistance value of the variable resistance element 401 is changed by the output of the control information register 402.

The internal impedance adjusting means 4
The data carrier including 20 and the control information register 402 is configured as an LSI. Control information register 4
02 is a variable resistance element 401 from the nonvolatile memory 505.
The optimum resistance value of the variable resistance element 401 is read out.
It operates as an initial value setting means for controlling.

A more detailed description will be given. The variable value information determined based on the measurement result at the product inspection stage is stored in a predetermined address of the non-volatile memory 505, and the initial operation when a predetermined signal is applied to the connection terminals VA and VB of the LSI. Then, the variable value information is set in the control information register 402 through the logic circuit 504.

The control information register 402 outputs the resistance value control information 403 based on the set variable value information to control the resistance value of the variable resistance element 401. The subsequent operation is as described in (Embodiment 1) above.

Therefore, the deterioration of the manufacturing yield due to the variation in the manufacturing process can be relieved in the subsequent process, and the burden of the manufacturing cost can be reduced. Furthermore, it is possible to tune to an optimum value in the system that the user wants to use, and the tolerance of the LSI to a plurality of systems can be increased, so that the effect of reducing the system development load can be expected.

Although (Fourth Embodiment) has been described by applying it to the above-mentioned (First Embodiment), (Second Embodiment)
It goes without saying that the resistance element 121 of (and the third embodiment) may be replaced with a variable resistance element, and the resistance value may be set to the initial value read from the nonvolatile memory 505 in the same manner as described above.

In each of the above-mentioned embodiments, the internal impedance adjusting means 120, 220, 420 switch the impedance between the power supplies of the entire internal circuit.
The object can be achieved by arranging at least the impedance between the power supplies of the reception signal demodulation circuit 502.

[0059]

As described above, according to the contact type data carrier of the present invention, the signal components of opposite phases applied to the first and second connection terminals are rectified to supply the electric power of the internal circuit and In the contact-type data carrier for creating an internal processing clock signal to be used in the internal circuit from the opposite phase signal component and demodulating the received signal component multiplexed in the opposite phase signal component, an internal impedance adjusting means is provided,
When the clock signal from the outside changes, the impedance of the internal circuit is switched to high, and when the signal voltage amplitude changes, the impedance of the internal circuit is switched to low, which prevents malfunction of the demodulation circuit due to the influence of skew between input signals and reduces the system design burden. Can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a contact-type data carrier according to (Embodiment 1) of the present invention.

FIG. 2 is an explanatory diagram of the same embodiment.

FIG. 3 is a block diagram of a contact-type data carrier according to (Embodiment 2) of the present invention.

FIG. 4 is a timing chart diagram of a main part of the embodiment.

FIG. 5 is a block diagram of a contact-type data carrier according to (Embodiment 3) of the present invention.

FIG. 6 is a timing chart showing the state transition of the operation of the embodiment.

FIG. 7 is a block diagram of a contact-type data carrier according to (Embodiment 4) of the present invention.

FIG. 8 is a block diagram of a conventional contact type data carrier.

FIG. 9 is a timing chart showing the state transition of the operation of the conventional example.

FIG. 10 is a timing chart showing the state transition of the operation when a timing skew occurs between input signals.

[Explanation of reference numerals] 120, 220, 420 Internal impedance adjusting means 121 Resistance element 201 Switch element 301 Counter 302 Transmission clock 401 Variable resistance element (variable element) 402 Control information register 501 Rectifier circuit 502 Received signal demodulation circuit 503 Clock generation circuit 504 logic circuit 505 non-volatile memory (memory) 506 transmission signal modulation circuit 507 connection terminal (first connection terminal VA) 508 connection terminal (second connection terminal VB) 514 internal processing clock signal

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5B035 AA11 BB09 CA11 CA12 CA22                       CA31                 5K012 AB11 AC11 AD02 AE13 BA02

Claims (4)

[Claims] 1. An internal process for rectifying opposite-phase signal components applied to first and second connection terminals to cover the electric power of an internal circuit and using the opposite-phase signal component in the internal circuit. In a contact-type data carrier for creating a clock signal and demodulating a received signal component multiplexed with the opposite-phase signal component, an internal impedance adjusting means for increasing the impedance of the internal circuit when the opposite-phase signal component changes Is provided
A contact-type data carrier that switches the impedance of the internal circuit to high when the signal component of the opposite phase changes and switches the impedance of the internal circuit to low when demodulating a data signal. 2. An internal process for rectifying signal components of opposite phases applied to the first and second connection terminals to cover the electric power of an internal circuit and using the signal components of the opposite phase in the internal circuit. In a contact-type data carrier that creates a clock signal and demodulates a received signal component that is multiplexed with the opposite-phase signal component, an internal impedance adjusting unit that increases the impedance of the internal circuit according to the polarity of the internal processing clock signal is provided. A contact-type data carrier that is provided to switch the impedance of the internal circuit to high when a clock signal input from the outside changes and to switch the impedance of the internal circuit to low when demodulating a data signal. 3. An internal process for rectifying signal components of opposite phases applied to the first and second connection terminals to cover the electric power of an internal circuit and using the signal components of the opposite phase in the internal circuit. In a contact-type data carrier that creates a clock signal and demodulates a received signal component that is multiplexed with the opposite-phase signal component, based on the result of detecting the phase of the input data signal and the externally input clock signal, And a clock generation circuit that generates the internal processing clock signal and outputs a transmission clock having a higher frequency than the internal processing clock signal based on the clock signal input from the outside, and counts the transmission clock. A counter for detecting a change point of the data signal within the rate of the internal processing clock signal; and the internal circuit based on the count value of the counter. Internal impedance and adjusting means is provided, contact data carrier for switching the impedance of the internal circuit to predict the change point of the data signal by the count value of the counter for switching the impedance. 4. An element for determining a low impedance of said internal impedance adjusting means is a variable element, and an output impedance of this variable element is changed based on initial setting data read from a memory. A contact-type data carrier according to any one of 1.