JP5504903B2 - Reception circuit, reception method, and signal transmission system - Google Patents

Reception circuit, reception method, and signal transmission system Download PDF

Info

Publication number
JP5504903B2
JP5504903B2 JP2010006175A JP2010006175A JP5504903B2 JP 5504903 B2 JP5504903 B2 JP 5504903B2 JP 2010006175 A JP2010006175 A JP 2010006175A JP 2010006175 A JP2010006175 A JP 2010006175A JP 5504903 B2 JP5504903 B2 JP 5504903B2
Authority
JP
Japan
Prior art keywords
voltage
circuit
signal
threshold
connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2010006175A
Other languages
Japanese (ja)
Other versions
JP2011146934A (en
Inventor
隼一 帰山
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP2010006175A priority Critical patent/JP5504903B2/en
Publication of JP2011146934A publication Critical patent/JP2011146934A/en
Application granted granted Critical
Publication of JP5504903B2 publication Critical patent/JP5504903B2/en
Application status is Expired - Fee Related legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12032Schottky diode
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Description

  The present invention relates to a transmission circuit, a reception circuit, a transmission method, a reception method, and a signal transmission system, and more particularly to a transmission circuit, a reception circuit, a transmission method, and a reception method for performing communication via an AC coupling means that transmits a signal by magnetic coupling. And a signal transmission system.

  When a signal is transmitted between a plurality of semiconductor chips having different power supply voltages, if the signal is directly transmitted by wiring, the semiconductor chip may be damaged or a signal transmission failure may occur due to a voltage difference generated in a DC voltage component of the transmitted signal. is there. Therefore, when signals are transmitted between a plurality of semiconductor chips having different power supply voltages, the semiconductor chips are connected by an AC coupling element and only the AC signal is transmitted. Such AC coupling elements include capacitors and transformers (hereinafter referred to as transformers).

  Here, the transformer is an AC coupling element in which the primary side coil and the secondary side coil are magnetically coupled. When a transformer is used as an AC coupling element, the receiving-side semiconductor chip is adjusted regardless of the voltage amplitude of the transmission signal of the transmitting-side semiconductor chip by adjusting the winding ratio between the primary coil and the secondary coil of the transformer. It is possible to transmit a signal having an appropriate voltage amplitude. Therefore, it is not necessary to adjust the voltage amplitude of the transmission signal or the reception signal on the semiconductor chip by performing communication between the semiconductor chips operating with different power supply voltages using a transformer. In the following description, the transformer formed on the semiconductor chip is sometimes referred to as an on-chip transformer.

  Examples of signal transmission technology using a transformer are disclosed in Patent Documents 1 to 11. In Patent Documents 1 to 5, using two on-chip transformers, when the data value transitions from the first value to the second value, a pulse signal is sent to the first transformer, and the data value is the second value. A technique is disclosed in which a pulse signal is transmitted to a second transformer when a transition from a value of 1 to a first value is made. However, this method has a problem that the chip area becomes large because two transformers having a diameter of several hundred μm to 1 mm are used.

  In Patent Documents 1, 2, 4 to 6, a continuous pulse signal is continuously sent to the on-chip transformer during a period in which the data value is the first value, and on-chip in a period in which the data value is the second value. A technique for fixing a signal to a transformer is disclosed. However, in this method, since the signal must be continuously transmitted while the logical value of the signal transmitted through the transformer is at a certain level, there is a problem that power consumption increases.

  In Patent Documents 1, 2, 4, and 5, during the period in which the data value is the first value, the continuous pulse signal having the first frequency is continuously sent to the on-chip transformer, and the data value is the second value. A technique is disclosed in which a continuous pulse signal of the second frequency is continuously sent to the on-chip transformer during the period of (1). However, this method also has a problem of increasing power consumption because the signal must be transmitted while the logical value of the signal transmitted through the transformer is at a certain level. Furthermore, in this system, there is a problem that a circuit used for determining the frequency becomes complicated or a circuit area of a filter circuit or the like becomes large.

  In Patent Document 7, when the data value transitions from the first value to the second value, a signal consisting of one pulse is sent to the on-chip transformer, and the data value changes from the second value to the first value. A technique for transmitting a signal composed of two continuous pulses to an on-chip transformer upon transition is disclosed. However, this method has a problem that the signal delay increases. In addition, in this method, there is a problem that the determination circuit for determining the number of pulses in the reception circuit becomes complicated.

  Patent Documents 8 and 9 disclose a receiving circuit mounted on a semiconductor device that transmits a signal via an AC coupling element. In the receiving circuit, a positive pulse and a negative pulse generated in the secondary coil on the receiving circuit side are captured by the receiving clock. However, in the techniques described in Patent Documents 8 and 9, there is a problem that it is necessary to synchronize the transmission timing of the transmission circuit and the reception timing of the reception circuit, and cannot cope with asynchronous communication. In addition, it is necessary to always generate a reception clock in the reception circuit, which causes a problem of increasing power consumption.

  The technologies described in Patent Documents 1 to 9 have a problem that the chip area increases or the power consumption increases. Therefore, in order to suppress the chip area and power consumption, Patent Documents 10 and 11 disclose techniques for reproducing a transmission signal transmitted from a voltage fluctuation generated in the secondary coil.

  Patent Document 10 discloses a transmission circuit that generates a positive current pulse and a negative current pulse at each of a rising edge and a falling edge of a transmission signal, and a secondary coil by using a positive current pulse and a negative current pulse. A pulse outn corresponding to the positive current pulse and a pulse outp corresponding to the negative current pulse are generated from the induced electromotive force and the reverse induced electromotive force generated in step, and the transmission signal rises and falls according to the order of the pulses outn and outp. And a receiving circuit that reproduces a transmission signal.

  According to Patent Document 11, the current flowing through the coil is sharply increased or decreased corresponding to the rising edge and falling edge of the transmission signal, and the signal level following the edge is constant. A technique for exponentially returning zero to zero is disclosed. As a result, in Patent Document 11, the voltage generated in the secondary coil is made asymmetric in the vertical direction, the voltage generated in the secondary coil is detected by the hysteresis comparator of the receiving circuit, and the transmission signal is reproduced from the detection result.

US Pat. No. 6,262,600 US Pat. No. 6,525,566 US Pat. No. 6,873,065 US Pat. No. 6,903,578 US Pat. No. 6,922,080 US Pat. No. 7,302,247 US Pat. No. 7,075,329 JP 2005-228981 A JP 2009-188468 A JP 2007-36497 A JP-A-8-236696

  However, in the technique described in Patent Document 10, when a transmission signal is modulated and transmitted with a short pulse having a short pulse width, the interval of voltage fluctuations generated in the secondary coil is narrowed, and an error in the received signal occurs in the receiving circuit. There is a problem that judgment occurs. Further, in the technique described in Patent Document 11, when a transmission signal is modulated by a short pulse, the interval between the rising edge and the falling edge of the short pulse is shorter than the period until the drive current of the primary coil returns to zero. In such a case, there is a problem that erroneous determination of the received signal occurs in the receiving circuit.

  The present invention has been made to solve such a problem. Even when a transmission signal is modulated with a short pulse with a short pulse width and transmitted, a transmission circuit and a reception circuit that prevent erroneous reception of the received signal are provided. It is an object to provide a circuit, a transmission method, a reception method, and a signal transmission system.

  A transmission circuit according to the present invention includes a pre-driver circuit that outputs a drive control signal to the drive circuit in response to a rising edge or a falling edge of a transmission signal generated based on transmission data, and a second circuit provided on the reception circuit side. A drive circuit that drives a primary side coil magnetically coupled to a secondary side coil by a positive drive current or a negative drive current in which an increase rate and a decrease rate become asymmetric according to the drive control signal It is.

  The receiving circuit according to the present invention includes a secondary side coil that is magnetically coupled to a primary side coil that is driven by a positive drive current or a negative drive current in which an increase rate and a decrease rate are asymmetric. A reception circuit for receiving a reception signal generated by a transmission signal flowing through a coil, connected to one terminal of the secondary coil, and according to a difference in absolute value between a positive amplitude and a negative amplitude of the reception signal A received signal detection circuit that outputs the detected voltage, and a hysteresis comparator that regenerates the transmission data that generated the received signal based on the voltage difference between the detected voltage and the comparison voltage.

  The transmission method according to the present invention provides a transmission signal generated based on transmission data by supplying a drive current to a primary side coil that is magnetically coupled to a secondary side coil provided on the reception circuit side. A transmission method for transmitting to a circuit, wherein a drive control signal is output according to a rising edge or a falling edge of the transmission signal, and a rise time change amount and a fall time change amount differ according to the drive control signal. The drive current is output.

  In the receiving method according to the present invention, a primary side coil magnetically coupled to a primary side coil driven by a positive drive current or a negative drive current in which an increase rate and a decrease rate are asymmetric is connected to the primary side. A reception method for receiving a reception signal generated by a transmission signal flowing in a coil, and detecting from one terminal of the secondary coil according to a difference in absolute value between a positive amplitude and a negative amplitude of the reception signal A voltage is output, and the transmission data in which the reception signal is generated is reproduced based on the voltage difference between the detection voltage and the comparison voltage.

  A signal transmission system according to the present invention includes a primary coil provided on a transmission circuit side, a secondary coil magnetically coupled to the primary coil, and a rising edge of a transmission signal generated based on transmission data Alternatively, a pre-driver circuit that outputs a drive control signal to the drive circuit in response to a falling edge, and a positive drive current or negative that causes an increase rate and a decrease rate to be asymmetric in the primary side coil in response to the drive control signal. A drive circuit that supplies a drive current of the second side coil, and a difference between absolute values of a positive amplitude and a negative amplitude of a reception signal that is connected to one terminal of the secondary side coil and is generated in the secondary side coil by the transmission signal A reception signal detection circuit that outputs a detection voltage corresponding to the detection voltage, and a hysteresis comparator that reproduces transmission data that generates the reception signal based on a voltage difference between the detection voltage and the comparison voltage. And over motor, and has a.

  According to the present invention, it is possible to provide a signal transmission system that can prevent an error in logic determination caused by an operating environment.

1 is a diagram illustrating a configuration example of a signal transmission system according to a first exemplary embodiment; It is a figure which shows the example of mounting of the signal transmission system concerning Embodiment 1. FIG. 1 is a diagram illustrating a configuration example of a signal transmission system according to a first exemplary embodiment; FIG. 3 is a diagram illustrating operating characteristics of the hysteresis comparator according to the first embodiment. 1 is a circuit diagram of a drive circuit according to a first exemplary embodiment; 3 is a timing chart illustrating an operation of the transmission circuit according to the first exemplary embodiment; 3 is a timing chart illustrating an operation of the transmission circuit according to the first exemplary embodiment; 3 is a timing chart illustrating an operation of the transmission circuit according to the first exemplary embodiment; FIG. 3 is a circuit diagram of a transmission circuit according to the first exemplary embodiment; 3 is a timing chart illustrating an operation of the transmission circuit according to the first exemplary embodiment; 3 is a timing chart illustrating an operation of the transmission circuit according to the first exemplary embodiment; FIG. 3 is a circuit diagram of a transmission circuit according to the first exemplary embodiment; It is a timing chart which shows operation | movement of a related transmission circuit. 3 is a configuration example of a receiving circuit according to the first exemplary embodiment; FIG. 3 is a diagram illustrating output characteristics of the threshold circuit according to the first exemplary embodiment. It is a figure which shows the structural example of a threshold value element. FIG. 3 is a circuit diagram of a receiving circuit according to the first exemplary embodiment; 3 is a timing chart illustrating an operation of the receiving circuit according to the first exemplary embodiment; FIG. 3 is a circuit diagram of a receiving circuit according to the first exemplary embodiment; 3 is a configuration example of a transmission circuit according to a second embodiment; 3 is a configuration example of a transmission circuit according to a second embodiment; 10 is a configuration example of a transmission circuit according to a third embodiment; 10 is a configuration example of a transmission circuit according to a third embodiment; 10 is a timing chart illustrating an operation of the transmission circuit according to the third exemplary embodiment; 10 is a configuration example of a transmission circuit according to a third embodiment; 10 is a timing chart illustrating an operation of the transmission circuit according to the third exemplary embodiment; 10 is a configuration example of a receiving circuit according to a fourth embodiment; 10 is a configuration example of a receiving circuit according to a fourth embodiment; 10 is a configuration example of a receiving circuit according to a fourth embodiment; 10 is a configuration example of a receiving circuit according to a fourth embodiment; 10 is a configuration example of a receiving circuit according to a fifth embodiment; 10 is a configuration example of a receiving circuit according to a sixth embodiment; 10 is a timing chart illustrating an operation of a received signal detection circuit according to a sixth exemplary embodiment; 6 is a timing chart illustrating an operation of the reception signal detection circuit according to the first to fifth embodiments. 6 is a timing chart illustrating an operation of the reception signal detection circuit according to the first to fifth embodiments. FIG. 10 is a circuit diagram of a receiving circuit according to a sixth embodiment; FIG. 10 is a circuit diagram of a receiving circuit according to a sixth embodiment; 2 is a configuration example of a transmission circuit and a reception circuit according to the present invention. It is an example of implementation of the signal transmission system concerning the present invention. It is an example of implementation of the signal transmission system concerning the present invention. It is an example of implementation of the signal transmission system concerning the present invention. It is an example of implementation of the signal transmission system concerning the present invention. It is an example of implementation of the signal transmission system concerning the present invention. It is an example of implementation of the signal transmission system concerning the present invention. It is an example of implementation of the signal transmission system concerning the present invention. It is an example of implementation of the signal transmission system concerning the present invention. It is an example of implementation of the signal transmission system concerning the present invention. It is an example of implementation of the signal transmission system concerning the present invention.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of the overall configuration of a signal transmission system 1 according to the present invention. The signal transmission system 1 shown in FIG. 1 includes a transmission circuit 2, a reception circuit 3, and a transformer 10. The transformer 10 is composed of a primary side coil 11 and a secondary side coil 12 and is an AC coupling element that transmits an AC signal from the primary side coil 11 to the secondary side coil. The transformers 10 are magnetically coupled to each other.

  FIG. 2 shows an implementation example of the signal transmission system 1. In the mounting state shown in FIG. 2, the first semiconductor chip 93 and the second semiconductor chip 94 are mounted on the semiconductor package 91. The first semiconductor chip 93 and the second semiconductor chip 94 each have a pad Pd. The pads Pd of the first semiconductor chip 93 and the second semiconductor chip 94 are connected to lead terminals 92 provided on the semiconductor package 91 via bonding wires (not shown).

  The transmission circuit 2 is formed on the first semiconductor chip 93. Further, the primary side coil 11 and the secondary side coil 12 are formed in the first semiconductor chip 93. On the other hand, the receiving circuit 3 is formed in the second semiconductor chip 94. A pad connected to the receiving circuit 3 is formed on the second semiconductor chip 94, and a pad connected to the secondary coil 12 is formed on the first semiconductor chip 93. The receiving circuit 3 is connected to the secondary coil 12 formed on the first semiconductor chip 93 via a pad and a bonding wire.

  In the signal transmission system 1, the transmission circuit 2 converts transmission data input from the pad Pd into a drive signal and outputs the drive signal to the primary coil as a transmission signal. The signal transmission system 1 converts the transmission signal (i (t)) into a magnetic signal using the primary coil 11 of the transformer 10, and converts the magnetic signal into a reception signal (VR) using the secondary coil 12. To do. Then, the receiving circuit 3 reproduces transmission data based on the received signal. This enables signal transmission between the first semiconductor chip 93 and the second semiconductor chip 94 that are electrically insulated.

  Next, details of a configuration example of the signal transmission system 1 will be described. The circuit shown in FIG. 3 is a detailed block diagram of the signal transmission system 1 according to the first exemplary embodiment. The transmission circuit 2 includes a drive circuit 21 and a pre-driver circuit 22. The drive circuit 21 is a positive drive current that causes the increase rate and decrease rate of the primary side coil 11 that is magnetically coupled to the secondary side coil 12 provided on the receiving circuit 3 side to be asymmetric with respect to the drive control signal. Or it drives with a negative drive current. The positive drive current and the negative drive current are supplied to the primary coil 11 as the drive current i (t). The pre-driver circuit 22 outputs a drive control signal to the drive circuit in accordance with the rising edge or falling edge of the transmission signal generated based on the transmission data TxIN.

  The reception circuit 3 includes a reception signal detection circuit 31 and a hysteresis comparator 32. The reception signal detection circuit 31 has an input terminal connected to the secondary coil 12. The reception signal detection circuit 31 is connected to one terminal of the secondary coil 12 and outputs a detection voltage corresponding to the difference in absolute value between the positive amplitude and the negative amplitude of the reception signal.

  The hysteresis comparator 32 is connected to the output terminal of the reception signal detection circuit 31, reproduces the transmission data TxIN that generates the reception signal based on the voltage difference between the detection voltage and the comparison voltage, and outputs it as output data RxOUT. Specifically, as shown in FIG. 4, the hysteresis comparator 32 receives the potential difference VR2 between the detection voltage and the comparison voltage as the input voltage Vin, and the logic of the output voltage Vout when the input voltage Vin becomes equal to or greater than a predetermined potential difference Vth1. Set the level to high level. On the other hand, the hysteresis comparator 32 sets the logic level of the output voltage Vout to a low level when the input voltage Vin becomes equal to or lower than a predetermined potential difference Vth2. These logic levels are output as output data RxOUT.

  Next, a specific configuration and operation of the transmission circuit 2 will be described. FIG. 5 is a diagram illustrating a specific circuit configuration example of the drive circuit 21. As shown in FIG. 5, the drive circuit 21 includes p-channel MOS transistors MP1 and MP2 and n-channel MOS transistors MN1 and MN2. The source of the p-channel MOS transistor MP1 is connected to the first reference voltage (for example, the power supply Vref), and the drain is connected to the drain of the n-channel MOS transistor MN1. A node to which the drain of the p-channel MOS transistor MP1 and the drain of the n-channel transistor MN1 are connected is connected to the first terminal of the primary side coil. The source of the n-channel MOS transistor MN1 is connected to a second reference voltage (for example, ground). A control signal VGP1 is supplied to the gate of the p-channel MOS transistor MP1. A control signal VGN1 is applied to the gate of the n-channel MOS transistor MN1.

  The source of the p-channel MOS transistor MP2 is connected to the first reference voltage (for example, the power supply Vref), and the drain is connected to the drain of the n-channel MOS transistor MN2. A node to which the drain of the p-channel MOS transistor MP2 and the drain of the n-channel transistor MN2 are connected is connected to the second terminal of the primary coil. The source of the n-channel MOS transistor MN2 is connected to a second reference voltage (for example, ground). The control signal VGP2 is applied to the gate of the p-channel MOS transistor MP2. A control signal VGN2 is applied to the gate of the n-channel MOS transistor MN2.

  In the example shown in FIG. 5, the configuration is shown in which only the pre-driver circuit 22 that outputs the control signal VGN2 is connected. However, the pre-driver circuit 22 is connected to the gate of each transistor or transmission is performed. An amplifier that converts the data TxIN into a voltage signal is connected (not shown). That is, the transmission data TxIN is input to the gates of the respective transistors via the pre-driver circuit 22 or the amplifier. The control signals VGP1, VGP2, and VGN1 are generated by a circuit (not shown) based on the transmission data TxIN.

  The drive circuit 21 gives a positive drive current and a negative drive current to the primary side coil. The positive drive current refers to a current that flows from the first terminal of the primary coil toward the second terminal, and the negative drive current refers to the first current from the second terminal of the primary coil. The current that flows toward the terminal.

  Here, an example of the operation of the drive circuit 21 shown in FIG. 5 will be described using waveforms inside the transmission circuit 2 shown in FIG. The pre-driver circuit 22 applies voltages VGN1 and VGN2 having a steep rise and a gentle fall to the gates of the n-channel MOS transistors MN1 and MN2 of the transmission circuit 2. At this time, the p-channel MOS transistor (MP2 for MN1 and MP1 for MN2) diagonally positioned with respect to the n-channel MOS transistor to be turned on is turned on in advance. That is, in order to turn on the p-channel MOS transistor, transmission data TxIN through the amplifier, that is, gate voltages VGP1 and VGP2 are applied to the gate.

  Here, the gate voltage applied to the n-channel MOS transistor and the current flowing between the source and the drain are approximately proportional. Therefore, as shown in FIG. 6, the drive current i flowing in the primary side coil 11 rises sharply by the voltages VGN1 and VGN2 having the steep rise and the gentle fall inputted to the gates of the n-channel MOS transistors MN1 and MN2. It will have a gradual fall.

  Note that the n-channel MOS transistor may be turned on in advance, and a voltage waveform having a steep rise and fall may be applied to the gate terminal of the p-channel MOS transistor.

  Further, in order to reverse the direction of the current flowing through the primary side coil 11, the p-channel MOS transistor MP1 and the n-channel MOS transistor MN2 shown in FIG. 5 are turned on, or the p-channel MOS transistor MP2 and the n-channel MOS transistor MN1 are turned on. It may be selected by controlling each gate voltage.

  On the other hand, as shown in FIG. 7, even when the n-channel MOS transistor is turned on in advance and the gate voltage of the p-channel MOS transistor is steeply set to a low level, the drive current i of the primary side coil is sharply raised. Good. As a result, the drive current i rises sharply. On the other hand, when the drive current i is gradually lowered, the drive current i of the primary coil 11 is gently lowered by gently lowering the gate voltage of the n-channel MOS transistor which has been turned on in advance. .

  In this way, by controlling the gate voltage of each transistor included in the drive circuit 21, the current flowing in the primary coil 11 has a waveform having a steep rise and a gradual fall, or a steep fall and a gradual rise. It becomes.

  Next, an operation example of the pre-driver circuit 22 will be described. The pre-driver circuit 22 outputs a drive control signal that controls the gate voltage of the transistor of the drive circuit 21 as described above. Specifically, a current is supplied to a gate to be controlled or a current is drawn.

  At this time, as shown in Expression (1), the voltage VR appearing in the secondary coil 12 is proportional to the time derivative of the current flowing through the primary coil 11. The current flowing through the primary coil 11 is approximately proportional to the gate voltage of the transistors (MP1, MP2, NM1, MN2) of the drive circuit 21. Furthermore, the gate voltage of the transistor of the drive circuit 21 is proportional to the integral of the current flowing through the gate. Therefore, the voltage appearing at the secondary coil 12 is approximately proportional to the gate voltage of the transistor of the drive circuit 21 that limits the current flowing through the primary coil 11. Note that gm is the transconductance of the MOS transistor.

  In other words, the waveform of the voltage VR appearing in the secondary coil 12 can be controlled by controlling the current flowing through the gate of the transistor of the drive circuit 21 by the pre-driver circuit 22. FIG. 8 shows waveforms of the current IGN2 output from the pre-driver circuit 22 to the n-channel MOS transistor MN2, the gate voltage VGN2 of the n-channel MOS transistor MN2, and the voltage VR appearing in the secondary coil 12.

  The operation in the waveform shown in FIG. 8 will be described. First, in the circuit shown in FIG. 5, the p-channel MOS transistor MP1 of the drive circuit 21 is turned on in advance. Next, the pre-driver circuit 22 supplies a large current iGN2 so that the gate voltage VGN2 of the n-channel MOS transistor MN2 rises sharply. Then, a large drive current i flows from the drive circuit 21 to the primary coil 11 due to the steeply rising gate voltage VGN2, so that a voltage VR having a large amplitude is generated in the secondary coil 12.

  Thereafter, the pre-driver circuit 22 draws a small current iGN2 from the gate so that the gate voltage VGN2 gradually falls. As a result, the gate voltage VGN2 falls gently, and a voltage VR having a small negative amplitude is generated in the secondary coil 12.

  Thus, by providing the pre-driver circuit 22 that controls the gate current of the transistor of the drive circuit 21, the amplitude of the voltage VR appearing in the secondary coil 12, that is, the time change rate of the voltage VR is controlled. Note that the n-channel MOS transistor MN1 may be turned on in advance and the gate current of the p-channel MOS transistor MP2 may be controlled by the pre-driver circuit 22, or both gates of the p-channel MOS transistor and the n-channel MOS transistor may be controlled. The pre-driver circuit 22 is connected, and the gate of the n-channel MOS transistor may be rapidly charged with a large current, and then the gate of the p-channel MOS transistor may be gradually turned off with a small current.

  FIG. 9 is a diagram illustrating a specific circuit configuration example of the pre-driver circuit 22. The pre-driver circuit 22 includes a p-channel MOS transistor MP3, an n-channel MOS transistor MN3, and a pulse generator 221. The source terminal of the p-channel MOS transistor MP3 is connected to the third reference voltage source, and the source terminal of the n-channel MOS transistor MN3 is connected to the fourth reference voltage source (for example, ground). The drain terminal of the p-channel MOS transistor MP3 and the drain terminal of the n-channel MOS transistor MN3 are connected to the output terminal of the pre-driver circuit 22. In the circuit of FIG. 9, the output terminal of the pre-driver circuit 22 is connected to the gate of the n-channel MOS transistor MN1.

  Transmission data TxIN is input to the pulse generator 221. The pulse generator 221 outputs pulses corresponding to the logic level of the transmission data TxIN to the gates of the p-channel MOS transistor MP3 and the n-channel MOS transistor MN3, and alternately turns on these transistors. Here, as shown in FIG. 10, when the gate voltage of the n-channel MOS transistor MN1 is charged, a large current iGN1 is supplied, and when discharging, the small current iGN1 is gradually extracted, the pre-driver circuit 22 is supplied. The on-resistance RONP of the p-channel MOS transistor MP3 is reduced, and the on-resistance RONN of the n-channel MOS transistor MN3 is increased. Thereby, the current supplied to the gate of the n-channel MOS transistor MN1 and the magnitude of the extracted current can be changed.

  For example, when RONP: RONN = 1: 2, the ratio of the current iGN1 flowing through the gate of the n-channel MOS transistor MN1 is rising current: falling current = 2: 1. Similarly, a pulse having positive and negative amplitudes proportional to the current iGN1 flowing through the gate also appears in the electromotive force (VR) of the secondary coil 12.

  Thus, by setting the ratio of the on-resistance of the p-channel MOS transistor MN3 and the n-channel MOS transistor MN3 of the pre-driver circuit 22 in advance, the positive and negative directions of the waveform of the voltage VR appearing in the secondary coil 12 and Amplitude can be set. Therefore, in the receiving circuit 3, if the waveform of the voltage VR generated in the secondary coil 12 determines which of the positive and negative amplitudes exceeds the threshold value or which of the positive and negative amplitudes is larger, the transmitting circuit 2 transmits the signal. The logic level of the processed signal can be determined.

  As shown in FIG. 11, when a waveform having a large positive amplitude is generated in the secondary coil 12, the circuit configuration shown in FIG. 12 may be used. That is, the pre-driver circuit 22 may be connected to the gate of the p-channel MOS transistor MP1. At this time, if RONP: RONN = 2: 1, the ratio of the current iGP1 flowing to the gate of the p-channel MOS transistor MP1 is rising current: falling current = 1: 2.

  The above is the description of the configuration and operation of the transmission circuit 2. Normally, in the method of changing the direction in which the current i flows through the primary coil 11 in accordance with the logic level of the transmission data TxIN, the waveform of the voltage VR swings between the positive and negative poles in a short time as shown in FIG. For this reason, it is difficult to determine the signal component sig and the noise component noise, and it is difficult to determine the logical value in the receiving circuit 3.

  However, the transmission circuit 2 according to the present invention can control the time change rate of the rise and fall of the current supplied to the primary coil 11 by the pre-driver circuit 22 controlling the drive circuit 21. As a result, as described with reference to FIG. 8, not only can a difference be provided between the positive and negative amplitudes of the waveform of the voltage VR generated in the secondary coil, but also the speed of waveform change can be adjusted. Therefore, since the voltage VR generated in the secondary coil 12 does not become a signal that swings between the positive and negative poles in a short time, erroneous determination of the logical value can be prevented.

  Hereinafter, the configuration and operation of the receiving circuit 3 will be described. FIG. 14 is a diagram illustrating a specific circuit configuration example of the reception circuit 3. The reception signal detection circuit 31 includes a threshold circuit 311, a capacitor element 312, and a resistance element 313. The threshold circuit 311 has an input terminal connected to the secondary coil 12, an output terminal connected to the hysteresis comparator 32, and a current im flows when the voltage Vm between the input terminal and the output terminal exceeds a certain value. A bias voltage VBIAS as a comparison voltage is applied to the output terminal of the threshold circuit 311 and is connected to a voltage source (not shown) of the voltage VBIAS via a capacitive element.

  FIG. 15 shows a graph representing the operation of the threshold circuit 311. As described above, when the voltage Vm across the threshold circuit 311 is greater than the threshold voltage Vth3, a current im having a magnitude proportional to the voltage Vm flows. Also, when the voltage Vm at both ends becomes smaller than the threshold voltage Vth4, a current im having a magnitude proportional to the magnitude of the voltage Vm flows. On the other hand, when the voltage Vm at both ends is not less than the threshold voltage Vth4 and not more than Vth3, no current flows in the threshold circuit 311.

  Here, a specific configuration example of the threshold circuit 311 will be described with reference to FIG. As shown in FIG. 16, a diode using a PN junction or a Schottky junction may be used as a threshold element included in the threshold circuit 311, or the gate of an n-channel MOS transistor or a p-channel MOS transistor is short-circuited to the source or drain. A configuration may be used. At this time, either the drain or the source of the transistor is connected to the input terminal of the threshold element, and the other of the drain and the source of the transistor is connected to the output terminal of the threshold element.

  When a PN junction diode of a general CMOS process is used, a stable threshold value can be obtained at about 0.7 V regardless of the power supply voltage or the like. When a transistor is used, the threshold value is about 0.2V to 1V depending on the generation of the CMOS process and the minimum processing size. However, even if fluctuation conditions such as process, power supply voltage, and temperature are taken into consideration, the fluctuation of the threshold is often suppressed to about ± 0.1V. These threshold fluctuations are generally smaller than hysteresis circuit threshold fluctuations. Therefore, by using these, it is possible to configure the receiving circuit 3 with a stable threshold.

  FIG. 17 shows a specific configuration example of the threshold circuit 311 having the above-described diode as a threshold element. The threshold circuit 311 illustrated in FIG. 17 includes diodes 3111 and 3112 which are two threshold elements through which a current flows when a certain voltage difference occurs between an input terminal and an output terminal. The anode of the diode 3111 and the cathode of the diode 3112 are connected to the secondary coil 12. The cathode of the diode 3111 and the anode of the diode 3112 are connected to the hysteresis comparator 32. The threshold element is not limited to a diode, and a configuration in which the gate terminal of an n-channel MOS transistor or a p-channel MOS transistor is short-circuited to a source terminal or a drain terminal as described above may be used.

  A waveform showing the operation of the reception signal detection circuit 31 is shown in FIG. As described in the transmission circuit 2, the secondary coil 12 has a magnetic signal generated by the positive drive current i (t) in which the increasing rate and the decreasing rate flowing in the primary coil 11 become asymmetrical. As shown, a waveform of a voltage VR having different magnitudes of positive amplitude and negative amplitude is generated.

  When the generated voltage VR exceeds the threshold voltage Vth3 or falls below the threshold voltage Vth4, the current im flows, so that the capacitor element 312 provided between the threshold circuit 311 and the hysteresis comparator 32 is charged or charged. Discharged. As a result, the voltage input to the hysteresis comparator 32 changes from VR to the voltage VR2. When the voltage VR2 increases, the hysteresis comparator 32 regards it as a high level and sends out high level output data RxOUT. On the other hand, when the voltage VR2 decreases, the hysteresis comparator 32 regards it as a low level and sends out low-level output data RxOUT. After that, if the capacitor 312 is not charged or discharged for a certain period of time, the input voltage VR2 to the hysteresis comparator 32 converges to the constant voltage VBIAS via the resistance element 313.

  As shown in FIG. 18, the voltage VR generated in the secondary coil 12 is a signal in which the amplitude of the signal component sig is larger than the amplitude of the noise component noise. Therefore, it becomes easy to make a determination using a pulse having a large amplitude as a signal component. However, in the hysteresis comparator 32, the threshold values Vth1 and Vth2 shown in FIG. 4 are likely to change due to environmental changes such as process, power supply voltage, and temperature. Therefore, if the voltage VR is directly input to the hysteresis comparator 32, the signal of the noise component noise shown in FIG. 18 may be erroneously determined as the signal component sig.

  However, as described above, the reception circuit 3 according to the present invention converts the voltage VR generated in the secondary coil 12 into the voltage VR2 by the reception signal detection circuit 31. That is, as shown in FIG. 18, the reception signal detection circuit 31 generates a voltage VR2 that is a signal obtained by removing the noise component noise from the voltage VR generated in the secondary coil 12. As a result, it is possible to suppress erroneous determination even when the threshold value of the hysteresis comparator 32 slightly varies. In the receiving circuit 3 according to the present embodiment, the voltage VR2 can be generated according to the difference between the absolute values of the components exceeding the threshold value of the threshold circuit 311 between the positive amplitude and the negative amplitude of the received signal. That is, in the receiving circuit 3, even when the threshold value of the threshold circuit 3 fluctuates, an erroneous determination is made based on the difference between the absolute values of the components exceeding the threshold value of the threshold circuit 311 between the positive amplitude and the negative amplitude of the received signal. Can be prevented.

  Note that the receiving circuit 3 shown in FIG. 17 may be configured as shown in FIG. An input terminal of the threshold circuit 311 is connected to one end of the secondary coil 12 via the input side capacitive element 35. Also in the receiving circuit 3 shown in FIG. 19, both terminals of the threshold circuit 311 are biased by the voltage VBIAS. Accordingly, the operation is the same as that of the reception circuit 3 in FIG. 17, and the waveform shown in FIG. Further, since the other end of the secondary coil L2 is connected to the ground and is insulated from the threshold circuit 311 by the input side capacitive element 35, the secondary coil 12 operates using the ground potential as a bias voltage.

Embodiment 2
The signal transmission system 4 according to the present embodiment will be described. In the signal transmission system 4 shown in FIG. 20, the drive circuit 21 of the transmission circuit 2 includes a current source 211. The current source 211 is inserted between the sources of the n-channel MOS transistors MN1 and MN2 and the ground. As the current source 211, for example, as shown in FIG. 20, a transistor having a gate terminal biased at a constant voltage is used. Since other configurations are the same as those of the signal transmission system 1, description thereof is omitted.

  In general, the current flowing through a transistor fluctuates due to the influence of process fluctuation, power supply voltage fluctuation, temperature fluctuation, and the like. Therefore, the power consumption of the transmission circuit varies due to variations in these factors, and the amplitude of the received signal that appears in the secondary coil 12 varies. On the other hand, the current source 211 is provided between the drive circuit 21 according to the present embodiment and the ground. The current source 211 sets a current value flowing through the p-channel MOS transistors MP1 and MP2 and the n-channel MOS transistors MN1 and MN2. Therefore, in the drive circuit 21 according to the present embodiment, the magnitude of the drive current i (t) flowing through the primary side coil 11 can be set regardless of the influence of process fluctuation, power supply voltage fluctuation, temperature fluctuation, and the like. As a result, it is possible to improve the controllability of the consumption current of the transmission circuit 2 and the magnitude of the waveform of the reception signal appearing in the secondary coil 12, that is, the amplitude of the voltage VR. Further, by providing the current source 211, it is possible to prevent an excessive current from flowing through the primary side coil, and it is possible to reduce current consumption and improve the reliability of the device. As shown in FIG. 21, a current source 211 may be inserted between the p-channel MOS transistor and the power source.

Embodiment 3
The signal transmission system 5 according to the present embodiment will be described. In the signal transmission system 5 illustrated in FIG. 22, the pre-driver circuit 22 of the transmission circuit 2 includes a current source 222. As in the second embodiment, the current source 222 is configured using, for example, a transistor whose gate terminal is biased with a constant voltage Vref. Since other configurations are the same as those of the signal transmission system 1, description thereof is omitted.

  In the pre-driver circuit 22 in FIG. 22, a current source 222 is provided between the n-channel MOS transistor MN3 and the ground. Therefore, when the gate voltage VGN1 is lowered, the gate voltage VGN1 is discharged by the current iGN1 limited by the current source 222. On the other hand, since no current source is provided between the p-channel MOS transistor MP3 and the power supply, the current iGN1 supplied to raise the gate voltage VGN1 is not limited. As a result, the magnitude of the charge current and discharge current of the gate of the n-channel MOS transistor MN1 can be controlled.

  That is, similarly to the waveform shown in FIG. 8, the time change rate of the rising current and the falling current of the current i flowing through the primary coil 11 can be controlled, and the waveform of the voltage VR generated in the secondary coil 12 is positive or negative. Waveforms with different amplitudes.

  Thus, according to the configuration of the signal transmission system 5 according to the present embodiment, the positive and negative amplitudes of the reception signals generated in the secondary coil 12 have different sizes. As a result, if the receiving circuit 3 determines which of the positive and negative amplitudes of the received signal exceeds the threshold value or which amplitude is larger, the logical level of the transmission data TxIN can be determined without erroneous determination. it can.

  Here, FIG. 23 shows a configuration example of the transmission circuit 2 in which both the drive circuit 21 and the pre-driver circuit 22 are provided with current sources. An example of the operation will be described with reference to the timing chart of FIG. In the transmission circuit 2 shown in FIG. 23, the pre-driver circuit 22 is connected to the gates of the n-channel MOS transistors MN1 and MN2 of the drive circuit 21. On the other hand, amplifiers 23 and 24 are connected to the gates of the p-channel MOS transistors MP1 and MP2, respectively. The source terminal of the drive circuit 21 is grounded via the current source 211. This suppresses changes in current consumption due to changes in the process, power supply voltage, temperature, etc., and changes in the received signal appearing on the secondary coil 12.

  Subsequently, an operation example will be described with reference to FIG. When the transmission data TxIN is switched from the low level to the high level, the amplifier 23 outputs a signal obtained by inverting the logic level of the transmission data TxIN to the gate of the p-channel MOS transistor MP1 of the drive circuit 21. Therefore, the p-channel MOS transistor MP1 is turned on. Further, the pulse generator 2212 of the pre-driver circuit 22 outputs a short pulse (VPREN2) for switching the logic level of the transmission data TxIN, and the pre-driver circuit 22 supplies a current to the gate of the n-channel MOS transistor MN2 as a drive control signal. Shed. Then, the gate voltage VGN2 is generated in the n-channel MOS transistor MN2, and is turned on for a short time. As a result, the drive circuit 21 causes a short pulse current i to flow through the primary coil 11.

  At this time, the voltage VR between the terminals of the secondary coil 12 greatly fluctuates in the positive direction only for a short time. In the process of lowering the gate voltage VGN2 of the n-channel MOS transistor MN2, the current magnitude is limited by the current source 222 of the pre-driver circuit 22. Therefore, the current is slowly extracted from the gate of the n-channel MOS transistor MN2 by the pre-driver circuit 22, and the current i flowing through the primary side coil 11 gradually decreases. Therefore, the voltage VR between the terminals of the secondary coil 12 fluctuates for a relatively long time with a small amplitude in the negative direction.

  On the other hand, when the transmission data TxIN is switched from the high level to the low level, the amplifier 24 outputs a signal having the same logical level as that of the transmission data TxIN. Therefore, the p-channel MOS transistor MP2 of the drive circuit 21 is turned on. Further, the pulse generator 2211 outputs a short pulse when the logic level of the transmission data TxIN is switched (VPREN1). In response to this, the pre-driver circuit 22 outputs to the drive circuit 21 a drive control signal that turns on the n-channel MOS transistor MN1 for a short time. The rise and fall of the gate voltage of the n-channel MOS transistor MN1 are controlled in the same manner as in the case of the n-channel MOS transistor MN2. Therefore, a negative voltage with a large amplitude appears in the secondary coil 12 in a short time and a positive voltage with a small amplitude appears in a relatively long time. As a result, the receiving circuit 3 determines the logic level transmitted by the transmitting circuit depending on whether the voltage VR of the secondary coil 12 exceeds a predetermined threshold value or by comparing the magnitudes of the positive and negative amplitudes. can do.

  The transmission circuit 2 shown in FIG. 22 has a configuration in which the pre-driver circuit 22 is connected to the gate of the n-channel MOS transistor. In FIG. 25, the pre-driver circuit 22 is connected to the gate of the p-channel MOS transistor. An example of the configuration of the transmission circuit 2 is shown.

  FIG. 26 shows a timing chart showing the operation of the signal transmission system 5 shown in FIG. In FIG. 25, a pre-driver circuit 22 is connected to a p-channel MOS transistor. Therefore, the logic level of the pulse signal output from the pulse generators 2211 and 2122 when the logic level of the transmission data TxIN is switched is opposite to that in the timing chart of FIG. Thereby, when the logic level of the transmission data TxIN is switched, the gate voltages VGP1 and VGP2 of the p-channel MOS transistor are steeply lowered. As a result, a positive or negative drive current i flows steeply through the primary coil 11. Thereafter, a current limited by a current source 222 provided between the source of the p-channel MOS transistor of the pre-driver circuit 22 and the power supply is supplied to the gate of the p-channel MOS transistor as a drive control signal. As a result, the amplitude of the drive current i gradually decreases. Therefore, a reception signal having a waveform similar to that of the voltage VR in FIG. 24 is generated in the secondary coil 12.

  Note that the configurations and connection relationships of the pre-driver circuit 22 and the amplifier are not limited to the circuit configurations of FIGS. As shown in FIG. 24 and FIG. 26, it is only necessary to be able to output drive currents having different rising and falling time change rates by controlling the gate voltage of the transistors included in the drive circuit 21.

Embodiment 4
A fourth embodiment according to the present invention will be described. FIG. 27 shows a configuration example of the signal transmission system 6. Different voltages (VBIAS1, VBIAS2) are applied to both ends of the threshold circuit 311 of the signal transmission system 6 according to the present exemplary embodiment.

  In the receiving circuit 3 of FIG. 27, a threshold circuit 311, a capacitive element 312, and a resistive element 313 are provided at both ends of the secondary coil 12. VBIAS1 is applied to the input terminal of each threshold circuit 311 and VBIAS2 is applied to the output terminal. Each output terminal is connected to a capacitor element 312 for charging electric charges. That is, the reception signal detection circuit 31 is provided at both terminals of the secondary coil 12, and one reception signal detection circuit 32 generates a detection voltage, and the other reception signal detection circuit 32 generates a comparison voltage. . Other configurations are the same as those of the signal transmission system shown in FIG.

  Generally, since the threshold value of a threshold element is a value unique to the element, the threshold value may not be changed in circuit design. In this embodiment mode, different voltages are applied to both ends of the threshold circuit 311. Therefore, even if the voltage VR generated in the secondary coil 12 has the same magnitude, current may or may not flow through the threshold circuit 311 depending on the degree of bias. That is, an operation equivalent to increasing or decreasing the threshold value of the threshold circuit 311 can be performed.

  28 to 30 show a signal transmission system including the receiving circuit 3 that can perform the same operation as the signal transmission system 6 shown in FIG. These circuits can also substantially change the threshold value of the threshold circuit. For example, if VBIAS1 is set to a higher DC voltage than VBIAS2, current can be passed through the threshold circuit 311 even if the amplitude of VR appearing in the secondary coil 12 is small. Conversely, when VBIAS1 is set to a DC voltage lower than VBIAS2, current does not flow through the threshold circuit 311 unless the amplitude of VR appearing in the secondary coil 12 is greater than in the former case. The receiving circuit 3 shown in FIG. 30 has an input side capacitive element 35, and an input terminal of the threshold circuit 311 is connected to the secondary coil 12 via the input side capacitive element 35.

Embodiment 5
A fifth embodiment according to the present invention will be described. The signal transmission system 7 according to the present embodiment illustrated in FIG. 31 further includes a current source 33, a resistance element 34, and an input side capacitive element 35 in addition to the configuration of the reception circuit 3 illustrated in FIG. Since other configurations are the same as those of the signal transmission system 1, description thereof is omitted.

  The current source 33 and the resistance element 34 are connected between the power source and the ground. Further, the anode terminal of the diode 3111, the cathode terminal of the diode 3112, and the output terminal of the threshold circuit 311 are connected between the current source 33 and the resistance element 34. As a result, different DC voltages are applied to the anode terminal of the diode 3111, the cathode terminal of the diode 3112, and the output terminal of the threshold circuit 311. The anode terminal of the diode 3111 and the cathode terminal of the diode 3112 are connected to the secondary coil 12 via the input side capacitive element 35.

  That is, the circuit shown in FIG. 31 can control the threshold value of the threshold circuit 311 by biasing different DC voltages to both terminals of the threshold element as in the fourth embodiment. In this circuit, the DC voltage at the anode terminal of the diode 3111 is controlled by the resistor 34 and the constant current ib1, the DC voltage at the cathode terminal of the diode 3112 is controlled by the resistor 34 and the constant current ib2, and the cathode terminal of the diode 3111 and the diode 3112 are controlled. The DC voltage at the anode terminal is controlled by a resistor 34 and a constant current ib3.

  The relationship between the magnitudes of the currents i1 to i3 and the threshold will be specifically described. When the relationship between the currents i1 to i3 is ib1 <ib3 <ib2, the amplitude of the voltage VR necessary for operating the hysteresis comparator 32, that is, the amplitude of the voltage VR necessary for flowing the current to the threshold circuit 311 is the diode It becomes lower than the threshold voltage.

  On the other hand, when ib1> ib3> ib2, the amplitude of the voltage VR required to operate the hysteresis comparator 32 is higher than the threshold voltage of the diode. Thus, by using the signal transmission system 7 according to the present embodiment, the threshold voltage necessary for the voltage VR of the secondary coil 12 to operate the hysteresis comparator 32 can be set to an arbitrary value.

Embodiment 6
A sixth embodiment according to the present invention will be described. In the signal transmission system 8 illustrated in FIG. 32, the reception signal detection circuit 31 includes a peak hold circuit 314, a bottom hold circuit 315, an inverting amplifier 316, and a differential amplifier 317.

  In FIG. 32, a reception signal detection circuit 31 is connected to one end of the secondary coil 12. The other end of the secondary coil 12 is connected to the ground. The input terminals of the peak hold circuit 314 and the bottom hold circuit 315 are connected to the input terminals of the reception signal detection circuit 31. The output terminal of the peak hold circuit 314 is connected to the differential amplifier 317, and the output terminal of the bottom hold circuit 315 is connected to the differential amplifier 317 via the inverting amplifier 316.

  Here, the peak hold circuit 314 detects the positive amplitude of the waveform of the input voltage VR. On the other hand, the bottom hold circuit 315 detects the negative amplitude of the waveform of the input voltage VR. The inverting amplifier 316 inverts the waveform sent from the bottom hold circuit 315 and outputs it.

  The output terminal of the differential amplifier 317 is connected to the hysteresis comparator 32. The differential amplifier 317 sends the detection voltage and the comparison voltage generated based on the output signals of the peak hold circuit 314 and the bottom hold circuit 315 to the hysteresis comparator 32.

  Next, an operation example of the signal transmission system 8 shown in FIG. 32 will be described. The received signal detection circuit 31 included in the signal transmission system 8 compares the magnitude of the positive amplitude and the negative amplitude that appear within a predetermined time by the differential amplifier 317 and determines the logic level depending on which is larger. .

  As shown in FIG. 33, first, the peak hold circuit 314 detects a positive waveform Vpeak of the voltage VR generated in the secondary coil 12. Similarly, the bottom hold circuit 315 detects a negative waveform Vbottom of the voltage VR generated in the secondary coil 12. Next, the inverting amplifier 316 generates a signal (comparison voltage) obtained by inverting the waveform output from the bottom hold circuit 315.

  The differential amplifier 317 compares the amplitude of Vpeak with the amplitude obtained by inverting Vbottom. Then, a signal Vcomp (detection voltage and comparison voltage) to be sent to the hysteresis comparator 32 is generated using a waveform having a large amplitude as the signal component sig. Accordingly, whether the amplitude of the transmission signal output from the transmission circuit 2 is large or small, the amplitude of the signal component sig is larger than the amplitude of the noise component noise, and therefore the magnitude relationship between the positive and negative amplitudes is determined. Thus, the logic level can be determined.

  For example, if the positive amplitude detected by the peak hold circuit 314 is larger than the negative amplitude detected by the bottom hold circuit 315, only the positive amplitude appears in the differential input signal Vcomp. Therefore, the hysteresis comparator 32 determines that the logical value is high level. On the other hand, if the negative amplitude detected by the bottom hold circuit 315 is larger than the positive amplitude detected by the peak hold circuit 314, only a negative amplitude appears in the differential input signal Vcomp. Therefore, the hysteresis comparator 32 determines that the logical value is a low level.

  Here, input / output when the peak hold circuit 314 and the bottom hold circuit 315 are not used will be described with reference to the waveforms shown in FIGS. When the signal amplitude output from the transmission circuit 2 is not constant and the output signal amplitude varies due to variations in process, power supply voltage, temperature, etc., the received signal voltage is compared with a certain threshold value to determine the logical value. become unable. Further, the transfer gain of the transformer 10 changes depending on the size and inductance value of the transformer 10 and the size of the gap between the coils. For this reason, the signal amplitude appearing in the secondary coil 12 changes. Therefore, if the transformer design is changed, the trouble of tuning the threshold value of the receiving circuit 3 occurs.

  For example, as shown in FIG. 34, when the amplitude of the transmission signal output from the transmission circuit 2 is small, the amplitude of the voltage VR generated in the secondary coil 12 is also small. If the threshold value of the receiving circuit 3 is set to ± VthA, the receiving circuit 3 can correctly perform the logic determination. However, when the threshold is set to ± VthB, correct reception operation cannot be performed.

  On the other hand, as shown in FIG. 35, when the amplitude of the transmission signal output from the transmission circuit 2 is large, the amplitude of the voltage VR generated in the secondary coil 12 also increases. If the threshold value of the receiving circuit 3 is set to ± VthA, the receiving circuit 3 cannot correctly perform the receiving operation. However, when the threshold is set to ± VthB, the receiving circuit 3 can perform a correct receiving operation.

  As described above, the threshold value appropriate for the reception circuit 3 depends on the amplitude of the transmission signal output from the transmission circuit 2. In particular, when the transmission circuit 2 and the reception circuit 3 are arranged on different chips, the process conditions, power supply voltage, temperature, etc. of the transmission circuit 2 cannot be known from the reception circuit 3. Therefore, the amplitude of the transmission signal output from the transmission circuit 2 cannot be predicted. Therefore, it is difficult to set an appropriate threshold voltage.

  However, the reception signal detection circuit 31 according to the present embodiment compares the relative magnitudes of the signal component and the noise component in the amplitude of the transmission signal output from the transmission circuit 2 to determine the logical level. As a result, there is no need to set a constant threshold voltage. Therefore, it is possible to prevent the erroneous determination of the logical value due to the fluctuation of the amplitude of the signal transmitted from the transmission circuit 2 as described above.

  FIG. 36 shows a specific circuit configuration example of the receiving circuit 3 in the signal transmission system 8. The peak hold circuit 314 includes a diode 3111 and a first capacitor element 3121 as first threshold elements, and the bottom hold circuit 315 includes a diode 3112 and a second capacitor element 3122 as second threshold elements. In the signal transmission system 8, the terminals on the secondary coil 12 side of the peak hold circuit 314 and the bottom hold circuit 315 are connected to the secondary coil 12 via the input side capacitive element 35, and the same input side reference Biased by voltage. In the example shown in FIG. 36, the anode terminal of the diode 3111 and the cathode terminal of the diode 3112 have an input-side reference voltage obtained by resistance-dividing a first power supply (eg, reference voltage VREF) and a second power supply (eg, ground). And is connected to the secondary coil 12 through the input side capacitive element 35. On the other hand, the cathode terminal of the diode 3111 is connected to the differential amplifier 317, and the anode terminal of the diode 3112 is connected to the differential amplifier 317 via the inverting amplifier 316.

  The first capacitor element 3121 is connected between the cathode terminal of the diode 3111 and a third power source (for example, ground). Further, the output side reference voltage is applied to the cathode terminal of the diode 3111. The second capacitor element 3122 is connected between the anode terminal of the diode 3112 and a third power source (for example, ground). The output side reference voltage is applied to the anode terminal of the diode 3112 diode 3112.

  Subsequently, the operation of the receiving circuit 3 shown in FIG. 36 will be described. When a voltage VR exceeding the threshold value of the diode 3111 or 3112 is generated in the secondary coil 12, a current flows through the diode 3111 or 3112. The current flowing through the diode 3111 is charged in the first capacitor element 3121. That is, the positive amplitude of the voltage VR is held in the first capacitor 3121.

  On the other hand, when a current flows through the diode 3112, the current is extracted from the second capacitor element 3122. That is, the negative amplitude of the voltage VR is held in the second capacitor 3122. In this way, the peak hold circuit 314 detects the positive waveform Vpeak of the voltage VR generated in the secondary coil 12, and the bottom hold circuit 315 generates the negative waveform Vbottom of the voltage VR generated in the secondary coil 12. To detect. Subsequent operations of the inverting amplifier 316, the differential amplifier 317, and the hysteresis comparator 32 are the same as the operations described above, and thus the description thereof is omitted.

  As another example of the signal transmission system 8, FIG. 37 shows a configuration of the receiving circuit 3 in the case where the input side reference voltages applied to the anode terminal of the diode 3111 and the cathode terminal of the diode 3112 are different. As shown in FIG. 37, the input-side reference voltage is separately applied to the anode terminal of the diode 3111 and the cathode terminal of the diode 3112. In this case, in order to individually insulate the diode 3111 and the diode 3112, the input-side capacitive elements 35 are also individually provided (for example, the input-side capacitive elements provided individually are the first input-side capacitive element and the second input-side capacitive element). This is referred to as the input side capacitive element.

  In the example shown in FIG. 37, the first capacitor element 3121 is connected between the cathode terminal of the diode 311 and a first power source (for example, the reference voltage VREF), and the second capacitor element 3122 is connected to the anode of the diode 3112. Connected between the terminal and a third power source (eg, ground). The cathode terminal of the diode 3111 is connected to the normal input terminal of the first differential amplifier, and the anode terminal of the diode 3112 is connected to the inverting input terminal of the second differential amplifier. Further, the midpoint voltage generated by the resistance divider circuit connected between the cathode terminal of the diode 3111 and the anode terminal of the diode 3112 is the positive input terminal of the first differential amplifier and the positive terminal of the second differential amplifier. To the input terminal.

  As described above, the peak hold circuit 314 and the bottom hold circuit 315 are configured by a DC bias circuit, an integrator, and a diode. When a voltage higher than the DC bias voltage appears in the secondary side coil 12, the first capacitive element 3121 of the peak hold circuit 314 is charged. Thereby, a peak with a positive amplitude is detected.

  When a voltage lower than the DC bias voltage appears in the secondary coil 12, the second capacitive element 3122 of the bottom hold circuit 315 is discharged. Thereby, the bottom of a negative amplitude is detected. The polarity of the output of the bottom hold circuit 315 is inverted by the next-stage differential amplifier. The higher the negative amplitude, the higher the voltage that is output.

  The hysteresis comparator 32 receives a voltage proportional to the magnitude of the positive and negative amplitudes output from the peak hold circuit 314 and the bottom hold circuit 315, determines a logical value depending on which is larger, and outputs it as output data RxOUT. The peak hold circuit 314 and the bottom hold circuit 315 bias different DC voltages to the anode terminal of the diode 3111 and the cathode terminal of the diode 3112. Therefore, the voltage VR of the secondary coil 12 can operate the hysteresis comparator 32 without depending on the threshold inherent to the diode. That is, the threshold voltage can be set to an arbitrary voltage as in the principle described with reference to FIG.

  Here, FIG. 38 shows a configuration example of the signal transmission system 9 including the transmission circuit 2 shown in FIG. 22 and the reception circuit 3 shown in FIG. Note that the specific circuit configuration is the same as that described in FIGS. 22 and 36, and thus the description thereof is omitted.

  In the transmission circuit 2, while the signal amplitude is limited by the current source, control is performed so that the rising and falling of the current flowing through the primary coil 11 have different slopes. In the receiving circuit 3, the logical value is determined by comparing the magnitude of the positive amplitude of the received signal with the magnitude of the negative amplitude. Further, since the diodes 3111 and 3112 are threshold circuit 311 having a threshold value, if the voltage of the noise component generated in the secondary coil 12 is 0.7V or less during the current falling process of the primary coil 11, it is removed. You can also By combining such transmission / reception circuits, a signal transmission system that is less susceptible to variations in process, power supply voltage, temperature, and the like can be configured.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the arrangement of the transmission circuit 2, the reception circuit 3, and the transformer 10 is not limited to the configuration shown in FIG. In place of the hysteresis comparator 32, it is also possible to use a Schmitt trigger circuit or a state circuit that holds a value exceeding a predetermined threshold for a certain period. 39 to 46 show other implementation examples of the signal transmission system according to the present invention.

  In the mounting state shown in FIG. 39, the transmission circuit 2 is formed on the first semiconductor chip 93. On the other hand, on the second semiconductor chip 94, the primary side coil 11, the secondary side coil 12, and the receiving circuit 3 are formed. In addition, a pad connected to the transmission circuit 2 is formed on the first semiconductor chip 93, and a pad connected to the primary side coil 11 is formed on the second semiconductor chip 94. The transmission circuit 2 is connected to the primary coil 11 formed on the second semiconductor chip 94 via a pad and a bonding wire.

  In the mounting state shown in FIG. 40, the primary side coil 11, the secondary side coil 12, and the transmission circuit 2 are formed on the first semiconductor chip 93. On the other hand, the receiving circuit 3 is formed on the second semiconductor chip 94. In addition, a pad connected to the secondary coil 12 is formed on the first semiconductor chip 93, and a pad connected to the receiving circuit 3 is formed on the second semiconductor chip 94. The receiving circuit 3 is connected to the secondary coil 12 formed on the first semiconductor chip 94 via a pad and a bonding wire.

  In the mounting state shown in FIG. 41, the transmission circuit 2 is formed on the first semiconductor chip 93. On the other hand, on the second semiconductor chip 94, the primary side coil 11, the secondary side coil 12, and the receiving circuit 3 are formed. In addition, a pad connected to the transmission circuit 2 is formed on the first semiconductor chip 93, and a pad connected to the primary side coil 11 is formed on the second semiconductor chip 94. The transmission circuit 2 is connected to the primary coil 11 formed on the second semiconductor chip 94 via a pad and a bonding wire.

  In the mounting state shown in FIG. 42, the primary side coil 11, the secondary side coil 12, and the transmission circuit 2 are formed on the first semiconductor chip 93. On the other hand, the receiving circuit 3 is formed on the second semiconductor chip 94. In addition, a pad connected to the secondary coil 12 is formed on the first semiconductor chip 93, and a pad connected to the receiving circuit 3 is formed on the second semiconductor chip 94. The receiving circuit 3 is connected to the secondary coil 12 formed on the first semiconductor chip 93 via a pad and a bonding wire.

  In the example shown in FIGS. 41 and 42, the primary side coil 11 and the secondary side coil 12 are formed in the same wiring layer of one semiconductor chip. Moreover, the primary side coil 11 and the secondary side coil 12 are formed as a coil | winding which has the same center position.

  43, the transmission circuit 2 is formed on the first semiconductor chip 93, the reception circuit 3 is formed on the second semiconductor chip 94, and the primary coil 11 and the secondary are formed on the third semiconductor chip 95. A side coil 12 is formed. The first semiconductor chip 93 is formed with a pad connected to the primary side coil 11, and the second semiconductor chip 94 is formed with a pad connected to the secondary side coil 12. A pad connected to the primary coil 11 and a pad connected to the secondary coil 12 are formed on the semiconductor chip 95. The transmission circuit 2 is connected to the primary coil 11 formed on the third semiconductor chip 95 via pads and bonding wires, and the reception circuit 3 is connected to the third semiconductor chip 95 via pads and bonding wires. The secondary coil 12 is connected to the secondary coil 12. In the example shown in FIG. 43, the primary side coil 11 and the secondary side coil 12 are formed by using a first wiring layer and a second wiring layer which are stacked in the vertical direction in one semiconductor chip. .

  The example shown in FIGS. 44 and 45 is an example in which the transmission circuit 2 and the primary side coil 11 are formed on the first semiconductor substrate, and the reception circuit 2 and the secondary side coil 12 are formed on the second semiconductor substrate. . In the example shown in FIGS. 44 and 45, a first semiconductor chip 93 and a second semiconductor chip 94 are stacked. 44 and 45, in the stacked state, the first semiconductor chip 93 and the central position of the primary side coil 11 and the central position of the secondary side coil 12 are on the same straight line. A second semiconductor chip 94 is disposed.

  In the example shown in FIG. 46, the transmission circuit 2, the reception circuit 3, the primary coil 11, and the secondary coil 12 are formed on the same semiconductor substrate 96. In the example shown in FIG. 46, the primary side coil 11 and the secondary side coil 12 are formed using a first wiring layer and a second wiring layer that are stacked in the vertical direction. The region where the transmission circuit 2 is disposed and the region where the reception circuit 3 is disposed are insulated from each other by an insulating layer formed on the semiconductor substrate 96.

  Here, cross-sectional views of the semiconductor substrate 96 are shown in FIGS. In the example shown in FIG. 47, the region where the transmission circuit 2 is formed and the region where the reception circuit 3 is formed are electrically separated by an insulating layer. And the primary side coil 11 and the secondary side coil 12 are provided in the area | region in which the receiving circuit 3 is formed. On the other hand, in the example shown in FIG. 48, the region where the transmission circuit 2 is formed and the region where the reception circuit 3 is formed are electrically separated by an insulating layer. And the primary side coil 11 and the secondary side coil 12 are provided in the area | region in which the transmission circuit 2 is formed.

1, 4 to 9 Signal transmission system 2 Transmission circuit 3 Reception circuit 10 Transformer 11 Primary side coil 12 Secondary side coil 21 Drive circuit 22 Pre-driver circuit 31 Reception signal detection circuit 32 Hysteresis comparator 33 Current source 34 Resistance element 35 Input side capacitance Element 91 Semiconductor package 92 Lead terminal 93 First semiconductor chip 94 Second semiconductor chip 95 Third semiconductor chip 96 Semiconductor substrate 211 Current source 221 Pulse generator 222 Current source 311 Threshold circuit 312 Capacitance element 313 Resistance element 314 Peak hold Circuit 315 Bottom hold circuit 316 Inverting amplifier 317 Differential amplifier 3111, 3112 Diode 3121 First capacitive element 3122 Second capacitive element

Claims (20)

  1. Reception caused by a transmission signal flowing in the primary side coil to a secondary side coil magnetically coupled to a primary side coil driven by a positive drive current or a negative drive current whose increase rate and decrease rate are asymmetric. A receiving circuit for receiving a signal,
    A reception signal detection circuit that is connected to one terminal of the secondary coil and outputs a detection voltage corresponding to a difference in absolute value between a positive amplitude and a negative amplitude of the reception signal;
    A hysteresis comparator that reproduces transmission data that generates the reception signal based on a voltage difference between the detection voltage and a comparison voltage ;
    The received signal detection circuit includes:
    An input terminal is connected to the secondary side coil, an output terminal is connected to the hysteresis comparator, and has a threshold circuit through which a current flows when a certain voltage difference occurs between the input terminal and the output terminal,
    A receiving circuit to which an output terminal of the threshold circuit is applied with a reference voltage, is connected to a voltage source of the reference voltage via a capacitive element, and holds the reception signal in the capacitive element .
  2. The reception signal detection circuit generates the detection voltage by holding the reception signal based on a voltage value and a voltage holding period corresponding to a difference in absolute value between a positive amplitude and a negative amplitude of the reception signal. The receiving circuit according to claim 1 .
  3. The receiving circuit according to claim 1 or 2 , wherein the receiving circuit is further connected to the other terminal of the secondary coil, and the receiving signal detecting circuit outputs the comparison voltage.
  4. The receiving circuit according to claim 1 , wherein an input side reference voltage is applied to an input terminal of the threshold circuit.
  5. The receiving circuit according to claim 4 , wherein an input terminal of the threshold circuit is connected to the secondary side coil via an input side capacitive element.
  6. The threshold circuit includes:
    Having first and second threshold elements through which a current flows when a certain voltage difference occurs between the input terminal and the output terminal;
    The input terminal of the first threshold element and the output terminal of the second threshold element are connected to the secondary coil,
    The receiving circuit according to claim 4 , wherein an output terminal of the first threshold element and an input terminal of the second threshold element are connected to the hysteresis comparator.
  7. The input-side reference voltages independent of each other are applied to the input terminal of the first threshold element and the output terminal of the second threshold element,
    An input terminal of the first threshold element is connected to the secondary coil via a first input side capacitive element;
    The receiving circuit according to claim 6 , wherein an output terminal of the second threshold element is connected to the secondary coil via a second input side capacitive element.
  8. Reception caused by a transmission signal flowing in the primary side coil to a secondary side coil magnetically coupled to a primary side coil driven by a positive drive current or a negative drive current whose increase rate and decrease rate are asymmetric. A receiving circuit for receiving a signal,
    A reception signal detection circuit that is connected to one terminal of the secondary coil and outputs a detection voltage corresponding to a difference in absolute value between a positive amplitude and a negative amplitude of the reception signal;
    A hysteresis comparator that reproduces transmission data that generates the reception signal based on a voltage difference between the detection voltage and a comparison voltage ;
    The received signal detection circuit includes:
    A peak hold circuit that detects a positive amplitude of the received signal and outputs a peak hold voltage in which a voltage value and a voltage holding period are determined according to the magnitude of the positive amplitude;
    A bottom hold circuit that detects a negative amplitude of the received signal and outputs a bottom hold voltage in which a voltage value and a voltage holding period are determined according to the magnitude of the negative amplitude;
    An inverting amplifier that outputs a hold voltage obtained by inverting the polarity of the bottom hold voltage;
    A differential amplifier that generates and outputs the detection voltage and the comparison voltage according to a voltage difference between the peak hold voltage and the inverted hold voltage;
    A receiving circuit comprising:
  9. The peak hold circuit includes a first threshold element having an input terminal connected to the secondary coil and an output terminal connected to the differential amplifier, and charge supplied via the first threshold element. A first capacitor element for storage,
    The bottom hold circuit includes a second threshold element having an input terminal connected to the differential amplifier via the inverting amplifier and an output terminal connected to the secondary coil, and the second threshold element. The receiving circuit according to claim 8 , further comprising: a second capacitive element that discharges the electric charge accumulated through the second capacitive element.
  10. The receiving circuit according to claim 9 , wherein different reference voltages are applied to an output terminal of the first threshold element and an input terminal of the second threshold element.
  11. The same input side reference voltage is applied to the input terminal of the first threshold element and the output terminal of the second threshold element,
    The receiving circuit according to claim 9 or 10 , wherein an input terminal of the first threshold element and an output terminal of the second threshold element are connected via the secondary coil via an input side capacitive element. .
  12. Independent input-side reference voltages are applied to the input terminal of the first threshold element and the output terminal of the second threshold element,
    An input terminal of the first threshold element is connected to the secondary coil via a first input side capacitive element;
    The receiving circuit according to claim 9 or 10 , wherein an output terminal of the second threshold element is connected to the secondary coil via a second input-side capacitive element.
  13. A non-inverting amplifier that amplifies the peak hold voltage and provides the differential amplifier to the differential amplifier;
    In the normal amplifier, the peak hold voltage is applied to the normal input terminal,
    In the inverting amplifier, the bottom hold voltage is applied to an inverting input terminal,
    Wherein the inverting input terminal and non-inverting input terminal of the inverting amplifier of the forward amplifier of claims 8 to 12 midpoint voltage having a voltage value between the peak hold voltage and the bottom hold voltage is applied The receiving circuit according to any one of the above.
  14. The first and second threshold elements are diodes,
    Input terminals of the first and second threshold elements is an anode of the diode, the cathode is a claim 6,9,10,11 of the output terminals of the first and second threshold elements the diode and, 13. The receiving circuit according to any one of items 12 .
  15. The first and second threshold elements are transistors whose drain and gate are short-circuited,
    Either the drain or the source of the transistor is connected to the input terminals of the first and second threshold elements, and the drain and the source of the transistor are connected to the output terminals of the first and second threshold elements. The receiving circuit according to any one of claims 6, 9, 10, 11 , and 12, to which the other is connected.
  16. Reception caused by a transmission signal flowing in the primary side coil to a secondary side coil magnetically coupled to a primary side coil driven by a positive drive current or a negative drive current whose increase rate and decrease rate are asymmetric. A receiving method for receiving a signal,
    Detecting the positive amplitude of the received signal, holding the received signal based on a voltage value and a voltage holding period according to the magnitude of the positive amplitude,
    Detecting the negative amplitude of the received signal, holding the received signal based on a voltage value and a voltage holding period according to the magnitude of the negative amplitude,
    Invert the polarity of the received signal held based on the magnitude of the negative amplitude,
    Generating a detection voltage and a comparison voltage according to a voltage difference between the received signal held based on the magnitude of the positive amplitude and the inverted received signal;
    A reception method for reproducing transmission data generated from the reception signal based on a voltage difference between the detection voltage and a comparison voltage.
  17. The detection voltage is generated according to claim 16 , wherein the detection voltage is generated by holding the reception signal based on a voltage value and a voltage holding period corresponding to a difference in absolute value between a positive amplitude and a negative amplitude of the reception signal. Reception method.
  18. By holding the received signal based on the positive amplitude and the negative voltage value and the voltage holding period corresponding to the difference between the absolute value of the amplitude of the received signal, to claim 16 or 17 to generate the comparison voltage The receiving method described.
  19. A primary coil provided on the transmission circuit side;
    A secondary coil that is magnetically coupled to the primary coil;
    A pre-driver circuit for outputting a drive motion control signal in response to the rising or falling edge of the transmit signal generated on the basis of the transmission data,
    A drive circuit for supplying a positive drive current or a negative drive current in which an increase rate and a decrease rate are asymmetric to the primary side coil according to the drive control signal;
    A reception signal that is connected to one terminal of the secondary side coil and outputs a detection voltage corresponding to a difference in absolute value between a positive amplitude and a negative amplitude of the reception signal generated in the secondary side coil by the transmission signal A detection circuit;
    A hysteresis comparator that reproduces transmission data that generates the reception signal based on a voltage difference between the detection voltage and a comparison voltage ;
    The received signal detection circuit includes:
    An input terminal is connected to the secondary side coil, an output terminal is connected to the hysteresis comparator, and has a threshold circuit through which a current flows when a certain voltage difference occurs between the input terminal and the output terminal,
    A signal transmission system in which a reference voltage is applied to an output terminal of the threshold circuit, and the reference voltage is connected to a voltage source of the reference voltage via a capacitive element, and the received signal is held in the capacitive element .
  20. A primary coil provided on the transmission circuit side;
    A secondary coil that is magnetically coupled to the primary coil;
    A pre-driver circuit for outputting a drive motion control signal in response to the rising or falling edge of the transmit signal generated on the basis of the transmission data,
    A drive circuit for supplying a positive drive current or a negative drive current in which an increase rate and a decrease rate are asymmetric to the primary side coil according to the drive control signal;
    A reception signal that is connected to one terminal of the secondary side coil and outputs a detection voltage corresponding to a difference in absolute value between a positive amplitude and a negative amplitude of the reception signal generated in the secondary side coil by the transmission signal A detection circuit;
    A hysteresis comparator that reproduces transmission data that generates the reception signal based on a voltage difference between the detection voltage and a comparison voltage ;
    The received signal detection circuit includes:
    A peak hold circuit that detects a positive amplitude of the received signal and outputs a peak hold voltage in which a voltage value and a voltage holding period are determined according to the magnitude of the positive amplitude;
    A bottom hold circuit that detects a negative amplitude of the received signal and outputs a bottom hold voltage in which a voltage value and a voltage holding period are determined according to the magnitude of the negative amplitude;
    An inverting amplifier that outputs a hold voltage obtained by inverting the polarity of the bottom hold voltage;
    A differential amplifier that generates and outputs the detection voltage and the comparison voltage according to a voltage difference between the peak hold voltage and the inverted hold voltage;
    A signal transmission system comprising:
JP2010006175A 2010-01-14 2010-01-14 Reception circuit, reception method, and signal transmission system Expired - Fee Related JP5504903B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010006175A JP5504903B2 (en) 2010-01-14 2010-01-14 Reception circuit, reception method, and signal transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010006175A JP5504903B2 (en) 2010-01-14 2010-01-14 Reception circuit, reception method, and signal transmission system

Publications (2)

Publication Number Publication Date
JP2011146934A JP2011146934A (en) 2011-07-28
JP5504903B2 true JP5504903B2 (en) 2014-05-28

Family

ID=44461393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010006175A Expired - Fee Related JP5504903B2 (en) 2010-01-14 2010-01-14 Reception circuit, reception method, and signal transmission system

Country Status (1)

Country Link
JP (1) JP5504903B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10430701B2 (en) 2016-08-01 2019-10-01 Samsung Electronics Co., Ltd. Magnetic secure transmission device, electronic device and mobile system including the same

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5891100B2 (en) * 2012-04-26 2016-03-22 ルネサスエレクトロニクス株式会社 Semiconductor device and data transmission method
JP6017232B2 (en) * 2012-09-07 2016-10-26 ルネサスエレクトロニクス株式会社 Transmitting apparatus and communication system
JP6248649B2 (en) * 2014-01-23 2017-12-20 株式会社デンソー Isolated communication device
JP6138074B2 (en) * 2014-03-07 2017-05-31 三菱電機株式会社 Signal transmission circuit
JP6272509B2 (en) 2015-01-20 2018-01-31 三菱電機株式会社 Signal transmission device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5701037A (en) * 1994-11-15 1997-12-23 Siemens Aktiengesellschaft Arrangement for inductive signal transmission between the chip layers of a vertically integrated circuit
US8477855B2 (en) * 2006-01-30 2013-07-02 Nec Corporation Signal transmission system and semiconductor integrated circuit device
JP2009060275A (en) * 2007-08-30 2009-03-19 Toyota Industries Corp Signal transfer circuit
JP4957495B2 (en) * 2007-10-03 2012-06-20 株式会社豊田自動織機 Signal transmission circuit
JP5600237B2 (en) * 2008-02-02 2014-10-01 学校法人慶應義塾 Integrated circuit
US20110291702A1 (en) * 2009-02-09 2011-12-01 Shunichi Kaeriyama Signal transmission system and signal transmission method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10430701B2 (en) 2016-08-01 2019-10-01 Samsung Electronics Co., Ltd. Magnetic secure transmission device, electronic device and mobile system including the same

Also Published As

Publication number Publication date
JP2011146934A (en) 2011-07-28

Similar Documents

Publication Publication Date Title
US6008665A (en) Termination circuits and methods therefor
US6459322B1 (en) Level adjustment circuit and data output circuit thereof
US7853236B2 (en) Rectifier circuit and RFID tag
EP1199790A2 (en) Power supply pulse width modulation (PWM) control system
US5923219A (en) Automatic threshold control circuit and signal amplifying circuit for amplifying signals by compensating for low-frequency response of photodetector
US20100066450A1 (en) High-Speed Low-Power Differential Receiver
US7898823B2 (en) Quasi-resonant fly-back converter without auxiliary winding
US6960925B2 (en) Input buffer with automatic switching point adjustment circuitry, and synchronous DRAM device including same
KR100933651B1 (en) Half-bridge driver, and a power conversion system with such a driver,
US6803825B2 (en) Pseudo-differential transimpedance amplifier
TWI519044B (en) A system and method for adjusting the output current of a power conversion system
US20030218508A1 (en) Transimpedance amplifier with selective DC compensation
US20090128116A1 (en) Switching regulator
KR100943865B1 (en) Isolation interface with capacitive barrier and method for transmitting a signal by means of such isolation interface
US20190372397A1 (en) Reducing corruption of communication in a wireless power transmission system
US8260155B2 (en) Carrier detection circuit, method for controlling carrier detection circuit, and infrared signal processing circuit having the carrier detection circuit
US7372289B2 (en) Semiconductor integrated circuit device and power supply voltage monitor system employing it
CN103227648A (en) Ground referenced single-ended signaling
DE102012208124A1 (en) Ringing suppression circuit
TW201415188A (en) Method of automatically adjusting determination voltage and voltage adjusting device
US7218903B2 (en) Squelch detecting circuit
EP2547000A1 (en) Signal transmitting apparatus
JP5157959B2 (en) Class D amplifier
EP1587226B1 (en) Reactance adjustment device, transceiver and transmission device using the same, signal processing circuit suitable for them, reactance adjustment method, transmission method, and reception method
US9338036B2 (en) Data-driven charge-pump transmitter for differential signaling

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20121210

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20131213

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140107

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140123

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140218

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140303

R150 Certificate of patent or registration of utility model

Ref document number: 5504903

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees