JP2011019373A - Demodulation circuit, power transmission controller, power transmitter, electronic apparatus, and method of demodulating data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately demodulate a signal transmitted by load modulation from a power reception apparatus, by using the detected amplitude of coil end voltage of a primary coil, and preferably to detect a removal/placement of the power reception apparatus or secondary apparatus including the power reception apparatus, by using a common amplitude detection circuit.SOLUTION: A demodulation circuit DM is provided in a power transmission apparatus of a contactless power transmission system and demodulates a signal transmitted by load modulation from the power reception apparatus; and the demodulation circuit DM includes a differential circuit SAMP that outputs a differential signal Aout (for example, a sine wave) between a first signal CSG from one end of a resonance capacitor CP1 connected to the primary coil L1 and a second signal DRV from the other end of the resonance capacitor CP1 and an amplitude detection circuit AMT, that detects the level of amplitude of the differential signal Aout output from the differential circuit SAMP.

Description

  The present invention relates to a demodulation circuit, a power transmission control device, a power transmission device, an electronic device, a data demodulation method, and the like.

  In a non-contact power transmission system, for example, frequency modulation is used for data communication from the power transmission device to the power reception device, and load modulation is used for data communication from the power reception device to the power transmission device (for example, Patent Documents 1 to 5). Reference 3).

  Patent Document 1 discloses a technique for demodulating data transmitted by a power receiving device by load modulation using a peak detection circuit (FIG. 1 of Patent Document 1). Since the voltage level of the coil end voltage of the primary coil varies depending on on / off of the load modulation transistor included in the power receiving apparatus, data can be demodulated by peak detection (paragraph (0022) of Patent Document 1). (0023) paragraph, (0054) paragraph). In Patent Document 1, the peak detection circuit detects the voltage level of the coil end voltage obtained from one end of the resonant capacitor connected to the primary coil. In Patent Document 1, the power receiving apparatus turns off a transistor provided between a power supply line and a load (battery or the like) to be fed to temporarily stop feeding power to the load to be fed ( In other words, a no-load period is provided), and data transmission by load modulation is executed in the no-load period (paragraph (0054) of Patent Document 1).

  In Patent Document 2, a pulse width detection circuit is used in place of the peak detection circuit in order to demodulate data transmitted by the power receiving device by load modulation. The pulse width detection circuit detects the pulse width information of the coil end voltage of the primary coil based on the drive clock that defines the drive frequency (AC frequency) of the primary coil. Since the pulse width changes according to on / off of the load modulation switch, data can be demodulated by detecting the pulse width information.

  In the non-contact power transmission system described in Patent Document 3, the power transmission device (primary side) detects a load state of the power reception device (secondary side), and a first waveform detection circuit for detecting a primary foreign object. (Adopting a pulse width rising detection method), a secondary waveform detection circuit for detecting secondary foreign matter and data (adopting a pulse width falling detection method), and a third waveform detection for detecting the removal of the power receiving device. The circuit (adopting the peak detection method) is used in combination to achieve more accurate load state detection.

JP 2006-60909 A (paragraph (0022), paragraph (0023), paragraph (0054), FIG. 1) JP 2008-237007 A (for example, paragraph (0007), paragraph (0008) and FIG. 5) JP 2009-33955 A (for example, (0107) paragraph, (0109) paragraph, (0176) paragraph, (0184 paragraph), (0187 paragraph), FIG. 11 and FIG. 24)

(1) Study on peak detection method When the power receiving device (secondary side) transmits data by load modulation, the voltage level of the coil end voltage of the primary coil changes, and the peak detecting circuit provided in the power transmitting device As described above, Patent Document 1 describes that communication data can be demodulated by peak value detection and comparison determination. However, Patent Document 1 shows the principle of demodulation, and it cannot be denied that there is a limit to the actual demodulation accuracy. Therefore, in Patent Document 2, instead of the peak detection method, communication using a pulse width detection method is performed. A data demodulation method is adopted.

  One reason that the accuracy of the demodulation method of the peak detection method described in Patent Document 1 is limited is that, as described in the background art section of Patent Document 2, “variation in power supply voltage, coil inductance, etc.” As a result, the coil end voltage also varies, making it difficult to optimally adjust the reference voltage for comparison and determination.

  Another reason is that not only the amplitude of the coil end voltage of the primary coil but also the waveform of the coil end voltage of the primary coil itself is changed by the load modulation on the secondary side (in other words, the distortion of the waveform). Difference in degree). Specifically, the waveform of the coil end voltage of the primary coil is a waveform obtained by synthesizing the resonance waveform (for example, sine wave) of the resonance circuit and the AC drive signal (drive clock) of the primary coil, and 2 The amplitude (and some phase) of the resonance waveform is changed by the load modulation transistor on the secondary side, and the drive clock (constant regardless of the load modulation) is synthesized with the resonance waveform. As a result, the waveform of the coil end voltage is deformed. For example, if only the amplitude of the sine wave obtained from the coil end of the primary coil is changed by the load modulation on the secondary side (the waveform itself is maintained as a sine wave), the peak detection voltage on the primary side It is considered that the change in the voltage level depends on only the load state on the secondary side. However, if not only the coil end voltage amplitude but also the coil end voltage waveform itself fluctuates due to load modulation, the fluctuation of the DC voltage level obtained by smoothing the coil end voltage is due to the change in the amplitude of the coil end voltage. Whether it is due to a change in the waveform of the coil end voltage cannot be determined. That is, the change in the DC voltage due to the change in the waveform of the coil end voltage becomes a noise component during peak detection.

  In addition, noise associated with the driving of the primary coil is also superimposed on the coil end voltage, and this is also a factor that causes a limit in the determination accuracy of the peak detection method.

(2) Study on Pulse Width Detection Method Therefore, Patent Document 2 adopts a pulse width detection method instead of the peak detection method. The outline of the pulse width detection method is as follows. That is, the waveform of the coil end voltage of the primary coil is superimposed with the AC drive waveform (square wave) DRCK of the primary coil and the resonance waveform (sine wave) SWV of the resonance circuit. Specifically, when there is no load, a series resonance circuit is configured by the resonant capacitor C, the primary side leakage inductance L1, and the coupling inductance M. When there is a load, the secondary side leakage inductance L2 The resistance RL of the secondary side load is also added to the components of the resonance circuit. Then, when there is a load, the resonance frequency of the sine wave SWV increases as the load changes from low to high, and approaches the frequency of the AC drive waveform DRCK of the primary coil.

  When the resonance frequency of the resonance circuit is low, the AC drive waveform DRCK is dominant, but as the resonance frequency increases, the influence of the resonance waveform (sine wave) SWV increases, and eventually the resonance waveform (sine wave) SWV Becomes more dominant. As a result, the waveform obtained by superimposing the AC drive waveform (square wave) DRCK and the resonance waveform (sine wave) SWV of the resonance circuit has a change that the width of the front end portion of the waveform becomes narrower as the load on the secondary side becomes heavier. Show. Therefore, by detecting the change in the width of the waveform by the pulse width detection circuit, the change in the load state on the secondary side can be detected with high accuracy.

(3) Examination of combined use of peak detection method and pulse width detection method In Patent Document 3, three waveform detection circuits are selectively used for different purposes. That is, the first waveform detection circuit for primary foreign object detection (adopting a pulse width rising detection method) and the second waveform detection circuit for secondary foreign object detection and data detection (adopting a pulse width falling detection method) And a third waveform detection circuit for detecting removal of the power receiving device (adopting a peak detection method) are used in combination to realize highly accurate load state detection.

  In other words, Patent Document 3 employs a pulse width detection method capable of highly accurate data demodulation for detecting communication data by load modulation. Although the peak detection method has a limit in data demodulation accuracy, it can be used sufficiently for the determination of two states where the secondary device is present / not present, and the peak detection circuit has a circuit configuration. Since there is an advantage that it is simple, a peak detection method is adopted for detection of removal of the power receiving apparatus (that is, detection of removal of the power receiving apparatus is performed by determining whether or not there is a secondary device (determination of two states). The accuracy may be lower than that of data demodulation, and the detection time can be increased, so that the peak detection method can be used).

  As described in Patent Document 3, if the peak detection method and the pulse width detection method are used in combination, and used properly according to the detection application (that is, the peak detection method is used for removal detection and landing detection of the power receiving device, (If the width detection method is used for data demodulation), it is possible to detect the load state with high functionality and high accuracy. However, the circuit configuration becomes complicated as multiple circuits are used together, and the area occupied by the circuit and the power consumption are reduced. It cannot be denied that it increases.

(Study on multi-transmission)
In addition, for example, if a single power transmission device is intended to realize multi-power transmission that enables power supply to a plurality of secondary devices having different power ratings, at least a part of the power transmission device can withstand a high power level. Therefore, it is necessary to employ power circuit elements that can be used (power transistors, high-voltage capacitors, resistors having a considerably large resistance value, etc.), and there is a tendency that the area occupied by the circuit and the power consumption increase. Therefore, for example, considering multi-power transmission, it is preferable to suppress an increase in the area occupied by the circuit by simplifying the detection circuit on the primary side.

  Therefore, the determination accuracy by peak detection is improved and can be used for demodulating communication data, and the peak detection circuit is used for data demodulation and detection of removal of the power receiving device (or landing detection, foreign object detection, or all of them). If they can be used in common, it is not necessary to use different types of circuits in combination, which is advantageous for realizing a small sized cradle (primary side charger) with low power consumption.

(Consider constant communication)
On the other hand, with regard to demodulation of a signal from a power receiving apparatus, in recent years, a technique for performing load modulation without stopping power supply to a load to be supplied with respect to communication from the power receiving apparatus to the power transmitting apparatus, that is, power supply and transmission to the load It is necessary to consider that a technique for simultaneously executing the above is being studied. Since the technology for transmitting a signal by load modulation without stopping power supply enables transmission by load modulation at any time during the power supply period (without time restrictions), the applicant has stated that “always communication (power supply non-stop communication) ) ".

  When the load modulation is performed only during the no-load period in which the power supply is stopped as in Patent Document 1, it cannot be denied that the power supply efficiency to the load is reduced due to the intermittent power supply stop. Since this is performed intermittently, power supply efficiency does not decrease. However, when performing constant communication, the time-dependent fluctuation of the load state of the load to be supplied (battery, etc.) directly affects data transmission by load modulation, so the accuracy of data demodulation on the power transmission device side It cannot be denied that it is more difficult to ensure the above. The conventional technique described in Patent Document 1 (a technique of demodulating a signal from a power receiving apparatus using peak detection) has a limit in detection accuracy as described above, and for example, high-precision detection as described above is required. It cannot be used for signal demodulation.

  According to at least one aspect of the present invention, it is possible to realize high-precision demodulation of a signal transmitted from a power receiving apparatus by load modulation using, for example, amplitude detection of a coil end voltage of a primary coil. Further, for example, removal of the power receiving device including the power receiving device and detection of landing can be realized using a common amplitude detection circuit.

  (1) One aspect of the demodulation circuit of the present invention is provided in the power transmission device of a contactless power transmission system that electromagnetically couples a primary coil and a secondary coil to transmit power from the power transmission device to the power reception device. A demodulating circuit for demodulating a signal transmitted by the power receiving device by load modulation, wherein a first signal from one end of a resonant capacitor connected to the primary coil and a second signal from the other end of the resonant capacitor; A differential circuit that outputs a differential signal from the differential circuit, and an amplitude detection circuit that detects an amplitude level of the differential signal output from the differential circuit.

  In this aspect, two coil end signals (first signal and second signal) are taken out from both ends of the resonant capacitor connected to the primary coil, and a differential signal is generated by a differential circuit (differential amplifier or the like). By detecting the amplitude level (voltage level, etc.) of the difference signal, the signal transmitted by the power receiving apparatus by load modulation is demodulated.

  Here, the first signal input to one end of the differential circuit is, for example, a signal based on the first coil end signal obtained from the first node on the power transmission driver side of the resonant capacitor (the first coil end signal itself may be, Similarly, the second signal input to the other end of the differential circuit is the primary coil of the resonance capacitor. This is a signal based on the second coil end signal obtained from the second node on the side. In this case, the AC drive signal (square wave) of the primary coil output from the power transmission driver is obtained from the second node almost as it is, and the signal becomes the second signal. On the other hand, from the first node, the resonance signal of the resonance circuit (for example, a sine wave) constituted by the resonance capacitor, the leakage inductance of the primary and secondary coils, the impedance of the secondary coil, etc. A waveform in which (square wave) is superimposed is obtained. That is, since the drive signal is an AC signal, it passes through the resonance capacitor and is superimposed on the resonance waveform, and the combined waveform of the resonance waveform and the drive signal (square wave) becomes the first signal.

  When the difference between the first signal and the second signal is taken, the component (in-phase component) of the drive signal (square wave) that is commonly included in the first signal and the second signal is canceled out, and thus included in the first signal. Only a resonance waveform (for example, a sine wave) is obtained. This sine wave is a differential signal. The amplitude of the differential signal varies according to the on / off state of the secondary side load modulation transistor. The differential signal functions as an amplitude-modulated carrier (communication carrier) whose amplitude changes according to on / off of the load transistor on the secondary side, and the waveform itself is not affected by on / off of the load modulation transistor. (Strictly speaking, the phase of the resonance waveform (sinusoidal wave) also varies slightly according to the on / off state of the load modulation transistor on the secondary side. However, since the waveform is not synthesized as in the prior art, the waveform It can be said that no deformation occurs.)

  In addition, a problem that has been regarded as a problem in the past is that it is difficult to optimally adjust the reference voltage for comparison judgment because the coil end voltage level also varies due to variations in power supply voltage, coil inductance, etc. There is no problem with the method of extracting only the difference component (relative component) between the first signal and the second signal. Specifically, for example, a DC cut capacitor is provided in front of the differential circuit, and the DC bias circuit can independently set the DC bias of the input node and the output node of the differential circuit. The fluctuation of the DC level of the voltage itself is not a problem.

  Even if noise is generated due to the drive clock of the primary coil or the back electromotive force of the coil, the noise is superimposed on both the first signal and the second signal, so that the in-phase component of the differential circuit The canceling action does not affect the differential signal output from the differential circuit.

  Therefore, according to this aspect, all the problems that have been the conventional problems are solved, and the determination of H and L can be made by paying attention only to the amplitude of the difference signal, so that highly accurate signal demodulation is realized. In other words, high-precision signal demodulation can be performed by the amplitude detection method (peak detection method), and the signal demodulation method of this aspect is also applied to the non-contact power system in which the above-described constant communication (power supply non-stop communication) is performed. can do.

  Further, as described above, the amplitude detection method can also be used to detect removal of the power receiving device and detection of landing. Therefore, according to this aspect, the secondary side is load-modulated by one demodulation circuit (detection circuit). Both high-accuracy demodulation of a signal to be transmitted, and removal of a power receiving device (or a secondary device including the power receiving device) and detection of landing can be realized. In this case, the primary side The detection circuit can be simplified, the area occupied by the circuit can be reduced, and the power consumption can be reduced. In addition, the demodulation technique of this aspect contributes to the realization of a non-contact power transmission system that supports multi-power transmission in which power is transmitted to a plurality of secondary devices having different power ratings with one primary device.

  (2) In another aspect of the demodulation circuit of the present invention, the amplitude detection circuit includes a peak hold circuit, and the peak hold circuit is also used for detecting at least one of removal of the power receiving device and landing.

  In this embodiment, a peak hold circuit with a simple configuration is used as the amplitude detection circuit. The peak hold circuit is used for both demodulation of the signal and detection of at least one of removal of the power reception device (or the secondary device including the power reception device) and landing detection. Therefore, the primary side detection circuit can be simplified.

  (3) In another aspect of the demodulation circuit of the present invention, the amplitude detection circuit compares the output voltage of the peak hold circuit with a determination threshold value and outputs an amplitude detection signal of the differential signal. And a demodulation determination circuit.

  In this aspect, it is clarified that the peak hold circuit and the demodulation determination circuit can be cited as the components of the amplitude detection circuit. That is, the peak voltage (amplitude value) of the differential signal output from the differential circuit is detected by the peak hold circuit, and the signal is demodulated by comparing the detected peak voltage with the determination threshold value in the demodulation determination circuit. . The demodulation of this signal is executed, for example, every cycle of the AC drive signal (drive clock) of the primary coil. That is, “signal demodulation” in this aspect is, for example, demodulation of a binary signal of H and L (first demodulation processing) synchronized with an AC drive clock (drive clock) of the primary coil. In order to demodulate 1-bit data (“1” or “0”) transmitted from the secondary side, a plurality of binary signals (H , L) requires a second demodulation process including correlation detection (continuity and periodicity detection). The amplitude detection circuit can execute both the first demodulation process and the second demodulation process, and executes only the first demodulation process. The obtained binary signal is transmitted to, for example, a power transmission side control unit (for example, a CPU). The determination of “1” or “0” can be left to the power transmission control unit.

  For example, since a predetermined period is required for the coil end voltage of the primary coil to change following the load state on the secondary side, the secondary side has 1-bit communication packet data “ When transmitting 1 ″, for example, the load modulation transistor is continuously turned on for a period corresponding to 32 cycles (32 clocks) of the drive clock. As a result, the amplitude of the communication carrier (sine wave that is a resonance waveform) having the same period as the drive clock increases over 32 periods. That is, for example, 1-bit “1” is transmitted from the secondary side to the primary side, that is, 32 Hs are transmitted from the secondary side to the primary side in synchronization with the cycle of the drive clock. Means that.

  The demodulation circuit of this aspect determines H and L for each cycle of the drive clock using the demodulation determination circuit, and demodulates the binary signal of H and L (first demodulation process). When the demodulation circuit also demodulates 1-bit data, a correlation detector (for example, a low-pass filter when an analog detection method is employed, and a digital detection method) When employed, it is necessary to provide an output circuit including a determination circuit that determines whether a predetermined number of the same value continuously appears and determines a cycle in which the same value continuously appears. (The point that the demodulation circuit further includes an output circuit is clarified in claim 14 ((14) below)).

  For example, when the binary demodulated signals of H and L (for each drive clock cycle) output from the demodulation determination circuit of this aspect are continuously H for a predetermined number (for example, 7 times), the secondary When it is determined that the transmission data on the side has changed from “0” to “1” and the H appears in units of 32 periods of the drive clock, the received data is “1” of the communication packet data. If the H appears in units of 16 periods of the drive clock, the communication data detects whether a foreign object has been inserted between the periodic authentication pattern (primary coil and secondary coil). Therefore, it is determined that the pattern signal is “1” periodically transmitted from the secondary side.

  In this way, the “demodulation determination circuit” in this aspect detects the amplitude of the differential signal, for example, “every cycle of the drive clock”. When an “output circuit” is provided in the subsequent stage, the output circuit detects the amplitude of the differential signal in “one-bit duration unit”, and both detect “the amplitude of the differential signal” The first demodulated signal (H and L binary signal) and the second demodulated signal (binary data) are both referred to as the “amplitude detection signal of the differential signal”, which is an input signal. (Therefore, it is clear that the above “output circuit” can also be a component of the amplitude detection circuit.) However, the unit time of amplitude detection is different between the first demodulation process and the second demodulation process. Will be.

  (4) In another aspect of the demodulation circuit of the present invention, the amplitude detection circuit includes an integration circuit including at least one resistor and a peak hold capacitor, the differential signal output from the differential circuit, and the peak hold. A comparison circuit for comparing the voltage of the capacitor; a feedback path for feeding back the output signal of the integration circuit to the comparison circuit; a switch provided between the output node of the comparison circuit and the input node of the integration circuit; When the switch is off, the peak hold capacitor and the comparison circuit operate as a demodulation determination circuit that outputs an amplitude detection signal of the differential signal.

  In this embodiment, the comparison circuit (and peak hold capacitor) included in the peak hold circuit is also used for demodulating binary data (H, L). This eliminates the need to provide a demodulation determination circuit separately from the peak hold circuit, thereby further simplifying the demodulation circuit.

  For example, the peak hold circuit basically includes a time constant circuit including a peak hold capacitor in the negative feedback loop of the comparison circuit, and the voltage of the peak hold capacitor is input to the comparison circuit by negative feedback control. This circuit matches the voltage and holds the peak voltage, and necessarily includes a comparison circuit. In this aspect, as described above, the comparison circuit included in the peak hold circuit is also used for demodulation of the binary signal. Therefore, in this aspect, a switch is provided to switch from the peak hold circuit to the demodulation determination circuit. This switch is provided in the negative feedback loop of the comparison circuit. When the switch is turned off, the negative feedback loop of the comparison circuit is opened, and the function to follow the peak hold capacitor voltage to the peak voltage of the input signal is turned off, and the circuit that supplies the peak hold capacitor voltage to the comparison circuit Only the configuration is valid. At this time, if the voltage held in the peak hold capacitor can be used as a determination threshold value for demodulation, the comparison circuit compares the input differential signal with the determination threshold value and demodulates the binary signal. It can also be used as a demodulation decision circuit that outputs (H, L).

  (5) In another aspect of the demodulation circuit of the present invention, in a preparation period in which the power receiving apparatus does not perform the load modulation, the switch is turned on, and a peak hold voltage is generated in the peak hold capacitor. In the demodulation period, which is a period for demodulating the signal transmitted by the power receiving device, the switch is turned off, and the difference between the peak hold voltage as the determination threshold and the difference by the comparison circuit included in the demodulation determination circuit The signal is compared, and an amplitude detection signal of the difference signal is output from the comparison circuit.

  The operation of the demodulating circuit (4) is classified into a preparation period for obtaining a determination threshold and a demodulation period following the preparation period. The preparation period is, for example, a period before the secondary side performs communication by load modulation, and it is clear that load modulation by the secondary side is not performed. For example, a signal instructing communication preparation from the primary side to the secondary side is transmitted by frequency modulation, and the power receiving apparatus that receives the instruction performs load modulation until a predetermined period elapses from the timing of receiving the instruction. First, data communication by load modulation is started after the predetermined period has elapsed. In this case, the period from when the power transmission apparatus instructs communication preparation until the predetermined period elapses is a period during which it is clear that secondary side load modulation is not performed (for both the power transmission apparatus and the power reception apparatus). This period is the preparation period.

  In the preparation period, the switch is turned on, and the peak hold circuit performs a peak tracking operation by negative feedback control, and the peak voltage of the input differential signal is held in the peak hold capacitor. As described above, load modulation on the secondary side is not performed in the preparation period. This means that the state where the load modulation switch on the secondary side is turned off continues. It is assumed that when the secondary side transmits data “1”, the secondary side load modulation switch is turned on, and when transmitting data “0”, the secondary side load modulation switch is turned off. In this case, in the preparation period, the amplitude of the differential signal (sine wave) output from the differential circuit is the same as the amplitude when data “0” is transmitted, and the amplitude value (peak value) is It is held by the peak hold capacitor.

  When the predetermined period has elapsed, the secondary side starts transmitting communication packet data. On the other hand, the switch of the peak hold circuit provided in the primary-side demodulation circuit is turned off when the predetermined period elapses, and the peak hold circuit is switched to the demodulation determination circuit. As described above, the comparison circuit holds the peak voltage of the differential signal corresponding to the data “0” acquired in the preparation period, and the peak voltage is supplied to the comparison circuit as a demodulation determination threshold value. Yes. When the demodulation period starts, data in which “0” and “1” are mixed is transmitted from the secondary side to the primary side.

  When a differential signal having an amplitude corresponding to data “0” is input to the comparison circuit, the peak voltage coincides with the determination threshold (the voltage of the peak hold capacitor), and therefore L (for example, from the comparison circuit) When the comparison circuit operates between VDD and GND, the L level is, for example, a midpoint bias voltage (VDD / 2). On the other hand, when a differential signal having an amplitude corresponding to data “1” is input to the comparison circuit, the peak voltage is a voltage level higher than the determination threshold value (the voltage of the peak hold capacitor). H (for example, VDD) is output from the circuit. That is, a binary demodulated signal (H, L) indicating the determination result is obtained from the comparison circuit.

  In this way, by using the comparison circuit (and the peak hold capacitor) included in the peak hold circuit also for demodulating binary data (H, L), an independent demodulation determination circuit can be provided after the peak hold circuit. The demodulating circuit can be further simplified.

  (6) In another aspect of the demodulation circuit of the present invention, as the at least one resistor included in the integration circuit, a first resistor that forms a charge time constant circuit together with the peak hold capacitor, and a discharge together with the peak hold capacitor A second resistor that constitutes a time constant circuit and has a resistance value higher than the resistance value of the first resistor is provided.

  In this aspect, when the circuit configuration of (4) or (5) is adopted, a charging resistor (first resistor) and a discharging resistor (second resistor) are separately provided, and the resistance value of the discharging resistor is set as the charging resistor. Set to a sufficiently high value compared to the resistance value of the peak hold capacitor after the switch is turned off over time (the accumulated charge of the peak hold capacitor is discharged via the discharge resistor over time) ) And the fluctuation of the determination threshold voltage during the demodulation period is suppressed. The circuit configuration of this aspect corresponds to the first modification example (first application example) of the “demodulation circuit in which the peak hold circuit has a negative feedback path cutoff switch” described in (4) and (5) above. To do.

  That is, in the demodulation circuits shown in (4) and (5), as described above, the comparison circuit (and peak hold capacitor) included in the peak hold circuit is also used for demodulation of binary data (H, L). . During the preparation period, the voltage of the peak hold capacitor is required to change following the peak voltage of the input signal (that is, the integration circuit resistance is required to allow a certain amount of charge current to flow). During the demodulation period, the voltage of the peak hold capacitor is used as a judgment threshold, so that it remains constant regardless of the passage of time (that is, the integration circuit is not connected to the peak hold capacitor even after the switch is turned off). It is necessary to set the resistance value of the resistor as large as possible in order to minimize the off-leakage current because the constituent resistor remains connected and an off-leakage current flows through the resistor and the switch. Is done. Since these two requirements are contradictory requirements, it cannot be denied that a circuit design using one resistor is forced to compromise.

  Therefore, in this aspect, in the integrating circuit, the resistor for the charge time constant circuit (first resistor) and the resistor for the discharge time constant circuit (second resistor) are separated, and the first resistor (charge resistor) and the second resistor are separated. The respective resistance values of (discharge resistance) were optimized to enable optimum design of charge characteristics and discharge characteristics.

  Specifically, the first resistor (charging resistor) and the second resistor (discharging resistor) are provided in parallel between the comparison circuit and the peak hold capacitor, for example, and the first resistor (charging resistor) includes For example, a rectifying element (such as a PN junction diode) having a forward direction from the comparison circuit toward the peak hold circuit is provided. Since the rectifier element prevents the backflow of the charge accumulated in the peak hold capacitor, the first resistor functions as a charging resistor that allows only the charging current to flow.

  In the demodulation circuits shown in the above (4) and (5), the demodulation determination threshold is the same as the peak voltage of the differential signal (sine wave) at the time of data “0” transmission (that is, input voltage = determination). In the demodulation of the binary data “L” corresponding to the transmission period of the data “0” (demodulation for each drive clock), there is almost no noise margin. Therefore, in order to ensure accurate binary determination, it is important to maintain the voltage level of the determination threshold voltage held in the peak hold capacitor during the preparation period as it is during the demodulation period. In other words, if the voltage level of the determination threshold decreases beyond the allowable range due to discharge, when a differential signal (sine wave) corresponding to data “0” is input, it is normally L (for example, VDD / When 2) is output, H (for example, VDD) is output, and erroneous determination by the comparison circuit occurs. If an erroneous determination occurs, the demodulation accuracy of 1-bit data due to the correlation detection of H and L binary signals is reduced.

  According to this aspect, the discharge current can be made as small as possible by setting the resistance value of the second resistor (discharge resistor) to be sufficiently larger than the resistance value of the first resistor (charge resistor). (In other words, the discharge can be substantially ignored), so that the level of the determination threshold voltage during the demodulation period can be kept substantially constant. Therefore, the circuit configuration of this aspect contributes to the realization of high-precision demodulation of data.

  (7) In another aspect of the demodulation circuit of the present invention, the amplitude detection circuit includes an integration circuit including one resistor and a first peak hold capacitor, and a buffer connected to an output node of the first peak hold capacitor. Comparing the circuit, the second peak hold capacitor charged or discharged by the output of the buffer circuit, the difference signal output from the differential circuit and the voltage of the second peak hold capacitor; A peak hold circuit comprising: a comparison circuit having an output node connected to an input node of the integration circuit; and a switch provided between the output node of the buffer circuit and the second peak hold capacitor; When it is off, the second peak hold capacitor and the comparison circuit It operates as a demodulation determining circuit for outputting an amplitude detection signal of the signal.

  The circuit configuration of this aspect corresponds to the second modification example (second application example) of the “demodulation circuit in which the peak hold circuit has a negative feedback path cutoff switch” described in (4) and (5) above. To do. Similar to the demodulator circuit of (6), this aspect is also a circuit that aims to achieve both desired peak detection in the preparation period and prevention of variation in the determination threshold voltage in the demodulation period.

  However, in the circuit of this embodiment, two peak hold capacitors are used. That is, in the preparation period, a peak detection voltage corresponding to the peak voltage of the input signal is generated in each of the first peak hold capacitor and the second peak hold capacitor. Specifically, when a peak detection voltage (first peak detection voltage) is generated in the first peak hold capacitor, the peak detection is performed from the output node of the buffer circuit (amplifier circuit) connected to the first peak hold capacitor. An output voltage corresponding to (proportional to) the voltage level of the voltage is obtained, the second peak hold capacitor is charged by the output voltage of the buffer circuit (amplifier circuit), and the peak of the input signal is also applied to the second peak hold capacitor. A peak detection voltage (second peak detection voltage) corresponding to the voltage is generated. For example, the gains of the comparison circuit and the buffer circuit (amplifier circuit) and the capacities of the first and second peak hold capacitors are determined so that the voltage levels of the first peak detection voltage and the second peak detection voltage match. (However, it is not limited to this).

  The second peak hold capacitor is connected to one of the input nodes of the comparison circuit. A switch is provided in the negative feedback path connecting the output node of the amplifier circuit and the second peak hold capacitor. The resistance of the integrating circuit that determines the time constant for peak detection is connected only to the first peak hold capacitor. In the demodulation period, the holding voltage of the second peak hold capacitor is supplied to one input node of the comparison circuit as a determination threshold voltage for demodulation.

  In the demodulator circuit of this aspect, when the switch is turned off during the demodulation period, no resistance is connected to the second peak hold capacitor, the discharge path is completely cut off, and the temporal variation of the voltage level of the determination threshold is sufficiently suppressed. Since the determination threshold for demodulation is extremely stabilized, there is an advantage that sufficient data demodulation (detection) sensitivity can be realized.

  (8) In another aspect of the demodulation circuit of the present invention, in a preparation period in which the power receiving device does not perform the load modulation, the switch is turned on, and a peak hold voltage is applied to the second peak hold capacitor. In the data demodulating period, which is a period for demodulating the signal generated and transmitted by the power receiving device, the switch is turned off, whereby the first peak hold capacitor and the second peak hold capacitor are separated, The comparison circuit constituting the demodulation determination circuit compares the peak hold voltage of the second peak hold capacitor with the difference signal, and outputs an amplitude detection signal of the difference signal from the comparison circuit.

  In this aspect, the operation of the demodulation circuit (7) in the preparation period and the demodulation period is clarified. That is, the switch is turned on during the preparation period, and as described above, a peak detection voltage corresponding to the peak voltage of the input signal (difference signal) is generated in each of the first peak hold capacitor and the second peak hold capacitor. That is, after a certain amount of time has elapsed since the switch was turned on, each of the first peak hold capacitor and the second peak hold capacitor has a differential signal having an amplitude corresponding to the data “0”. Is maintained).

  Next, the switch is turned off during the demodulation period, thereby blocking the negative feedback path. Then, the peak hold circuit loses the peak detection function, and the voltage generated in each of the first peak hold capacitor and the second peak hold capacitor (that is, the peak voltage of the differential signal having an amplitude corresponding to data “0”). Is fixed, and the discharge path of the accumulated charge of the second peak hold capacitor is completely cut off. That is, since the integration resistor is not connected to the second peak hold capacitor, the discharge path of the second peak hold capacitor is completely cut off when the connection to the output node of the amplifier circuit is cut off. Therefore, the peak voltage generated in the second peak hold capacitor (the peak voltage of the differential signal having an amplitude corresponding to the data “0”) is an extremely stable determination threshold voltage for demodulation with little variation with time, The determination threshold voltage is supplied to the comparison circuit.

  Therefore, in the demodulation period, high-precision comparison determination is performed by the comparison circuit, and a plurality of binary signals of H and L transmitted for each primary coil AC drive signal (drive clock) transmitted from the secondary side. (In the case of packet communication data, 32 binary signals) are accurately demodulated. Therefore, correlation detection based on the obtained binary signal is also accurately performed, and high-precision demodulation of data (“1”, “0”) transmitted from the secondary side is realized.

  (9) In another aspect of the demodulation circuit of the present invention, the amplitude detection circuit includes a peak hold capacitor, a comparison circuit that compares a voltage at an output node of the peak hold capacitor and the difference signal, and the comparison circuit; A charge circuit provided between the peak hold capacitor and charging the peak hold capacitor based on an output signal of the comparison circuit; and provided between an output node of the peak hold capacitor and a reference potential. A discharge circuit that discharges a charge of a hold capacitor to the reference potential, and the discharge does not depend on a peak voltage of the differential signal input to the comparison circuit, and includes a peak hold circuit, An output signal is extracted as an amplitude detection signal of the difference signal.

  The demodulator circuit of this aspect has a peak hold circuit, and the peak hold circuit also serves as a demodulation determination circuit, and is common to the demodulator circuits (4) to (8) in this respect. However, the peak hold circuit in the demodulation circuit of this aspect does not have a switch that is turned on / off corresponding to each of the preparation period and the demodulation period, and therefore the voltage of the peak hold capacitor is always the peak of the input signal. Fluctuates following the voltage. However, in this aspect, the peak tracking time constant is set to a large value, the peak tracking capability is intentionally weakened, and the “peak tracking voltage generated in the peak hold circuit (the fluctuation that occurs in the peak tracking process up to the peak hold is changed). Voltage) ”is used as a decision threshold for demodulation.

  Generally, the determination threshold value used for amplitude detection using the comparison circuit is fixed, but in this embodiment, the variation of the determination threshold value is allowed. That is, the demodulation determination threshold (that is, the peak follow-up voltage generated in the peak hold capacitor) has a lower first peak voltage (referred to as Vpeak1) of the input signal (difference signal) and a higher second peak voltage. As long as it stays within the voltage range (Vpeak2), the peak follow-up voltage of the peak hold capacitor is used as a demodulation determination threshold, and the input signal (difference signal) H and L are accurately determined. (For example, if the determination threshold is the same as the second peak voltage Vpeak2, the result of comparison by the comparison circuit is that, for example, H (for example, VDD) is output normally, VDD / 2 (middle) Voltage) is output, resulting in an erroneous determination).

  From this point of view, in this embodiment, the peak tracking time constant is set to be slow, and the peak tracking voltage of the peak hold capacitor is the peak value during the signal demodulation period even if the peak voltage of the input signal changes. The tracking time constant of the peak hold circuit is designed so as not to reach. Specifically, for example, the voltage increase amount (voltage increase rate) of the peak hold capacitor per unit time during charging is set to a desired value, and similarly, the voltage of the peak hold capacitor per unit time during discharge The amount of decrease (voltage decrease rate) is set to a desired value, and the condition that the amount of voltage increase and the amount of voltage decrease of the peak-hode capacitor are substantially balanced (substantially the same) is satisfied. preferable.

  In this aspect, it is necessary to precisely set the peak tracking time constant of the peak hold circuit. Therefore, a charging circuit for charging the peak hold capacitor and a discharge circuit for discharging the peak hold capacitor are separately provided, and the charging circuit And design the characteristics of each discharge circuit optimally. At this time, when the discharge of the discharge circuit depends on the peak voltage (H, L) of the differential signal input to the comparison circuit (that is, when the discharge is at L and the discharge is stopped at H) ) Is determined depending on the probability of occurrence of H and L of the input signal, and the discharge amount per unit time cannot be designed accurately. In this embodiment, the discharge is input to the comparison circuit. The discharge circuit does not depend on the peak voltage of the difference signal.

  That is, when the voltage V of the peak hold capacitor is fixed, per unit time from the peak hold capacitor (for example, per time corresponding to n cycles of the primary clock, which is a period in which one bit of received data continues). It is preferable that the total discharge charge amount (Ik) is uniquely specified regardless of the peak level of the signal input to the comparison circuit.

  For example, in a period in which 1-bit data “0” is received, if charging by the charging circuit is stopped, the total discharge charge amount (Ik) is a period in which 1-bit “0” is received. The total discharge charge amount at. The discharge time constant (for example, the resistance value of the discharge resistor and the capacitance of the peak hold capacitor) is determined to be an appropriate value in consideration of the total discharge charge amount (Ik) during the period in which the 1-bit “0” is received. Thus, the voltage drop rate of the peak hold capacitor during the period in which 1-bit “0” is received can be set within a desired range.

  Similarly, when the total charge amount of the peak hold capacitor by the charging circuit in the period in which 1-bit “1” is received is Ib, (Ib−Ik) is in the period in which 1-bit “1” is received. If the charge time constant (for example, the resistance value of the charge resistor and the capacity of the peak hold capacitor) is determined to an appropriate value in consideration of the amount of charge, the amount of charge contributes to the voltage increase of the peak hold capacitor. The voltage increase rate of the peak hold capacitor during the period in which “1” is received can be set within a desired range, and the voltage increase rate and the voltage in the period in which 1 bit “0” is received By setting the descent rate to be approximately the same, it is possible to balance charging and discharging.

  In the demodulator circuit of this aspect, unlike the demodulator circuits (4) to (8) above, it is not necessary to distinguish between the preparation period for turning on the switch and the demodulation period for turning on the switch. That is, in the demodulation circuits of (4) to (8), it is necessary for the power receiving apparatus to recognize the preparation period (period in which the load modulation switch is not turned on) and the modulation period (period in which the load modulation switch is turned on / off). Similarly, the power transmission device also needs to recognize the preparation period (period in which the peak hold circuit switch is turned on) and the demodulation period (period in which the peak hold circuit switch is turned off), and thus the power transmission device and the power reception device. Therefore, for example, communication such as transmitting a preparation period instruction signal from the power transmission apparatus to the power reception apparatus may be necessary.

  On the other hand, since the demodulation circuit of this aspect does not need to distinguish between the preparation period and the demodulation period, there is an advantage that synchronization between the power transmission device and the power reception device is unnecessary, and the communication procedure is simplified. . For example, when it is desired to keep the voltage of the peak hold capacitor at the start of communication within a desired range, the secondary side performs dummy data of a predetermined bit having a predetermined value before transmission of the original communication data. May be transmitted to adjust the potential of the peak hold capacitor on the primary side, and then transmit the communication data. When communication is started, the determination threshold repeatedly rises and falls every cycle of the drive clock of the primary coil according to the difference signal H and L as the input signal, and reaches the peak of the input signal (slowly). At the same time, the comparison circuit performs a comparison determination using the peak tracking voltage as a determination threshold, and the amplitude determination signal (H and L binary signals for each driving clock: first signal) from the comparison circuit. Demodulated signal) is taken out.

  Moreover, the peak hold circuit of this aspect can also be used for the original use of holding the peak of the input signal (difference signal). Depending on the presence / absence of the secondary device, the resonance characteristic of the resonance circuit changes, and the level (amplitude) of the coil end voltage of the primary coil changes. Therefore, as described above, it is possible to detect the landing or removal of the power receiving device by detecting the change in the peak voltage, but there is almost no problem even if the detection is delayed by, for example, several seconds (secondary). For example, when it takes several tens of minutes to charge the battery of the side device, even if the landing detection is delayed for several seconds, there is no effect on the charging period of the battery charge, and similarly, the removal detection of the power receiving device is delayed by about several seconds However, the amount of power transmitted in the meantime is small, and the problem of increase in power consumption hardly arises). Therefore, in this aspect, even if the peak tracking time constant of the peak hold circuit is set larger than that of the conventional peak hold circuit so as to match the demodulation performance of the demodulation circuit, the power receiving device (or 2 including the power receiving device). If each event can be detected within the maximum permissible period in the detection of the landing and removal of the (secondary device), no particular problem occurs.

  (10) In another aspect of the demodulation circuit of the present invention, the charging circuit has a rectifying element and a charging resistor connected in series, and the discharging circuit has one end connected to the output node of the peak hold capacitor. A discharge switch that is periodically turned on to discharge the charge of the peak hold capacitor, and a discharge resistor connected between the other end of the discharge switch and the reference potential.

  In this aspect, it has been clarified that the discharge circuit includes a discharge switch and a discharge resistor, and the discharge switch is turned on periodically (that is, intermittently with periodicity). As described above, the discharge circuit discharges the accumulated charge of the peak hold capacitor regardless of the difference signal H and L input to the comparison circuit, and once the initial voltage V of the peak hold capacitor is determined, Is determined uniquely. Here, when the discharge circuit always discharges the accumulated charge of the peak hold capacitor, there is a possibility that a lot of charge tends to be discarded, and the power consumption of the peak hold circuit increases.

  Therefore, in this embodiment, a discharge switch is provided, and the discharge switch is intermittently turned on / off. By appropriately designing the ON / OFF cycle and the ON time, the discharge charge amount can be set to an appropriate value, and a discharge without waste is realized. The on / off control signal for periodically turning on / off the discharge switch can be obtained, for example, by dividing the difference signal by a frequency dividing circuit having an appropriate frequency dividing ratio. Design is easy.

  (11) In another aspect of the demodulation circuit of the present invention, the duration of 1-bit data transmitted from the power receiving device side is the n period of the AC drive signal of the primary coil (n is an integer of 2 or more) Further, when the power receiving apparatus transmits binary data by load modulation, the same value of m bits (m is an integer of 2 or more) is allowed to continue, and the peak hold capacitor A peak voltage corresponding to one value of the binary data generated at the first value is defined as a first peak hold voltage, corresponds to the other value of the binary data, and from the first peak hold voltage When the peak voltage of the higher voltage is the second peak hold voltage and the potential difference between the first peak hold voltage and the second peak hold voltage is ΔVpeak, the peak hold capacitor Of the charging circuit and the discharge circuit so that the time required for the voltage of the current to transition by ΔVpeak is equal to or longer than the time corresponding to the (m · n) period of the AC drive signal of the primary coil. Characteristics are set.

  In the present embodiment, an example of designing the peak tracking time constant in the demodulation circuits (10) and (11) above is defined. In this aspect, for example, at the time when data demodulation is started, the voltage of the peak hold capacitor is maintained at Vpeak1, which is the peak value of the differential signal corresponding to data “0”. It is assumed that m is an integer of 1 or more) continuous data “1” is received, and m bits of continuous data “1” is demodulated by the demodulation circuit. The peak voltage value of the difference signal corresponding to the data “1” is Vpeak2, and the potential difference between Vpeak1 and Vpeak2 is ΔVpeak. In this case, the voltage of the peak hold capacitor transits from Vpeak1 to Vpeak2 over time due to the peak follow function of the peak hold circuit included in the demodulation circuit.

  As described above, the period in which 1-bit transmission data from the secondary side continues is a period corresponding to n cycles of the drive clock of the primary coil. In the communication from the secondary side to the primary side, when continuous transmission of data of the same value of m bits is permitted, the time that the continuous data of the same value of m bits continues is the time of the drive clock of the primary coil This is a period corresponding to (m · n) period. Therefore, when the voltage of the peak hold capacitor (= determination threshold) reaches Vpeak2 within a period corresponding to the (m · n) cycle of the drive clock of the primary coil, the determination threshold is input to the H signal. Even though the reception period of the data “1” continuous with m bits has not ended, the correct voltage “1” cannot be demodulated thereafter, and a reception error occurs.

  Therefore, in this example, the peak follow-up time required for the voltage of the peak hold capacitor (= determination threshold) to transition from Vpeak1 to Vpeak2 (that is, the time required for the transition of ΔVpeak) is (m N) If set to be longer than the cycle, the voltage of the peak hold capacitor does not reach Vpeak2 and stays between Vpeak1 and Vpeak2 within the period of demodulating “1” that is m bits continuous. Therefore, the comparison circuit can accurately determine the H and L of the input signal by using the peak tracking voltage of the peak hold capacitor as the determination threshold, and therefore, the m bit transmitted from the secondary side. Continuous "1" can be demodulated reliably.

  In the above example, the case where the voltage of the peak hold capacitor follows from Vpeak1 to Vpeak2 has been described, but the same applies to the case where the voltage of the peak hold capacitor follows from Vpeak2 to Vpeak1. That is, at the time when data demodulation is started, the voltage of the peak hold capacitor is maintained at Vpeak2, which is the peak value of the differential signal corresponding to the data “1”, and in this state, m bits (m is 1 or more) The same applies to the case where continuous data “0” is received and m bits of continuous data “0” is demodulated by the demodulation circuit. That is, also in this case, each of the characteristics of the charging circuit and the discharging circuit is set so that the time required for the voltage of the peak hold capacitor to change by ΔVpeak is equal to or longer than the (m · n) period of the driving clock of the primary coil. It is sufficient to set the characteristics.

  (12) In another aspect of the demodulation circuit of the present invention, the duration of 1-bit data transmitted from the power receiving device side is the n period of the AC drive signal of the primary coil (n is an integer of 2 or more) Further, when the power receiving apparatus transmits binary data by load modulation, the same value of m bits (m is an integer of 2 or more) is allowed to continue, and the peak hold capacitor A peak voltage corresponding to one value of the binary data generated at the first value is defined as a first peak hold voltage, corresponds to the other value of the binary data, and from the first peak hold voltage Is set to a second peak hold voltage, a potential difference between the first peak hold voltage and the second peak hold voltage is ΔVPeak, The smaller of the potential difference between the voltage difference between the voltage of the peak hold capacitor and the first peak hold voltage and the voltage difference between the peak hold capacitor voltage and the second peak hold voltage at the start of the demodulation ( When ΔVpeak / p) (where p is a real number larger than 2), the time required for the voltage of the peak hold capacitor to change by (ΔVpeak / p) is the AC drive signal of the primary coil. Of the primary coil when the voltage of the peak hold capacitor is 1 bit of one value of the binary data. When the amount of voltage drop that falls during a period corresponding to the period and 1 bit of the other value of the binary data is received, the primary coil is received. A voltage increase amount increases in a period corresponding to n cycles of such balance, characteristic properties and the discharge circuit of the charging circuit is set.

  In the above aspect (11), it is assumed that m-bit continuous data “1” (or “0”) is received. However, in actuality, m-bit continuous data “1” and m bits are received in the demodulation period. It is desirable that both continuous data “0” can be detected. Therefore, for example, at the start of demodulation, the voltage (determination threshold) of the peak hold capacitor is the midpoint voltage of Vpeak1 and Vpeak2 (that is, (Vpeak1 + Vpeak2) / 2). ) Is often set near. When the potential difference between Vpeak1 and Vpeak2 is ΔVpeak and the voltage of the peak hold capacitor (= determination threshold) is set to the midpoint voltage (Vpeak1 + Vpeak2) / 2), the variation margin of the determination threshold with respect to Vpeak1 (variable allowable range) and Vpeak2 The fluctuation margin (tolerable fluctuation range) for both is (ΔVpeak / 2). In the above aspect (11), the variation margin (variable allowable range) of the determination threshold is set to ΔVpeak. Therefore, in the above example of this aspect, the variation margin (allowable variation range) of the determination threshold is ½ that in the case of (11) above.

  That is, in this example, the time required for the peak hold capacitor voltage (= determination threshold) to change by (ΔVpeak / 2) is longer than the (m · n) period of the drive clock of the primary coil. When set to “1”, both “1” continuous with m bits and “0” continuous with m bits can be properly received.

  In the above example, the initial setting voltage of the peak hold capacitor voltage (= determination threshold) is set to the midpoint voltage. However, the present invention is not limited to this. More generally, the smaller one of the potential difference between the peak hold capacitor voltage and Vpeak1 at the start of demodulation and the potential difference between the peak hold capacitor voltage and Vpeak2 at the start of demodulation (ΔVpeak / p). When (where p is a real number greater than 2), (ΔVpeak / p) is the minimum allowable fluctuation range of the voltage of the peak hold capacitor. Therefore, the time required for the peak hold capacitor voltage to transition by (ΔVpeak / p) may be set to be equal to or longer than the (m · n) period of the drive clock of the primary coil.

  As a result, the slope of the straight line indicating the rate of voltage rise during charging of the peak hold capacitor or the slope of the straight line indicating the rate of voltage drop during discharging is determined. That is, the amount of voltage rise or voltage drop of the peak hold capacitor voltage per period during which 1-bit data continues (period corresponding to n cycles of the drive clock of the primary coil) is determined.

  Next, the circuit characteristics of the charging circuit and the discharging circuit may be determined so that the amount of voltage increase and the amount of voltage drop per period in which 1-bit data continues are balanced (same). In other words, since the voltage of the peak hold capacitor fluctuates following the peak of the input signal, when data “1” is received, the voltage of the peak hold capacitor rises and data “0” is received. When it is, the voltage of the peak hold capacitor drops. Assuming that data “1” and data “0” are alternately received, the voltage of the peak hold capacitor repeatedly rises and falls, but the voltage rise amount and the voltage fall amount in the 1-bit data period are the same. If so, the voltage level of the peak hold capacitor does not change before and after receiving the series of data.

  In most cases, the occurrence ratio of “1” and “0” included in the received data is almost the same over a long period of time (or the transmission data on the secondary side is intentionally so. Therefore, if the voltage increase amount and the voltage decrease amount in the 1-bit data period are set to be the same as described above, the voltage level of the peak hold capacitor is set to the demodulation period. , The probability of staying in an intermediate voltage range between Vpeak1 and Vpeak2 is extremely high, and thus the reliability of the demodulated binary signal can be ensured. If the amount of voltage rise and the amount of voltage drop are not balanced, even when data “1” and “0” are alternately received, the determination threshold (that is, the voltage of the peak hold capacitor) is changed over time. Shifting to either Vpeak1 or Vpeak2 side, the fluctuation margin decreases accordingly, eventually reaching the peak value, at which point the voltage of the peak hold capacitor is demodulated Cannot be used as the determination threshold.

  Therefore, as described above, when the data “1” is received, the voltage increase amount of the peak hold capacitor in the duration of the data “1” (a period corresponding to the n period of the driving clock of the primary coil), and the data “ When receiving “0”, the voltage drop amount of the peak hold capacitor in the duration of data “0” (a period corresponding to the n period of the drive clock of the primary coil) is balanced (substantially the same). Further, it is preferable to set the characteristics of the charging circuit and the characteristics of the discharging circuit.

  Thus, it is preferable to set the characteristics of the charging circuit and the discharging circuit so as to satisfy both of the above two conditions. That is, the peak follow-up time required for the peak hold capacitor voltage (= determination threshold) to transition (ΔVpeak / p) is set to be not less than the (m · n) period of the drive clock of the primary coil, and 1 The voltage increase amount and the voltage decrease amount of the voltage (= determination threshold) of the peak hold capacitor in the bit duration (period corresponding to the n period of the drive clock of the primary coil) are balanced (that is, approximately the same, Each characteristic of the charging circuit and the discharging circuit is set (determined) so as to be substantially the same or the same.

  (13) In another aspect of the demodulation circuit of the present invention, the peak hold circuit is also used for detecting at least one of removal and landing of a power receiving device including the power receiving device, and at least one of the removal and landing At the time of detection, the characteristics of the charging circuit and the characteristics of the discharging circuit are set so as to satisfy the peak tracking characteristics required for the peak hold circuit.

In the above aspects (11) and (12), allowable “delay of peak tracking” was examined from the viewpoint of signal demodulation. In this aspect, when the demodulation circuit according to aspects (11) and (12) is also used for detecting at least one of removal and landing of the power receiving apparatus (or the secondary device including the power receiving apparatus)
Clarified that the “peak tracking speed” is necessary so that it can handle removal detection or landing detection of the power receiving device (secondary equipment including the power receiving device). That is, in this aspect, the “peak tracking speed” that can handle removal detection or landing detection of a power receiving device (secondary device including the power receiving device) and “peak tracking tracking” for reliable signal demodulation. The characteristics of the charging circuit and the characteristics of the discharging circuit are determined so as to satisfy both “slowness”.

  (14) Another aspect of the demodulation circuit of the present invention further includes an output circuit including a correlation detector that detects the correlation of the amplitude detection signal of the differential signal output from the comparison circuit.

  As described in the above aspect (3), “signal demodulation” includes demodulation of binary signals of H and L synchronized with the AC drive clock (drive clock) of the primary coil (first demodulation process). And correlation detection (for example, detection of continuity or detection of both continuity and periodicity) of a plurality of binary signals (H, L) continuous on the time axis obtained by the first demodulation process. There are “1” and “0” data demodulation (second demodulation processing). The demodulation circuit of the present invention may perform only the first demodulation process and output the amplitude detection signal for each cycle of the drive clock, and subsequently execute the second demodulation process to correlate the binary signals. Detection may be performed to output an amplitude detection signal (that is, demodulated data) for each period in which 1-bit data continues (a period corresponding to n cycles of the drive clock).

  In this aspect, the demodulation circuit can further include a correlation detector (corresponding to the second demodulation processing circuit) that detects the correlation between the H and L binary signals obtained by the first demodulation processing. Clarified.

  (15) One aspect of the power transmission control device of the present invention is provided in the power transmission device of a contactless power transmission system that electromagnetically couples a primary coil and a secondary coil to transmit power from the power transmission device to the power reception device. A power transmission control device for controlling the operation of the power transmission device, comprising: the demodulation circuit; and a power transmission side control unit for controlling the operation of the power transmission device and to which an output signal of the demodulation circuit is input. Including.

  As described above, the demodulation circuit of the present invention employs a novel method of detecting the difference between the coil end signals obtained from both ends of the capacitor connected to the primary coil, and utilizes the in-phase component canceling action. Thus, for example, even when the power receiving device (secondary side) performs constant communication (power supply non-stop transmission), the signal transmitted from the secondary side can be demodulated with high accuracy. Further, for example, a signal transmitted from the secondary side can be demodulated with high accuracy by using a circuit having a simple configuration such as a peak hold circuit, and the circuit scale can be suppressed. Further, for example, by using the comparison circuit of the peak hold circuit as the demodulation determination circuit, the exclusive area of the circuit is further reduced, and the power consumption is also reduced. In addition, for example, by using the peak hold circuit for signal removal, power removal device removal detection and landing detection, integration of the detection circuit is promoted, further reducing the area occupied by the circuit and reducing power consumption. Further reduction is possible.

  Therefore, when such a demodulation circuit is mounted on a power transmission control device (for example, an IC), downsizing and low power consumption of the power transmission control device are realized.

  (16) One aspect of the power transmission device of the present invention is the power transmission device of a non-contact power transmission system that electromagnetically couples a primary coil and a secondary coil to transmit power from the power transmission device to the power reception device. A power transmission unit having a drive unit that AC drives the primary coil, and the power transmission control device.

  The power transmission device on which the power transmission control device of the present invention is mounted can obtain the same effects as the power transmission control device described above (effects such as power saving and space saving). In addition, when realizing multi-transmission capable of transmitting power to a plurality of secondary devices having different power ratings with a single power transmission device, a circuit disposed in a location close to the primary coil of the power transmission device, In some cases, a high voltage circuit (or medium voltage circuit) having a certain level of resistance against a high voltage may be required. In this case, a level shifter that converts the high voltage obtained from the primary coil to an appropriate level. Etc. are also required, and the circuit tends to be enlarged. On the other hand, the power transmission device of the present invention has a simplified internal circuit (in particular, a communication system circuit including a demodulation circuit), and is excellent in power saving and space saving. Therefore, it is easy to realize a power transmission device that supports multi-power transmission.

  (17) One aspect of the electronic apparatus of the present invention includes the above power transmission device and a primary coil driven by the power transmission device.

  Since the power transmission device of the present invention is small and power-saving, it can be easily mounted on a primary-side electronic device (for example, a charging stand (cradle)). Similarly, the electronic device of the present invention also enjoys the effect of being small and saving power. In addition, as described above, a multifunctional primary electronic device that supports multi-power transmission can be realized.

  (18) According to one aspect of the data demodulation method of the present invention, the primary coil and the secondary coil are electromagnetically coupled to transmit power from the power transmission apparatus to the power reception apparatus, and the power reception apparatus transmits the power to the load to be fed. A non-contact power transmission system for supplying power, wherein the power transmission device demodulates data transmitted by load modulation from the power reception device, wherein the load modulation in the power reception device is applied to the load to be fed. The load modulation is performed without stopping power supply, and the load modulation is performed in synchronization with the AC drive signal of the primary coil, and the duration of 1-bit data transmitted from the power receiving device side is: The first signal from one end of the resonant capacitor connected to the primary coil and the resonant core when the period corresponds to n periods (n is an integer of 2 or more) of the AC drive signal of the primary coil. A differential signal with the second signal from the other end of the denser is generated, and the amplitude of the differential signal is detected for each cycle of the AC drive signal of the primary coil to obtain the amplitude detection signal of the differential signal Then, the correlation of the amplitude detection signal of the differential signal in a period corresponding to the n period of the AC drive signal is detected, and 1-bit data is demodulated every n periods of the AC drive signal.

  In this aspect, an example of the procedure until the data transmitted by the power receiving apparatus by load modulation is demodulated in the power transmitting apparatus has been clarified. That is, data transmission from the secondary side is executed without stopping power supply to the load to be supplied (always communication). The power transmission device adopts a new method of detecting the difference between the coil end signals obtained from both ends of the capacitor connected to the primary coil, and uses a canceling action of the in-phase component to increase the power by a simple circuit. Perform precision demodulation.

  First, the amplitude information of the differential signal output from the differential circuit is detected for each cycle of the drive clock of the primary coil by the first demodulation process, and a binary (H, L) amplitude detection signal is obtained. . Next, by the correlation detection (second demodulation process) based on the binary (H, L) amplitude detection signal, the difference is made in units of n periods (period in which 1-bit data continues) of the drive clock of the primary coil. The amplitude information of the signal is detected, and demodulated 1-bit data is obtained. As a result, the data transmitted by the power receiving device by load modulation can be demodulated efficiently and reliably on the power transmitting device side.

1A to 1C are diagrams for explaining a technique (prior art) for extracting a coil end voltage of a primary coil from one end of a resonance capacitor. FIGS. 2A to 2C illustrate the configuration and circuit operation of the first embodiment of the demodulation circuit of the present invention using a technique for extracting the coil end voltage of the primary coil from both ends of the resonance capacitor. Illustration for 3A and 3B are diagrams illustrating an example of a demodulation method of the demodulation circuit illustrated in FIG. 4A and 4B are diagrams for explaining an overall configuration example of a contactless power transmission system and an outline of communication between a power transmission device and a power reception device. The figure which shows an example of the specific structure of a power transmission apparatus 6A to 6C illustrate the outline of a second embodiment of the demodulation circuit according to the present invention (example in which a switch is provided in the peak hold circuit and the peak hold circuit is switched to the demodulation determination circuit). Illustration to do 7A to 7C are diagrams for explaining a specific circuit configuration and circuit operation of the second embodiment of the demodulation circuit of the present invention. The figure which shows the structure of 3rd Example (The 1st modification (Example which isolate | separates charging resistance and discharge resistance) about 2nd Example) of the demodulation circuit of this invention. FIGS. 9A and 9B show the configuration of a fourth embodiment of the demodulation circuit of the present invention (second modification of the second embodiment (an example using two peak hold capacitors)). Figure Signal waveform diagram showing operation of demodulation circuit shown in FIG. FIGS. 11A and 11B are diagrams for explaining the configuration and operation principle of the fifth embodiment of the demodulation circuit according to the present invention (an example in which the peak tracking voltage is used as a demodulation determination threshold). 12A to 12C are diagrams for explaining a design example of peak tracking characteristics of the peak hold circuit shown in FIG. Signal waveform diagram for explaining the specific operation of the peak hold circuit in the fifth embodiment shown in FIG. Signal waveform diagram for explaining the specific operation of the demodulator circuit of the fifth embodiment shown in FIG. FIGS. 15A and 15B are diagrams for explaining a first preferred design example of peak tracking characteristics of the peak hold circuit in the fifth embodiment. FIGS. 16A and 16B are diagrams for explaining a second preferred design example of the peak tracking characteristic of the peak hold circuit in the fifth embodiment. The figure for demonstrating the preferable 3rd design example of the peak tracking characteristic of the peak hold circuit in 5th Example. The figure for demonstrating the 4th design example with the preferable peak tracking characteristic of the peak hold circuit in 5th Example. The figure for demonstrating an example of operation | movement of the primary side electronic device (cradle) and the non-contact electric power transmission system which mount the power transmission apparatus containing the demodulation circuit of this invention

  Next, embodiments of the present invention will be described with reference to the drawings. Note that the present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are as means for solving the present invention. It is not always essential.

(First embodiment)
FIG. 1A to FIG. 1C are diagrams for explaining a technique (conventional technique) for extracting a coil end voltage of a primary coil from one end of a resonance capacitor. As shown in FIG. 1A, the power transmission unit 12 AC drives the primary coil L1 based on an AC drive signal (drive clock) DRCK. A resonant capacitor CP1 is connected to the primary coil L1. The coil end signal CSG is taken out from the node N1 on the primary coil L1 side of the resonance capacitor CP1. The coil end signal CSG is a waveform in which a drive signal DRV output from a power transmission driver (not shown in FIG. 1A) included in the power transmission unit 12 and a resonance waveform (for example, a sine wave) of a resonance circuit are combined. (See FIGS. 1B and 1C). In a state where the primary coil and the secondary coil are coupled, the resonance circuit is configured by the resonance capacitor CP1, the leakage inductance of the primary coil L1 and the secondary coil L2, the impedance connected to the secondary coil L1, and the like. Is done.

  When the load is low and when the load is high, the resonance characteristic of the resonance circuit changes and the amplitude (and some phase) of the resonance waveform changes. Therefore, when the load state on the secondary side is a low load state, the coil end signal CSG has a waveform as shown in FIG. 1B, for example, while the load state on the secondary side becomes a high load state. The end signal CSG has a waveform as shown in FIG. As can be seen from FIGS. 1B and 1C, the signal amplitude (peak value) also changes, but the waveform itself also changes. This change in the waveform itself becomes noise at the time of peak detection, and noise generated with the AC drive of the primary coil L1 also causes a decrease in S / N of peak detection. In addition, the primary coil and the resonance capacitor CP1 are external components, and the DC bias point of the coil end signal CSG varies due to variations in characteristics of the external components and variations in the power supply voltage. Make it difficult to optimize the decision threshold. In addition, when the secondary side always communicates (communication of signals without stopping power supply to the load to be fed), the state fluctuation of the load to be fed directly affects the voltage level of the communication signal, etc. give.

  Therefore, compared with the case where the secondary side intermittently stops the power supply to the load to be supplied and performs communication during the stop period, the S / N of the signal transmitted by the constant communication tends to decrease, It is difficult for conventional techniques to perform demodulation of signals by constant communication with high accuracy by peak detection.

(Example of circuit configuration of demodulation circuit)
Therefore, in this embodiment, a new demodulation method (amplitude detection method) is employed in which a differential signal is generated using a differential circuit based on the difference between two coil end signals and the amplitude of the difference signal is detected. . FIGS. 2A to 2C illustrate the configuration and circuit operation of the first embodiment of the demodulation circuit of the present invention using a technique for extracting the coil end voltage of the primary coil from both ends of the resonance capacitor. FIG.

  As shown in FIG. 2A, the demodulation circuit DM of the present embodiment demodulates a signal transmitted by the power receiving apparatus (secondary side) by load modulation. The demodulation circuit DM has a differential circuit (here, a differential amplifier circuit) SAMP and an amplitude detection circuit AMT. The amplitude detection circuit AMT includes a peak hold circuit PH, a demodulation determination circuit DET, and an output circuit QTC. The output circuit QTC has a low-pass filter (LPF) 3 as a correlation detector and a level shift circuit (LS) 5.

  Further, a load modulation unit 46 is provided in the power receiving device (secondary side). The load modulation unit 46 includes a load modulation transistor TB3 and a load resistor RB3. One end of the load resistor RB3 is connected to a common connection node N3 of the resistors RB1 and RB2 connected between both ends of the secondary coil L2. The load modulation transistor TB3 is controlled to be turned on / off by a load modulation control signal Qmod. The period for transmitting 1-bit communication packet data “1” or “0” (1-bit data length) is, for example, a period corresponding to 32 cycles of the AC drive signal (drive clock) DRCK of the primary coil (that is, When the period of the drive clock DRCK is Tdr, this is a period corresponding to 32 Tdr), and the time corresponding to 2 bits is the modulation period Tmod.

  The longer period for transmitting 1-bit data is that there is a certain delay time from the start of load modulation until the signal level of the coil end voltage of the primary coil L1 changes by a predetermined level. This is because of consideration. In addition to communication packets (communication data: for example, a full charge notification save frame), data sent from the secondary side includes a periodic authentication pattern for detecting foreign object insertion. Periodic authentication is a process of periodically transmitting a signal of a predetermined pattern from the secondary side, and periodically receiving and detecting the pattern on the primary side. When the pattern that should be detected is not detected, it can be determined that a foreign object has been inserted between the primary coil L1 and the secondary coil L2. In order to be able to distinguish between “communication packet data” and “periodic authentication pattern data”, the data length of 1 bit constituting the periodic authentication pattern is when the period of the drive clock DRCK of the primary coil is Tdr. , And a length corresponding to 16 periods (16 Tdr).

  Further, when the node on the primary coil L1 side of the resonant capacitor CP1 connected to the primary coil L1 is N1, and the node on the power transmission driver Dr2 side is N2, the first coil end signal is extracted from the node N1, A second coil end signal is extracted from the node N2. Since each of the first coil end signal and the second coil end signal is usually at a considerably high voltage level, the voltage level is set by a voltage dividing resistor included in a waveform monitor circuit (not shown in FIG. 2A). Further, for example, after the DC component is removed by a DC cut capacitor (not shown in FIG. 2A), it is input to the non-inverting terminal and the inverting terminal of the differential circuit (differential amplifier circuit) SAMP. Is done. The signal input to the non-inverting terminal of the differential amplifier circuit SAMP is the “first signal CSG” from the node N1 of the primary coil L1, and the signal input to the inverting terminal of the differential amplifier circuit SAMP is 1 This is the “second signal DRV” from the node N2 of the next coil L1.

  As described above, the first signal CSG is a combined waveform of the resonance waveform and the drive signal (square wave), and the second signal DRV is the drive signal (square wave) itself output from the power transmission driver Dr2.

  When the difference between the first signal CSG (sinusoidal wave + DRV) and the second signal (DRV) is taken, the component of the drive signal DRV (square wave) included in both the first signal and the second signal is an in-phase component. Therefore, only the resonance waveform (sine wave) included in the first signal is extracted. This is the difference signal Aout. The amplitude of the difference signal Aout varies according to the on / off state of the secondary side load modulation transistor TB3. The differential signal Aout functions as an amplitude-modulated carrier (communication carrier) whose amplitude changes in accordance with on / off of the load transistor TB3 on the secondary side, and the waveform itself is on / off of the load modulation transistor TB3. (Strictly speaking, the phase of the resonance waveform (sine wave) also varies slightly according to the on / off state of the secondary side load modulation transistor TB3. However, the waveform is synthesized as in the prior art. Therefore, it can be said that the waveform deformation as shown in FIGS. 1B and 1C does not occur).

  Further, differential amplification is a method of extracting a difference component (only relative change) between two input signals. Even if the DC level of each of the two input signals is shifted, each of the two input signals is shifted. If the shift amount is the same, the fluctuation is not a problem. Therefore, the problem of “adjustment of the reference voltage for comparison judgment is difficult because the coil end voltage level also varies due to variations in power supply voltage, coil inductance, etc.,” which has been considered as a problem in the past. The Specifically, for example, if a DC cut capacitor is provided in front of the differential amplifier circuit SAMP and the DC bias circuit sets the DC bias of the input node and output node of the differential amplifier circuit SAMP independently, The DC level of the coil end voltage of the primary coil L1 can be optimized.

  Further, even if noise due to the drive signal of the primary coil L1 or the counter electromotive force of the coil is generated, the noise is superimposed on both the first signal CSG and the second signal DRV, so that the differential amplifier circuit SAMP Is canceled by the canceling action of the in-phase component of the differential signal Aout and the difference signal Aout output from the differential amplifier circuit SAMP is not affected.

  Therefore, according to the demodulation circuit DM on the power transmission device side shown in FIG. 2A, all the problems that have been the conventional problems are solved, and the determination of H and L is made surely only focusing on the amplitude of the difference signal Aout. Can be done. Therefore, highly accurate signal demodulation is realized based on the amplitude (peak value) of the differential signal Aout. That is, if the demodulation circuit DM shown in FIG. 2A is used, highly accurate signal demodulation can be performed by the amplitude detection method (peak detection method). Therefore, the demodulation circuit DM illustrated in FIG. 2A can also be applied to a contactless power system in which the above-described constant communication (power supply non-stop communication) is performed.

  An amplitude detection circuit AMT is provided after the differential amplifier circuit SAMP. The amplitude detection circuit AMT compares the output signal of the peak hold circuit PH and the output signal of the peak hold circuit PH with the determination threshold value Vth, and outputs a binary detection signal (first demodulated signal DXdmod) of H and L. A determination circuit DET and an output circuit QTC are included. The output circuit QTC includes a low-pass filter (LPF) 3 that functions as a correlation detector that detects a correlation on the time axis of the first demodulated signal DXdmod, and a level shift circuit (LS) 5. A second demodulated signal DQdmod is obtained from the output circuit QTC. The second demodulated signal DQdmod is demodulated data (“1” or “0”).

  That is, the demodulation determination circuit DET detects the peak value (amplitude value) of the difference signal Aout (the period of which coincides with the period Tdr of the drive clock DRCK of the primary coil) for each period, and the demodulation determination circuit The DET detects the magnitude of the amplitude for each period of the difference signal Aout using the determination threshold Vth, and outputs a binary (H, L) detection signal DXdmod (first demodulated signal) (FIG. 2 (B)). As shown in FIG. 2B, when the received data changes to “1”, “0”, “1”, “0”, and the received data is communication packet data. H and L appear alternately every 32 cycles of the drive clock DRCK of the primary coil, and when the received data is periodic authentication data, H and L appear alternately every 16 cycles. . At this stage, it is not detected whether the received data is “1” or “0”.

  A low-pass filter (LPF) 3 as a correlation detector included in the output circuit QTC detects a time correlation of a binary (H, L) detection signal DXdmod (first demodulated signal). In other words, if the change of the detection signal DXdmod (first demodulated signal) from L to H depends on the on / off of the load modulation transistor TB3 on the secondary side, H or L is not one-shot. A plurality of times should appear continuously (continuity), and the appearance period should be 32 or 16 periods of the drive clock (periodicity). By integrating the detection signal DXdmod (first demodulated signal) with the low-pass filter (LPF) 3, for example, a voltage waveform (integrated waveform) as shown in FIG. 2C is obtained. As shown in FIG. 2C, if H is continuous, the output voltage level (time average value) of the LPF 3 exceeds a predetermined value, and if L is continuous, the output voltage level (time) of the LPF 3 The average value) does not exceed a predetermined value, and therefore, it is possible to discriminate between data “1” and “0”. In addition, when the duration of 1 bit “1” or “0” is a time corresponding to 32 clocks, the 1 bit is communication packet data, and when 1 bit is equivalent to 16 clocks, the 1 bit is periodically authenticated. It can be determined that the pattern data is for use. The output signal of the LPF 3 is leveled down by the level shift circuit (LS) 5 and adjusted to a voltage level suitable for the logic circuit, and then output. This output signal is the second demodulated signal (DQdmod), and this second demodulated signal DQdmod is demodulated data ("1" or "0").

  In FIG. 2A, the low-pass filter (LPF) 3 is used as the correlation detection circuit (analog correlation detector), but a digital correlation detector can also be used. The digital correlation detector can be constituted by, for example, a register that temporarily stores a binary (H, L) detection signal and a determination circuit that reads the register value and performs data determination. The determination circuit determines the value when the same value is detected continuously j times (j is an integer of 2 or more, for example, j = 7), and then the duration of 1 bit is 32 of the drive clock DRCK. If it is a time corresponding to the clock, it is determined as communication packet data, and if it is a time corresponding to 16 clocks, it is determined that the data is for periodic authentication.

  In FIG. 2A, the output circuit QTC that outputs demodulated data (“1”, “0”) is not necessarily provided. That is, the binary (H, L) detection signal (first demodulated signal) DXdmod output from the demodulation determination circuit DET is directly supplied to, for example, the power transmission side control unit (for example, CPU), and the received data itself The power transmission side control unit may perform the demodulation.

  In summary, the demodulation determination circuit DET in FIG. 2A detects the amplitude of the difference signal Aout for each cycle of the drive clock, and when the output circuit QTC is provided in the subsequent stage, the output circuit The QTC detects the amplitude of the difference signal Aout in units of 1-bit duration, and both are common in that the amplitude of the difference signal is detected. Both the first demodulated signal (H and L binary signal) DXdmod and the second demodulated signal (demodulated data) DQdmod can be said to be amplitude detection signals of the differential signal Aout, which is the input signal of the demodulating circuit DM (thus, output) It is clear that the circuit QTC can also be a component of the amplitude detection circuit AMT). However, the unit time of amplitude detection is different between the first demodulation process and the second demodulation process.

  Further, in the demodulation circuit DM of FIG. 2A, the peak hold circuit PH and the demodulation determination circuit DET are depicted as separate circuits, but this is an example (the most basic circuit configuration example). It is shown and is not limited to this example. For example, the comparison circuit in the peak hold circuit PH can also be used as a demodulation determination circuit (an example of this will be described later).

  Further, the amplitude detection circuit DM shown in FIG. 2A can also be used to detect removal of the power receiving device (secondary device including the power receiving device) and landing (primary coil and secondary coil). The resonance characteristics of the resonance circuit change depending on the presence or absence of coupling, and the voltage level of the coil end voltage of the primary coil varies). Therefore, by adopting the circuit configuration shown in FIG. 2 (A), a single demodulation circuit (detection circuit) DM enables high-precision demodulation of a signal transmitted by the secondary side using load modulation, and a power receiving device (power receiving device). Both of the removal of the secondary side device to which the device is attached and the detection of the landing can be realized. In this case, further simplification of the detection circuit on the primary side, further reduction of the occupied area of the circuit, Low power consumption can be realized. Further, the demodulation circuit DM shown in FIG. 2A is a non-contact power corresponding to multi-power transmission that transmits power to a plurality of power receiving devices (secondary devices) having different power ratings in one primary device. Contributes to the realization of transmission systems.

(Basic demodulation method)
3A and 3B are diagrams illustrating an example of a demodulation method of the demodulation circuit illustrated in FIG. As shown in FIG. 3A, the determination threshold used in the demodulation determination circuit DET is properly used depending on the purpose of demodulation. The first threshold value (Vth1) is a data determination threshold value, the second threshold value (Vth2) is a removal detection threshold value, and the third threshold value (Vth3) is a landing detection threshold value. At the time of signal demodulation, the demodulated data DQdmod is output from the amplitude detection circuit AMT, and at the time of detection of removal of the power receiving device (secondary device), a removal detection signal is output. A signal is output.

  As shown in FIG. 3B, the peak voltage of the differential signal Aout output from the differential amplifier circuit SAMP when data “0” is received (at the time of small amplitude) is Vpeak1, and when data “1” is received ( When the peak voltage at the time of large amplitude is Vpeak2, the determination threshold value Vth1 (Vth2, Vth3) used in the demodulation determination circuit DET is set so as to satisfy the relationship of Vpeak1 <Vth1 (Vth2, Vth3) <Vpeak2. Is done.

(Variation of demodulation method)
The above demodulation method is an example, and there are various variations in the demodulation method used in the present invention. For example, the comparison circuit included in the peak detection circuit PH is also used as the demodulation determination circuit DET, and the peak hold circuit PH is switched to the demodulation determination circuit DET by turning off the switch provided in the peak hold circuit PH. Method of demodulating a signal (second embodiment), modification and application example of second embodiment (third embodiment (example in which charging resistance and discharging resistance are provided separately)), fourth embodiment (2 peak hold capacitors) And an example in which the time constant of the peak follow-up voltage VC1 in the peak hold circuit PH is optimized, and the peak follow-up voltage is used as it is as a determination threshold for demodulation (fifth embodiment). .

(Configuration and operation of contactless power transmission system)
Next, the configuration and communication method of the contactless power transmission system will be described with reference to FIGS. 4 and 5. FIG. 4A and FIG. 4B are diagrams for explaining an overall configuration example of a contactless power transmission system and an outline of communication between a power transmission device and a power reception device. As illustrated in FIG. 4A, frequency modulation is used for data communication from the power transmission device 10 to the power reception device 40, and load modulation is used for data communication from the power reception device 40 to the power transmission device 10. In the power transmission device 10, the first signal CSG and the second signal DRV extracted from both ends of the resonance capacitor CP <b> 1 are input to the differential circuit (differential amplifier circuit) SAMP via the waveform monitor circuit 14. In addition to the load modulation unit 46, the power receiving device 40 controls power supply (supply of the supply current IL) to the rectification unit 43, the smoothing capacitor CB1, and a load (for example, secondary battery: battery) 90 to be supplied. Power supply control unit 48, frequency detection circuit 60 (having DRCK regeneration unit 61), and power reception side control unit 52. The DRCK reproducing unit 61 in the frequency detection circuit 60 is based on a resonance component (sine wave) included in a common connection point of the resistors RB1 and RB2 connected in series between both ends of the secondary coil L2. The drive clock DRCK of the coil is reproduced. In FIG. 4A, the regenerated drive clock is denoted as DRCK (RE). The power receiving side control unit 52 measures the 1-bit duration using the reproduced drive clock DRCK (RE) as a reference clock, and corresponds to the 1-bit duration (32 clocks in the case of communication packet transmission). The load modulation transistor TB3 is turned on / off in units of time (a time corresponding to 16 clocks in the case of periodic authentication pattern data). As described above, data “1” is transmitted while the load modulation transistor TB3 is on, and data “0” is transmitted when the load modulation transistor TB3 is off. Note that “1” and “0” are meanings for the coil end voltage of the primary coil L1 that changes depending on on / off of the load modulation transistor TB3, and the above “1” and “0” can be interchanged. .

  FIG. 4B shows an example of transmission and reception of communication packet data. The load modulation period Tmod corresponds to a 2-bit transmission period (2-bit duration). The load modulation transistor TB3 is turned on / off every time corresponding to 32 drive clocks (this is a 1-bit duration), whereby “0” and “1” are received from the power receiving device 40. It is transmitted alternately. The differential signal (sine wave) Aout output from the differential amplifier circuit SAMP provided in the power transmission device 10 is output in synchronization with the drive clock DRCK of the primary coil. That is, during the 1-bit duration, the difference signal Aout for 32 cycles is output. The amplitude of the difference signal Aout increases or decreases in accordance with the on / off state of the load modulation transistor TB3. That is, the differential signal Aout serves as an amplitude-modulated communication carrier.

(Configuration of power transmission device)
FIG. 5 is a diagram illustrating an example of a specific configuration of the power transmission device. The power transmission unit 12 includes a power supply circuit 101 (having a power supply unit 103 and a smoothing capacitor 105), a power transmission driver DR1 (configured by NMOS transistors M1 and M2), and a power transmission driver DR2 (NMOS transistors M3 and M4). And). CZ1 to CZ4 are zero volt switch capacitors for increasing the switching efficiency. Each of the NMOS transistors M1 to M4 is controlled by on / off drive control signals TG1 to TG4 output from the drive control circuit 107. The operation of the drive control circuit 107 is controlled by the power transmission side control unit (power transmission side control circuit) 22.

  The waveform monitor circuit 14 includes DC cut capacitors 111a and 111b and resistors RXa and RXb. The power transmission control device 20 is configured by, for example, one IC (integrated circuit device). The power transmission control device 20 includes the demodulation circuit DM of the present invention and a power transmission side control unit 22 that controls the overall operation of the power transmission device 10.

  A differential circuit (differential amplifier circuit) SAMP (reference numeral 15) included in the demodulation circuit DM includes an operational amplifier AMP1, a feedback resistor RYA, an output resistor Ryb, capacitors 113a and 113b and a resistor Ryc constituting a high-pass filter. And a voltage source Vref for setting a DC bias voltage of the differential amplifier circuit SAMP (15). The reason why the high-pass filter is provided at the output of the differential amplifier circuit SAMP (15) is to feed back the noise superimposed on the output signal of the operational amplifier AMP1 to the inverting terminal. For example, when an instantaneous noise is generated by the operation of the internal circuit of the operational amplifier AMP1, and the noise is superimposed on the output signal of the operational amplifier AMP1, the noise is fed back to the non-inverting terminal via the feedback resistor Rya, Similarly, it is fed back to the inverting terminal via a high pass filter. Therefore, noise is removed by the common-mode noise canceling action of the differential amplifier circuit SAMP (15). Therefore, the differential amplifier circuit SAMP (15) outputs a differential signal Aout having a good S / N with an amplitude corresponding to on / off of the load modulation transistor TB3.

  As described above, the amplitude detection circuit AMT included in the demodulation circuit DM includes the peak hold circuit PH and the demodulation determination circuit DET. For example, the peak follow-up voltage (or peak hold voltage) Vpeak of the peak hold circuit PH, the second demodulated signal (demodulated data) DQdmod, and the like are supplied to the power transmission side control unit 22. The power transmission side control unit 22 interprets the received data and the like, and controls the operation of the power transmission device 10 based on the interpretation.

(Second Embodiment)
In the present embodiment, the comparison circuit (and peak hold capacitor) included in the peak hold circuit PH is also used for demodulation of the binary detection signal (H, L). This eliminates the need to provide the demodulation determination circuit DET separately from the peak hold circuit PH, thereby further simplifying the demodulation circuit DM.

  6A to 6C illustrate the outline of a second embodiment of the demodulation circuit according to the present invention (example in which a switch is provided in the peak hold circuit and the peak hold circuit is switched to the demodulation determination circuit). It is a figure for doing. 6A is a diagram for explaining the operation of the amplitude detection circuit DM in the preparation period, and FIG. 6B is a diagram for explaining the operation of the amplitude detection circuit DM in the demodulation period. FIG. 6C is a diagram for explaining the relationship between the two peak values (Vpeak1 and Vpeak2) of the difference signal Aout and the determination threshold for demodulation (Vth1).

  For example, as shown in FIG. 6A, the peak hold circuit PH basically includes an integration circuit (timer) including a peak hold capacitor C1 and a resistor (integral resistor) R1 in the negative feedback loop of the comparison circuit COM. (Constant circuit) 2 is provided, and the voltage of the peak hold capacitor C1 is made to coincide with the peak voltage (Vpeak1 or Vpeak2) of the differential signal Aout input to the comparison circuit COM by negative feedback control, and the peak voltage (Vpeak1 or Vpeak2) is held. And necessarily includes a comparison circuit COM.

  Here, if the comparison circuit COM is also used for demodulating a binary signal, the circuit can be simplified. Therefore, as shown in FIG. 6A, a switch SW1 is provided to switch from the peak hold circuit PH to the demodulation determination circuit DET. The switch SW1 is provided in the negative feedback loop of the comparison circuit COM. When the switch SW1 is turned off, the negative feedback loop of the comparison circuit COM is opened, the function of detecting the peak voltage of the differential signal Aout as an input signal is turned off, and the voltage of the peak hold capacitor C1 is supplied to the comparison circuit COM. Only the circuit configuration is valid. At this time, if the peak hold voltage held in the peak hold capacitor C1 can be used as the demodulation determination threshold value Vth1, the comparison circuit COM compares the input difference signal Aout with the determination threshold value Vth1. Therefore, it can also be used as a demodulation determination circuit DET that outputs a demodulated binary detection signal (H, L) (first demodulation signal DXdmod).

  Therefore, in the present embodiment, in the preparation period shown in FIG. 6A, the switch SW1 is turned on to obtain the lower peak value Vpeak1 of the difference signal Aout. Then, in the demodulation period shown in FIG. 6B, the switch SW1 is turned off to turn off the peak tracking function of the peak hold circuit PH, and the obtained Vpeak1 is used as the demodulation determination threshold value Vth1, and the difference signal Aout Amplitude judgment is executed.

  That is, in the demodulation period shown in FIG. 6B, when the peak value of the input difference signal Aout is Vpeak1, the voltage level is the same as the determination threshold Vth1 (= Vpeak1). When operating between the first power supply potential VDD and the second power supply potential GND (ground), the comparison circuit COM outputs a midpoint bias potential (VDD / 2 = L). On the other hand, when the peak value of the input difference signal Aout is Vpeak2, since the peak voltage of the input signal Aout is higher than the determination threshold Vth1 (= Vpeak1), VDD (= H) is output from the comparison circuit COM. The Therefore, a binary (H, L) detection signal (first demodulated signal DXdmod) is obtained.

  However, in order to realize such demodulation, for example, it is necessary that both the power transmission device 10 and the power reception device 10 recognize the preparation period and the demodulation period, and an operation synchronized between the both is executed. (That is, during the preparation period, it is necessary to ensure that load modulation by the power receiving apparatus is not executed, and when the switch SW1 is turned off and the demodulation period is started, the power receiving apparatus 40 has an appropriate timing. It is necessary to start communication by load modulation of In other words, the preparation period is, for example, a period before the power receiving device 40 performs communication by load modulation, and it is clear that load modulation by the power receiving device 40 is not performed. For example, a signal instructing communication preparation is transmitted from the power transmitting apparatus 10 to the power receiving apparatus 40 by frequency modulation, and the power receiving apparatus 40 that receives the instruction performs load modulation until a predetermined period elapses from the timing of receiving the instruction. Instead, data communication by load modulation is started after the predetermined period has elapsed. In this case, it is clear that secondary-side load modulation is not performed (for both the power transmission device 10 and the power reception device 40) during the period from when the power transmission device 10 instructs communication preparation until the predetermined period elapses. It is a period, and this period can be used as a preparation period. (This example is an example, and the present invention is not limited to this. For example, if a predetermined period is set as a preparation period from the time when landing of a power receiving device is detected) You may decide).

  As shown in FIG. 6A, in the preparation period, the control signal EHOLD becomes an active level and the switch SW1 is turned on. The amplitude of the input differential signal Aout is an amplitude value without load modulation (that is, an amplitude value corresponding to data “0”. An integrating circuit (low-pass filter LPF) is formed by the integrating resistor R1 and the peak hold capacitor C1. The time constant of the integration circuit determines the peak tracking time constant of the peak hold circuit PH, and the voltage of the peak hold capacitor C1 becomes the peak voltage Vpeak1 after a predetermined time has elapsed. The output circuit QTC has a low-pass filter (LPF) 3 that functions as a correlation detector, and a level shift circuit LS 5. In the preparation period, the output circuit QTC outputs a first output from the output circuit QTC. 2 The demodulated signal DQdmod is invalid.

  Next, as shown in FIG. 6B, in the demodulation period, the control signal EHOLD becomes an inactive level and the switch SW1 is turned off. The peak hold capacitor C1 and the comparison circuit COM constitute a demodulation determination circuit DET. The comparison circuit COM compares the determination threshold value (Vpeak1) with the peak value (Vpeak1 or Vpeak2) of the input difference signal Aout. If the peak value of the difference signal Aout is Vpeak1, the determination threshold value Vth1 is equal to the peak value of the difference signal Aout, so that the output of the comparison circuit COM is L level (for example, the comparison circuit COM is between VDD and GND). When operating, for example, VDD / 2), and if the peak value of the difference signal Aout is Vpeak2, the output of the comparison circuit COM becomes H level (for example, VDD). In this way, the binary detection signal (first demodulated signal) DXdmod of H and L is obtained. The output circuit QTC performs correlation detection based on the binary detection signal (first demodulated signal) DXdmod, and further performs a level shift as necessary. As a result, the second demodulated signal DQdmod (that is, demodulated data “1” or “0”) is obtained.

  In this demodulation method, since the comparison circuit in the peak hold circuit PH can be used as a determination circuit for demodulation, the circuit can be made compact. However, since both the power transmission device 10 and the power reception device 40 need to recognize the preparation period and the demodulation period, synchronization between the power transmission device 10 and the power reception device 40 is necessary. Further, in this demodulation method, since the comparison target signal (Vpeak1 which is the amplitude of Aout of the difference signal) and the determination threshold Vth1 (= Vpeak1) are at the same level in the L determination by the comparison circuit COM, Regarding the L determination, there is almost no noise margin. Therefore, in the demodulation period, it is preferable to suppress a change with time in the voltage level of the determination threshold value Vth1 as much as possible to prevent erroneous determination, and to suppress a decrease in detection accuracy during correlation detection.

  FIGS. 7A to 7C are diagrams for explaining a specific circuit configuration and circuit operation of the second embodiment of the demodulation circuit of the present invention. As shown in FIG. 7A, the switch SW1 can be configured with, for example, a tristate buffer (or a transfer switch or the like). Further, the low-pass filter LPF2 as a correlation detector included in the output circuit QTC includes a resistor R2 and a capacitor C2. The level shift circuit (LS) 5 includes, for example, a variable gain amplifier gm using a voltage controlled current source and an output stabilization capacitor C3.

  As shown in FIG. 7B, time t1 to t2 is a preparation period (Vpeak1 acquisition period), and time t2 to t3 is a demodulation period (comparison period between Vpeak1 as the determination threshold Vth1 and the difference signal Aout). It is. As a result, as shown in FIG. 7C, data of “0” or “1” is demodulated every predetermined time (here, every time corresponding to 32 cycles of the drive clock of the primary coil). (That is, the second demodulated signal DQdmod is output).

(Third embodiment)
In the demodulation system of the second embodiment (demodulation circuit of FIG. 7), the voltage of the peak hold capacitor C1 is required to detect the peak voltage of the input signal Aout during the preparation period, and the peak hold capacitor during the demodulation period. Since the voltage of C1 (Vpeak1) is used as the determination threshold value Vth1, it is required to be kept constant regardless of the passage of time.

  These two requirements are contradictory requirements, and in fact, it cannot be denied that the integration circuit design using one resistor R1 is forced to compromise. That is, in the demodulation circuit DM of FIG. 7, even after the switch SW1 is turned off, the resistor R1 constituting the integrating circuit (LPF) 2 remains connected to the peak hold capacitor C1, and the resistor R1 and the switch SW1 are passed through. In order to minimize the off-leakage current, it is required to set the resistance value of the resistor R1 as large as possible. This requirement is a request to ensure a desired peak tracking performance. Is a conflicting request.

  Therefore, in the present embodiment, the charge resistance and the discharge resistance are separated and the resistance value of the discharge resistance is set to a sufficiently high value. This will be described with reference to FIG. FIG. 8 is a diagram showing the configuration of a demodulator circuit according to a third embodiment (a first modification of the second embodiment (an example in which a charge resistor and a discharge resistor are separated)).

  As shown in FIG. 8, in the integration circuit (LPF) 2, a charging resistor (first resistor) R10 and a discharging resistor (second resistor) R20 are provided separately, and the resistance value of the discharging resistor R20 is the charging resistor R10. It is set sufficiently higher than the resistance value. A diode D1, which is a rectifying element, is connected between the switch SW1 and the charging resistor (first resistor) R10. The diode D1 is a rectifying element whose forward direction is from the switch SW1 toward the charging resistor (first resistor) R10. Therefore, the discharge current from the peak hold capacitor C1 is blocked by the diode D1. Therefore, only the charging current Ixa for charging the peak hold capacitor C1 flows through the charging resistor (first resistor) R10.

  When the H output of the comparison circuit COM is at the VDD level, the forward voltage of the diode D1 is VF, and the resistance value of the charging resistor (first resistor) R10 is expressed as R10, the charging current Ixa is (VDD−VF). / R10. In the preparation period, the voltage of the peak hold capacitor C1 becomes the peak value Vpeak1 of the difference signal Aout corresponding to the data “0”. In the demodulation period, the discharge current Ixb flowing through the discharge resistor R20 is determined by Vpeak1 / R20 when the resistance value of the discharge resistor R20 is expressed as R20. If the resistance value of the discharge resistor R20 is set sufficiently high, the discharge current Ixb can be suppressed (however, the amount of discharge current necessary for peak tracking needs to be ensured).

  As described above, in the present embodiment, the change with time of the holding voltage of the peak hold capacitor C1 after the switch SW1 is turned off (the accumulated charge of the peak hold capacitor C1 is discharged via the discharge resistor R20 as time passes). ) Can be reduced to reduce the variation of the determination threshold voltage (Vth1 = Vpeak1) during the demodulation period. Therefore, erroneous determination by the comparison circuit COM is reduced, and as a result, a decrease in accuracy of correlation detection of the low-pass filter (LPF) 3 as a correlation detector included in the output circuit QTC is suppressed.

(Fourth embodiment)
In the present embodiment, as in the demodulation circuits of the second and third embodiments described above, it is possible to achieve both desired peak detection during the preparation period and prevention of fluctuations in the determination threshold voltage during the demodulation period. However, in the demodulation circuit of this embodiment, two peak hold capacitors are used. That is, during the preparation period, a voltage that follows the peak voltage of the input signal is generated in each of the first peak hold capacitor and the second peak hold capacitor. FIGS. 9A and 9B show the configuration of a fourth embodiment of the demodulation circuit of the present invention (second modification of the second embodiment (an example using two peak hold capacitors)). FIG.

(Circuit configuration)
The peak hold circuit PH included in the amplitude detection circuit AMT includes an integration circuit (LPF) 2 including one resistor R1 and a first peak hold capacitor C1, and a buffer circuit connected to the output node of the first peak hold capacitor C1. 9 (specifically, it can be constituted by a differential amplifier circuit, a voltage follower, or the like, here a differential amplifier circuit), and the second peak hold that is charged or discharged by the output of the buffer circuit 9 The capacitor C4, the differential signal Aout output from the differential amplifier circuit (SAMP) 15 and the voltage of the second peak hold capacitor C4 are compared, and the output node N10 is connected to the input node N11 of the integrating circuit (LPF) 2. Comparison circuit COM connected, output node N12 of buffer circuit 9 and second peak hold Having a switch SW2 provided between the condensers C4. When the switch SW2 is off, the second peak hold capacitor C4 and the comparison circuit COM operate as a demodulation determination circuit DET that outputs an amplitude detection signal of the difference signal Aout. The resistor R1 of the integrating circuit 2 that determines the time constant for peak tracking is connected only to the first peak hold capacitor C1.

  (Basic operation)

  As shown in FIG. 9B, in the preparation period (time t1 to t2), the switch SW2 is turned on, the peak detection operation (peak holding operation) of the peak hold circuit PH is executed, and the first peak hold capacitor When both C1 and the second peak hold capacitor C4 are charged and a predetermined time elapses from the time t1, the first peak hold voltage Vpeak1a is generated in the first peak capacitor C1, and the second peak hold voltage is applied to the second peak hold capacitor C4. Vpeak 1b is generated. As a result, the peak voltage value of the amplitude of the differential signal Aout when there is no load modulation (that is, the peak voltage value of the amplitude of the differential signal Aout corresponding to the data “0”) is acquired.

  Next, in the demodulation period (time t2 to t3), the switch SW2 is turned off, and the first peak hold capacitor C1 and the second peak hold capacitor C4 are disconnected. The second peak hold voltage Vpeak1b of the second peak hold capacitor C4 becomes the demodulation determination threshold value Vth1. The comparison circuit COM compares the demodulation determination threshold value Vth1 (second peak hold voltage Vpeak1b) with the difference signal Aout as an input signal, and compares the binary (H, L) amplitude detection signal (first demodulated signal) DXdmod. Is output.

(Specific operation)
In the preparation period, the switch SW2 is turned on by a control signal (ON / OFF control signal) EHOLD output from the power transmission side control unit 22. When the first peak hold voltage Vpeak1a is generated in the first peak hold capacitor C1, it corresponds to the peak hold voltage Vpeak1a from the output node N12 of the buffer circuit (amplifier circuit) 9 connected to the first peak hold capacitor C1. A (proportional) output voltage is obtained, and the second peak hold capacitor C4 is charged by the output voltage of the buffer circuit (amplifier circuit) 9, and the second peak hold capacitor C4 also receives the difference signal Aout as an input signal. A second peak hold voltage Vpeak1b corresponding to the peak is generated. For example, the gains of the comparison circuit COM and the buffer circuit (amplifier circuit), the first and second peak hold capacitors (C1, C1) are set so that the voltage levels of the first peak hold voltage Vpeak1a and the second peak hold voltage Vpeak1b match. Each capacity of C4) is determined (but not limited to this). For example, when the capacitance values of the first and second peak hold capacitors (C1, C4) are set to be the same, and the gains of the comparison circuit COM and the buffer circuit (amplifier circuit) 9 are set to be the same, the first peak hold voltage is set. The voltage levels of Vpeak1a and the second peak hold voltage Vpeak2 can be made the same.

  In the demodulation period, the switch SW2 is turned off and the negative feedback path is interrupted. Accordingly, the first peak hold capacitor C1 and the second peak hold capacitor C4 are separated. The peak hold circuit PH loses the peak detection function, and has a second peak hold voltage Vpeak1b (that is, an amplitude corresponding to data “0”) generated in each of the first peak hold capacitor C1 and the second peak hold capacitor C4. The peak voltage of the difference signal is fixed.

  The comparison circuit COM uses the second peak hold voltage Vpeak1b of the second peak hold capacitor C4 as a determination threshold value (Vth1) to determine the amplitude of the difference signal Aout. As a result, a binary (H, L) amplitude detection signal (first demodulated signal) DXdmod is obtained.

(effect)
In the demodulation circuit DM of the present embodiment, in the peak hold circuit PH, the resistor R1 of the integration circuit 2 that determines the time constant for peak detection is connected only to the first peak hold capacitor C1. Therefore, when the switch SW2 is turned off during the demodulation period, the discharge path for the second peak hold capacitor C4 is completely cut off. Therefore, the temporal fluctuation of the voltage level of the second peak hold voltage Vpeak1b (= demodulation judgment threshold Vth1) held in the second peak hold capacitor C4 is sufficiently suppressed. Therefore, the determination threshold value Vth1 for demodulation is extremely stable, and thus high data demodulation (detection) sensitivity (for example, sensitivity twice or more that of the circuit of the third embodiment) can be realized.

(Waveform diagram showing demodulation operation)
FIG. 10 is a signal waveform diagram showing an operation of the demodulation circuit shown in FIG. As shown in the uppermost part of FIG. 10, the comparison circuit COM performs the magnitude determination of the amplitude of the difference signal Aout using the second peak hold voltage Vpeak1b of the second peak hold capacitor C4 as the determination threshold (Vth1). The As a result, as shown in the second stage from the top in FIG. 10, a binary (H, L) amplitude detection signal (first demodulated signal) DXdmod is obtained.

  Next, as shown in the third stage from the top in FIG. 10, a correlation detection signal is output from a low-pass filter (LPF) 3 serving as a correlation detector included in the output circuit QTC. Then, as shown in the lowermost stage of FIG. 10, demodulated data “1” and “0” (second demodulated signal DQdmod) are output from the output circuit QTC. In this way, the data transmitted from the secondary side is accurately demodulated.

(Fifth embodiment)
In the demodulation circuits of the second to fourth embodiments, it is assumed that the determination threshold (Vth1) is fixed during the demodulation period. However, in the demodulation circuit dm of this embodiment, the signal is demodulated. The voltage level of the determination threshold value (Vth1) is allowed to vary. Instead, the peak tracking capability of the peak hold circuit PH is set to be considerably weaker than that of the normal circuit design so that the variation of the determination threshold value (Vth1) falls within a desired range. In this way, even if the peak follow-up voltage VC1 (= determination threshold Vth1) of the peak hold capacitor C1 fluctuates due to the peak follow-up, unless the same value data is continuously input exceeding the allowable number, the peak The peak follow-up voltage VC1 (= determination threshold Vth1) of the hold capacitor C1 remains between the smaller peak value Vpeak1 and the larger peak value Vpeak2 of the difference signal Aout, and thus the difference signal Aout. Can be determined.

(Circuit configuration and principle)
FIGS. 11A and 11B are diagrams for explaining the configuration and operating principle of a fifth embodiment of the demodulation circuit according to the present invention (an example in which a peak tracking voltage is used as a demodulation determination threshold). . The amplitude detection circuit AMT included in the demodulation circuit DM shown in FIG. 11A includes a peak hold capacitor C1, a comparison circuit COM that compares the voltage of the output node N13 of the peak hold capacitor C1 with the difference signal Aout, A charging circuit CCH (including a diode DS as a rectifying element and a resistor R1) provided between the circuit COM and the peak hold capacitor C1 and charging the peak hold capacitor C1 based on an output signal of the comparison circuit COM; Provided between the output node N13 of the hold capacitor C1 and the reference potential (GND, etc.), the charge of the peak hold capacitor C1 is discharged to the reference potential (GND, etc.), and the discharge is input to the comparison circuit COM. Discharge circuit DCH independent of the peak voltage of differential signal Aout Discharging a switch SWP and including) a discharge resistor R9, the on / off control signal VASW discharge switches SWP, a frequency divider 19 for generating a differential signal Aout by dividing the. An amplitude detection signal (first demodulated signal) DXdmod of the difference signal Aout is extracted from the output node N10 of the comparison circuit COM.

  The charging circuit CCH (including the diode DS and the charging resistor R1) is a circuit for charging the peak hold capacitor C1, and its charging time constant is determined by the charging time constant circuit CHT (the charging resistor R1 and the peak hold capacitor C1). (That is, the charging current amount is determined by the resistance value of the charging resistor R1, and the rate of voltage increase during charging is determined by the charging current amount and the capacitance value of the peak hold capacitor C1). In addition, the discharge time constant of the discharge circuit DCH (including the discharge switch SWP and the discharge resistor R9) is determined by a discharge time constant circuit (configured by the discharge switch SWP, the discharge resistor R9, and the peak hold capacitor C1). In other words, the discharge current amount per unit time is determined by the period when the discharge switch SWP is turned on, the ON time, and the resistance value of the discharge resistor R9, and the unit time during discharge is determined from the discharge current amount and the capacitance value of the peak hold capacitor C1. The voltage drop rate per unit is determined).

  The peak hold circuit PH of this embodiment also serves as a demodulation determination circuit (DET). In this respect, the peak hold circuit PH is common to the demodulation circuits of the second to fourth embodiments. The PH does not have a switch that is turned on / off corresponding to each of the preparation period and the demodulation period, and therefore the voltage of the peak hold capacitor C1 always follows the peak voltage (Vpeak1 or Vpeak2) of the input signal Aout. And fluctuate. However, in this embodiment, the peak tracking time constant is set to be large and the peak tracking capability is intentionally weakened, and the “peak tracking” generated in the peak hold circuit PH as shown in FIG. The voltage (fluctuating voltage generated in the peak following process until reaching the peak hold) VC1 ”is used as the determination threshold value Vth1 for demodulation.

  Generally, the determination threshold value Vth1 used for amplitude detection using the comparison circuit COM is fixed, but in this embodiment, variation of the determination threshold value is allowed. That is, the demodulation determination threshold value Vth1 (the peak follow-up voltage VC1 generated in the peak hold capacitor) has a lower first peak voltage (Vpeak1) and a higher second peak voltage (Vpeak1) of the differential signal Aout as an input signal. As long as it stays within the voltage range between Vpeak 2), the peak follow voltage VC1 of the peak hold capacitor C1 is used as a determination threshold for demodulation, and the H and L of the input signal (difference signal) Aout are accurately determined. (For example, if the determination threshold VC1 is the same as the second peak voltage Vpeak2, as a result of comparison by the comparison circuit COM, for example, H (for example, VDD) is normally output. (Middle voltage) is output, resulting in erroneous determination).

  From this point of view, in this embodiment, the peak follow-up characteristic is set to be slow, and even if the peak voltage of the input signal Aout changes, the peak follow-up voltage of the peak hold capacitor is “within the period during which the signal is demodulated”. The peak tracking time constant of the peak hold circuit PH is designed so that does not reach the peak value.

  In the demodulation circuit DM of the present embodiment, unlike the demodulation circuits of the second to fourth embodiments, it is not necessary to distinguish between the preparation period for turning on the switch and the demodulation period for turning on the switch. That is, in the demodulation circuit in the above-described embodiment, the power receiving device 40 needs to recognize the preparation period (period in which the load modulation switch is not turned on) and the modulation period (period in which the load modulation switch is turned on / off). In addition, the power transmission apparatus 10 also needs to recognize the preparation period (period in which the peak hold circuit switch is turned on) and the demodulation period (period in which the peak hold circuit switch is turned off). For this reason, for example, as described above, communication such as transmitting a preparation period instruction signal from the power transmission apparatus to the power reception apparatus may be required.

  On the other hand, the demodulation circuit DM of the present embodiment does not need to distinguish between the preparation period and the demodulation period, so that synchronization between the power transmission apparatus and the power reception apparatus is unnecessary, and the communication procedure is simplified. There is. For example, when it is desired to keep the voltage of the peak hold capacitor C1 at the start of communication within a desired range, the secondary side performs a predetermined bit dummy having a predetermined value before transmission of the original communication data. For example, the initial potential of the primary-side peak hold capacitor C1 may be adjusted by transmitting data, and then communication data may be transmitted. When communication is started, the determination threshold repeatedly rises and falls every cycle of the drive clock of the primary coil according to the H and L of the difference signal Aout that is an input signal, and reaches the peak of the input signal (slowly At the same time, the comparison circuit COM performs a comparison determination using the peak tracking voltage VC1 as the determination threshold value Vth1, and the amplitude detection signal (first demodulated signal) DXdmod is extracted from the comparison circuit COM. become.

  Moreover, the peak hold circuit PH of this embodiment can also be used for the original use of holding the peak of the input signal (difference signal) Aout. Depending on the presence / absence of the secondary device, the resonance characteristic of the resonance circuit changes, and the level (amplitude) of the coil end voltage of the primary coil changes. Therefore, as described above, it is possible to detect the landing or removal of the power receiving device by detecting the change in the peak voltage, but there is almost no problem even if the detection is delayed by, for example, several seconds (secondary). For example, when it takes several tens of minutes to charge the battery of the side device, even if the landing detection is delayed for about several seconds, it does not affect the charging period of the battery charge, and similarly, the removal detection of the power receiving device is about several seconds. Even if it is delayed, the amount of power transmitted during that period is small, and there is almost no problem of increase in power consumption. Therefore, in this embodiment, even if the peak tracking time constant of the peak hold circuit PH is set larger than that of the conventional peak hold circuit so as to match the demodulation performance of the demodulation circuit DM, If each event can be detected within the maximum permissible period in removal detection, no particular problem occurs.

(Explanation of the balance between the charging circuit and discharging circuit)
Since the peak follow-up voltage VC1 is also a determination threshold value (Vth1) for demodulation, for example, when data “1” and “0” are received alternately and continuously, the peak tracking voltage VC1 is balanced so as to remain at a predetermined potential. It is better to design a circuit with good quality. That is, even if data “1” and “0” are alternately received continuously, if the peak tracking voltage VC1 shifts to either Vpeak1 or Vpeak2, it will eventually peak. The voltage VC1 reaches Vpeak1 or Vpeak2, and at that time, the peak follow-up voltage VC1 cannot be used as a demodulation determination threshold (Vth1). Therefore, when designing the charging circuit CCH and the discharging circuit DCH, for example, the voltage increase amount (voltage increase rate) of the peak hold capacitor C1 per unit time at the time of charging is set to a desired value. The voltage decrease amount (voltage decrease rate) of the peak hold capacitor C1 per unit time is set to a desired value, and the voltage increase amount and the voltage decrease amount of the peak hold capacitor are balanced (that is, the same) It is preferable that a certain condition (including substantially the same and substantially the same) is satisfied.

  Therefore, it is necessary to precisely set the peak follow time constant of the peak hold circuit PH. Therefore, a charging circuit CCH for charging the peak hold capacitor C1 and a discharge circuit DCH for discharging the peak hold capacitor C1 are separately provided. The characteristics of the charging circuit CCH and the discharging circuit DCH are optimally designed. In addition, the discharge characteristics of the discharge circuit DCH are designed not to depend on the peak voltage of the differential signal input to the comparison circuit COM. If the discharge of the discharge circuit DCH depends on the peak voltage (Vpeak1, Vpeak2) of the differential signal Aout input to the comparison circuit COM (that is, the discharge is discharged when the output of the comparison circuit COM is L, and is H Assuming that the discharge stops), the presence or absence of discharge is determined according to the appearance probability of H and L of the output signal of the comparison circuit COM, and the discharge amount per unit time cannot be designed accurately. Therefore, in this embodiment, the discharge characteristic by the discharge circuit DCH is designed so as not to depend on the peak voltage of the differential signal input to the comparison circuit COM.

  12A to 12C are diagrams for explaining a design example of the peak tracking characteristic of the peak hold circuit shown in FIG. In FIG. 12A, a total charge amount Ib and a total discharge charge amount Ik are defined. In other words, in the discharge circuit DCH used in the present embodiment, for example, when the voltage (V) of the peak hold capacitor C1 is fixed, one bit of received data continues from the peak hold capacitor C1 per unit time (for example, Let Ik be the total discharge charge amount during the period of n cycles of the primary clock (per hour corresponding to n = 32 in this case). The total discharge charge amount Ik is uniquely specified regardless of the peak level of the difference signal Aout input to the comparison circuit COM.

  For example, during a period in which 1-bit data “0” is received (a period corresponding to 32 clocks of the primary coil drive clock), the output of the comparison circuit COM becomes L (for example, GND), and the diode DS is reverse-biased. Thus, charging of the peak hold capacitor C1 by the charging circuit CCH is stopped. Therefore, the total discharge charge amount Ik described above is the total discharge charge amount during the period in which 1-bit “0” is received.

  If the discharge time constant (the resistance value of the discharge resistor R9 and the capacitance value C1 of the peak hold capacitor C1) is determined to an appropriate value in consideration of the total discharge charge amount Ik during the period in which 1-bit “0” is received. The voltage drop amount ΔV2 (see FIG. 12B) of the peak hold capacitor C1 during a period in which 1-bit “0” is received can be set to a value within a desired range, for example, Ik / C1 = ΔV2 is established.

  Similarly, when the total charge amount of the peak hold capacitor C1 by the charging circuit CCH during the period in which 1-bit “1” is received is Ib, (Ib−Ik) is 1-bit “1” is received. The charge amount contributes to the voltage rise of the peak hold capacitor C1 during the period, and the charge time constant (for example, the resistance value of the charge resistor R1 and the capacitance C1 of the peak hold capacitor C1) is set to an appropriate value in consideration of this charge amount. If determined, the voltage increase ΔV1 (see FIG. 12B) of the peak hold capacitor during the period in which 1-bit “1” is received can be set to a value within a desired range, for example, (Ib−Ik) / C1 = ΔV2 is established. Then, as shown in FIG. 12B, the voltage increase amount ΔV1 per 1-bit duration in the period in which 1-bit “1” is received and 1 in the period in which 1-bit “0” is received. By balancing the voltage drop amount ΔV2 per bit duration (for example, ΔV1≈ΔV2), charging and discharging can be balanced. In this way, as shown in FIG. 12B, the slope (negative) of the line segment L1 indicating the discharge characteristics and the slope (positive) of the line segment L2 indicating the charge characteristics are balanced (substantially the same). Can).

  Here, it is possible to always discharge the accumulated charge of the peak hold capacitor C1 to the discharge circuit DCH. In this case, however, a tendency to throw away a lot of charges is generated, and the power consumption of the peak hold circuit PH is reduced. It may increase. Therefore, in the present embodiment, the discharge circuit DCH includes the discharge switch SWP and the discharge resistor R6, and the discharge switch SWP is turned on periodically (that is, intermittently with periodicity) by the on / off control signal VASW. The As described above, the discharge circuit DCH periodically discharges the accumulated charge of the peak hold capacitor C1 regardless of the amplitude of the difference signal Aout input to the comparison circuit COM, and the initial voltage V of the peak hold capacitor is determined. For example, the total discharge charge amount Ik per unit time is uniquely determined. By appropriately designing the ON / OFF cycle and the ON time of the discharge switch SWP, the discharge charge amount Ik can be set to an appropriate value, and a wasteful discharge is realized. The on / off control signal VASW for periodically turning on / off the discharge switch can be obtained, for example, by dividing the difference signal Aout by the frequency dividing circuit 19 having an appropriate frequency dividing ratio. The control signal VASW can be easily generated.

  As shown in FIG. 12C, when data “0” is received, the charge of the peak hold capacitor C1 is discharged only when the on / off control signal VASW of the discharge switch SWP is active for a very short period of time. The peak follow-up voltage VC1 of the peak hold capacitor C1 decreases stepwise. A line segment obtained by approximating this voltage drop with a straight line is L1. The line segment L1 can be expressed by, for example, a linear function of y = −ax + d (the variable x is time), and its slope is −a.

  On the other hand, when data “1” is received, the peak hold capacitor C1 is charged by the charging circuit CCH. Assume that H (= VDD) is output from the comparison circuit COM when data “1” is received, the forward voltage of the diode DS is VF, and the resistance value of the charging resistor R1 is R1, per unit time (Δt). The charging charge (here, Icx) is determined by (VDD−VF) / R1. With this charged charge Icx, the peak hold capacitor C1 is charged, and the voltage level of the peak follow-up voltage VC1 rises. On the other hand, the period of the on / off control signal VASW of the discharge switch SWP is Δt. The discharge charge that is instantaneously discharged every Δt is defined as Idx. Icx> Idx is set. Therefore, the voltage of the peak hold capacitor C1 rises with time while repeating the rise and the slight fall every Δt. When the charge is accumulated in the peak hold capacitor C1, unlike the case where the charge is removed, the voltage fluctuation is not linear, but here, in order to simplify the explanation, the voltage fluctuation should be considered by approximating the voltage linearly. To. A line segment obtained by approximating the rise in the voltage of the peak hold capacitor C1 with a straight line is L2. The line segment L2 can be expressed by, for example, a linear function of y = ax + b (the variable x is time), and its slope is a. In this way, it is possible to balance the voltage drop rate and the voltage rise rate of the peak follow-up voltage VC1.

(Explanation of demodulation operation)
FIG. 13 is a signal waveform diagram for explaining the demodulation operation (first demodulation only) of the peak hold circuit in the fifth embodiment shown in FIG. In the operation example shown in FIG. 13, the voltage level of the peak follow-up voltage VC1 generated in the peak hold capacitor C1 at time t1 matches Vpeak1 (the peak voltage of the differential signal Aout when data “0” is received). . From time t1 to time t3, the 3-bit dummy data “1” is received, whereby the peak follow-up voltage VC1 is the midpoint between Vpeak1 and Vpeak2 (the peak voltage of the differential signal Aout when data “1” is received). (= Vpeak1 + (ΔVpeak / 2): where ΔVpeak is a potential difference between Vpeak1 and Vpeak2).

  Regular data communication is started from time t4.

  The on / off control signal VASW of the discharge switch SWP is instantaneously turned on periodically and intermittently from time t4 to t14. In FIG. 13, data “0” and “1” are continuously received. Since the peak follow-up time constant is set large, the fluctuation range of the peak follow-up voltage VC1 is ΔV1, and, as described above, the voltage drop rate and the voltage rise rate are balanced, so the time t4 The voltage level of the peak follow-up voltage VC1 at and the peak follow-up voltage VC1 at time t14 is substantially the same.

  Since the peak follow-up voltage VC1 (= determination threshold Vth1) remains in the vicinity of the midpoint potential of Vpeak1 and Vpeak2, the comparison circuit COM can accurately determine the magnitude of the amplitude of the input difference signal Aout. A binary (H, L) amplitude detection signal (first demodulated signal) DXdmod is obtained from the comparison circuit COM. 13, the amplitude detection signal (first demodulated signal) DXdmod is at the GND level from time t4 to time t9, and the amplitude detection signal (first demodulation) from time t9 to time t14. Signal) DXdmod is at the VDD level. Therefore, H and L can be clearly distinguished.

  FIG. 14 is a signal waveform diagram for explaining the demodulation operation (first demodulation and second demodulation) of the demodulation circuit of the fifth embodiment shown in FIG. As shown in the drawing, an H level amplitude detection signal (first demodulated signal) DXdmod is obtained in the period from time t6 to time t11 and in the period from time t16 to time t20. “1” and “0” are determined by correlation detection (integration) by a low-pass filter (LPF) 3 as a correlation detector included in the output circuit QTC, and the second demodulated signal (demodulation) is received from the level shift circuit (LS) 5. Data) DQdmod is output.

(Specific considerations regarding the design of charge and discharge characteristics)
(Consideration 1: When the allowable fluctuation range of the peak tracking voltage VC1 is ΔVpeak)
FIGS. 15A and 15B are diagrams for explaining a first preferred design example of the peak tracking characteristic of the peak hold circuit in the fifth embodiment.

(Demodulation of 1-bit data)
First, reference is made to FIG. FIG. 15A is a diagram showing a conforming example and an unsuitable example of the peak tracking characteristic when demodulating 1-bit data “1” when the allowable fluctuation range of the peak tracking voltage VC1 is ΔVpeak.

  In FIG. 15A, at time t0 when data demodulation is started, the peak tracking voltage VC1 of the peak hold capacitor C1 is maintained at Vpeak1, which is the peak value of the differential signal Aout corresponding to the data “0”. In this state, 1-bit data “1” is received, and 1-bit data “1” is demodulated by the demodulation circuit DM.

  The peak voltage value of the difference signal corresponding to the data “1” is Vpeak2, and the potential difference between Vpeak1 and Vpeak2 is ΔVpeak. In this case, due to the peak tracking function of the peak hold circuit PH included in the demodulation circuit DM, the peak tracking voltage VC1 of the peak hold capacitor C1 changes from Vpeak1 to Vpeak2 over time.

  In FIG. 15A, a characteristic line L1 indicated by a thick dotted line (a characteristic line approximating a change over time of the peak follow-up voltage of the peak hold capacitor C1 with a straight line) is obtained when 1-bit data “1” is detected. An inappropriate example of the peak tracking characteristic is shown, and a characteristic line L2 indicated by a thick solid line indicates an adaptation example of the peak tracking characteristic (however, an example indicating the minimum condition). Similarly, a characteristic line L3 indicated by a thick dotted line indicates an inappropriate example of the peak tracking characteristic when 1-bit data “0” is detected, and a characteristic line L4 indicated by a thick solid line indicates an example of conforming the peak tracking characteristic. (However, an example showing the minimum conditions) is shown.

  As described above, the period in which 1-bit transmission data from the secondary side continues is a period corresponding to the n period of the drive clock DRCK of the primary coil. Accordingly, in FIG. 15A, a period in which the voltage VC1 of the peak hold capacitor C1 (= determination threshold Vth1) corresponds to n cycles of the drive clock of the primary coil, as shown by a characteristic line L1 indicated by a dotted line. When Vpeak2 is reached, the determination threshold Vth1 becomes the same voltage level as the peak voltage of the difference signal Aout, and the reception period of 1-bit data “1” has not ended. Thereafter, accurate “1” demodulation cannot be performed, and a reception error occurs. In an inappropriate example of the peak follow-up characteristic indicated by the characteristic line L1, the voltage VC1 (= determination threshold Vth1) of the peak hold capacitor C1 reaches Vpeak2 at time t1, so that accurate demodulation is performed from time t1 to time t2. Can not be.

  Therefore, as indicated by a characteristic line L2 (conformity example) indicated by a thick solid line in FIG. 15A, it is necessary for the peak hold voltage VC1 (= determination threshold Vth1) of the peak hold capacitor C1 to transition from Vpeak1 to Vpeak2. If the peak follow-up characteristics are set so that the peak follow-up time (that is, the time required for the transition of ΔVpeak) is longer than the time corresponding to the n period of the drive clock of the primary coil (the time from t0 to t2). It will be good. That is, in the conforming example of the peak follow-up characteristic indicated by the characteristic line L2, the peak hold voltage VC1 of the peak hold capacitor VC1 is within the period in which 1-bit “1” is demodulated (the period from time t0 to time t2). Since it does not reach Vpeak2 and stays between Vpeak1 and Vpeak2, the comparison circuit COM uses the peak follow voltage VC1 of the peak hold capacitor C1 as the determination threshold value Vth1, and uses H and L of the difference signal Aout. Therefore, it is possible to accurately determine 1-bit “1” transmitted from the secondary side. However, in the adaptation example indicated by the characteristic line L2, strictly speaking, the peak follow-up voltage VC1 at time t0 is Vpeak1, and the peak follow-up voltage VC1 at time t2 reaches Vpeak2, so that demodulation is performed at time t0 and time t4. The data is invalid. When designing an actual charging circuit and discharging circuit, the change with time of the peak follow-up voltage VC1 of the peak hold capacitor C1 (for example, the rate of change of the characteristic line approximating the change with time) is smaller than the slope of the characteristic line L1. Thus, it is preferable to design the characteristics of the charging circuit CCH and the discharging circuit DCH (however, it is not limited to this example).

  Although the case where the voltage of the peak hold capacitor follows from Vpeak1 to Vpeak2 has been described above, the same applies to the case where the peak follower voltage VC1 of the peak hold capacitor follows from Vpeak2 to Vpeak1. That is, at the time when data demodulation is started, the voltage of the peak hold capacitor is maintained at Vpeak2, which is the peak value of the differential signal corresponding to data “1”, and in this state, 1-bit data “0” is stored. This is the same when 1-bit data “0” is demodulated by the demodulation circuit. That is, in FIG. 15A, the characteristic line L3 indicates an inappropriate example, and the characteristic line L4 indicates a compatible example. Also in this case, the characteristics of the charging circuit CCH and the characteristics of the discharging circuit DCH are such that the time required for the voltage of the peak hold capacitor C1 to change by ΔVpeak is equal to or longer than the n period of the driving clock DRCK of the primary coil. Should be set.

(Demodulation of data with m bits and the same value continuously)
In FIG. 15A, it is assumed that 1-bit “1” is demodulated. However, in FIG. 15B, it is assumed that m (m is an integer of 2 or more) consecutive “1” is demodulated. (The same applies when demodulating "0"). For example, when it is permitted by the communication protocol that the power receiving device 40 continuously transmits data of the same value m bits, the primary side may demodulate “1” that is m bits continuous. Can occur. In the example of FIG. 15B, m = 3 is set.

  The period during which m-bit “1” is received is a time corresponding to the (m · n) period of the drive clock DRCK of the primary coil. In the case of characteristic line L5 (unsuitable example) indicated by a thick dotted line in FIG. 15B, peak follow-up voltage VC1 (= determination threshold Vth1) within a period (time t0 to t3) corresponding to (m · n) period. ) Reaches Vpeak2 (time t2), and thereafter (period from time t2 to time t3), data "1" cannot be accurately demodulated.

  Therefore, as indicated by a thick characteristic line L6 (matching example) in FIG. 15B, it is necessary for the peak hold voltage VC1 (= determination threshold Vth1) of the peak hold capacitor C1 to transition from Vpeak1 to Vpeak2. Peak tracking characteristics (that is, the charging time constant of the charging circuit CCH and the discharging circuit) so that the peak tracking time (that is, the time required for the transition of ΔVpeak) is longer than the (m · n) period of the drive clock DRCK of the primary coil. DCH discharge time constant) may be set. In this case, the voltage of the peak hold capacitor does not reach Vpeak2 and stays between Vpeak1 and Vpeak2 within the period during which m-bit “1” is demodulated. Using the peak follow-up voltage VC1 of C1 as the determination threshold value Vth1, it is possible to accurately determine the magnitude of the amplitude of the difference signal Aout. Therefore, it is possible to ensure that the m-bit continuous “1” transmitted from the secondary side is “1”. Demodulation is possible (however, in the example of the characteristic line L6, the demodulated data at time t0 and time t3 is strictly invalid). The peak follow-up characteristics can be set based on the same concept when the peak follow-up voltage VC1 of the peak hold capacitor follows from Vpeak2 to Vpeak1.

(Consideration 2: When the allowable fluctuation range of the peak follow-up voltage VC1 is ΔVpeak / 2)
FIGS. 16A and 16B are diagrams for explaining a second preferred design example of the peak follow-up characteristic of the peak hold circuit in the fifth embodiment.

  Consideration 1 is based on the assumption that only one of m bits of continuous data “1” (or “0”) is received, but in actuality, m bits of continuous data “1” and “1” and It is desirable that any of m bits of continuous data “0” can be detected. Therefore, for example, at the start of demodulation, the peak follow-up voltage VC1 (= determination threshold Vth1) of the peak hold capacitor is set near the midpoint voltage VBS of Vpeak1 and Vpeak2 (that is, VBS = {Vpeak1 + (ΔVpeak / 2)}). (ΔVpeak is a potential difference between Vpeak1 and Vpeak2).

  When the voltage VC1 (= determination threshold Vth1) of the peak hold capacitor is set to the midpoint voltage VBS, both the fluctuation margin (variable allowable range) for Vpeak1 and the fluctuation margin (variable allowable range) for Vpeak2 are (ΔVpeak / 2). In the above consideration 1, the fluctuation margin (fluctuation allowable range) of the determination threshold Vth1 is set to ΔVpeak. On the other hand, in the example of the consideration 2, the variation margin (variation allowable range) of the determination threshold value Vth1 is ½ that of the example of the consideration 1.

  That is, in the example shown in FIG. 16A and FIG. 16B, the peak follow-up voltage VC1 (= determination threshold Vth1) of the peak hold capacitor when m bits of continuous “1” or “0” are received. However, if the peak follow-up characteristic is set so that the time required for transition by (ΔVpeak / 2) is longer than the (m · n) period of the drive clock DRCK of the primary coil, “1” which is m bits continuous "And m bits consecutive" 0 "can be properly received.

  FIG. 16A shows an example of adaptation of the peak tracking characteristics when “1” that is m bits continuous is received. In FIG. 16A, a characteristic line L7a indicated by a thick solid line shows an example of adaptation of the peak following characteristic (an example of the minimum condition). Note that the characteristic L7b indicated by a thick dashed line in FIG. 16A indicates a characteristic line when the allowable fluctuation range of the determination threshold Vth1 is ΔVpeak. That is, the characteristic line L7b indicates that the time required for the peak follow-up voltage VC1 (= determination threshold Vth1) of the peak hold capacitor C1 to change by ΔVpeak is 2 · (m · n) cycles of the drive clock DRCK of the primary coil. This means that it may be set to be longer than that.

  FIG. 16B shows an example of adaptation of the peak follow-up characteristics when receiving “0” which is m bits continuous. Each of the characteristic line L8a and the characteristic line L8b in FIG. ) Corresponding to each of characteristic lines L7a and L7b.

(Consideration 3: When fluctuation allowable range of peak follow-up voltage VC1 is ΔVpeak / p)
In the example shown in FIGS. 16A and 16B, the initial setting voltage of the peak follow-up voltage VC1 (= determination threshold Vth1) of the peak hold capacitor C1 is set to the midpoint potential VBS. However, this is merely an example, and in actual circuit design, the initial bias point (= determination threshold Vth1) of the peak follow-up characteristic (= determination threshold Vth1) of the peak hold capacitor C1 is considered in consideration of the noise margin of each of the H determination and L determination. The initial potential point may be optimized.

  FIG. 17 is a diagram for explaining a third preferred design example of the peak tracking characteristic of the peak hold circuit in the fifth embodiment. In FIG. 17, the initial bias point (initial potential point) of the peak tracking characteristic (= determination threshold Vth1) of the peak hold capacitor C1 is VBSP (= Vpeak2−ΔVpeak / P = Vpeak1 + {((p−1) / p) · ΔVpeak). } (Where P is a real number greater than 2).

  The potential difference between the peak follow-up voltages VC1 and Vpeak1 of the peak hold capacitor C1 at the start of demodulation is Δ ((p−1) / p) · ΔVpeak, and the peak follow-up voltages VC1 and Vpeak2 of the peak hold capacitor C1 at the start of demodulation. The difference in potential is (ΔVpeak / p). When both are compared, in FIG. 17, it is clear that (ΔVpeak / P) is smaller, so (ΔVpeak / p) is the minimum allowable fluctuation range of the peak tracking voltage VC1 of the peak hold capacitor C1. Therefore, in the example of FIG. 17, the time required for the peak tracking voltage VC1 of the peak hold capacitor C1 to transition by (ΔVpeak / p) is set to be equal to or longer than the (m · n) period of the drive clock of the primary coil. Therefore, it is only necessary to set the peak tracking characteristic.

  A characteristic L9a indicated by a thick solid line in FIG. 17 is an example of adapting the peak following characteristic when receiving data “1” when the minimum allowable fluctuation range of the determination threshold Vth1 is ΔVpeak / p (minimum condition) ) Is a characteristic line. Further, the characteristic L9b indicated by a thick dashed line indicates that the time required for the peak follow-up voltage VC1 (= determination threshold Vth1) of the peak hold capacitor C1 to change by ΔVpeak is (p of the drive clock DRCK of the primary coil.・ M · n) This means that it may be set longer than the period.

(Discussion 4: Circuit design considering landing or removal detection)
In the considerations 1 to 3, paying attention to the demodulation of the signal by the demodulation circuit DM, the allowable “delay of peak tracking” was examined. Here, the allowable “speed of peak tracking” will be examined. When the demodulating circuit DM is also used to detect at least one of removal and landing of the power receiving device, the “peak tracking speed” that can cope with detection or landing detection of the power receiving device is the peak hold. Required for the circuit.

  That is, the peak follow-up characteristic of the peak hold circuit PH in the fifth embodiment has a “peak follow-up speed” that can cope with the removal or landing detection of the power receiving apparatus, and is a highly reliable signal demodulator. Is preferably designed so as to satisfy two of the following factors: “slow peak tracking”.

  FIG. 18 is a diagram for explaining a fourth preferred design example of the peak tracking characteristic of the peak hold circuit in the fifth embodiment. In FIG. 18, removal of the power receiving apparatus occurs at time t20. Accordingly, the peak value of the difference signal Aout output from the primary-side differential circuit SAMP increases from, for example, Vpeak1 to Vpeak3. Here, Vpeak3 is a peak voltage value of the differential signal Aout corresponding to the state where the power receiving device is removed. The maximum allowable time for detecting the removal of the power receiving apparatus is TX.

  That is, the primary side must detect removal of the power receiving device by time t25. FIG. 18 shows three characteristic lines (L10a, L10b, L11) indicating peak tracking characteristics. In the peak follow-up example indicated by the characteristic line 11 (thick two-dot chain line), the time when the peak hold voltage Vpeak of the peak hold capacitor C1 reaches Vpeak3 is time t26. That is, in this example, the period until the state where the removal of the power receiving apparatus can be detected exceeds the maximum allowable time TX, and is therefore unsuitable.

  In the peak follow-up example indicated by the characteristic line L10a (thick solid line), the time point when the peak follow-up voltage VC1 of the peak hold capacitor C1 reaches Vpeak3 is time t25, and in this example, removal of the power receiving device can be detected. The period until the state is reached is just the maximum allowable time TX. Therefore, although it is a conforming example, it is quite difficult to provide a margin in consideration of detection delay and the like.

  In the peak follow-up example indicated by the characteristic line L10b (thick one-dot chain line), the time point when the peak follow-up voltage VC1 of the peak hold capacitor C1 reaches Vpeak3 is time t24. In this example, removal of the power receiving device is detected. Since the period until the state is obtained is within the maximum allowable time TX, for example, the removal of the power receiving device can be reliably detected in the period from time t24 to time t25. Therefore, this example is a preferable adaptation example.

  In the above description, the removal of the power receiving apparatus is taken as an example, but in the case of landing detection, a preferable example of the peak tracking characteristic can be determined based on the same concept.

(Example of design method for charging circuit and discharging circuit)
Here, the design procedure of each characteristic (time constant) of the charging circuit and the discharging circuit will be considered. For example, the design is performed by the following procedure 1 and procedure 2.

(Procedure 1: Setting of preferable ranges of voltage increase rate and voltage decrease rate)
Based on the design principle shown in the above considerations 1 to 4, the allowable range of the slope of the straight line (the peak following characteristic line obtained by linear approximation) indicating the voltage increase rate at the time of charging the peak hold capacitor C1, or at the time of discharging The allowable range of the slope of the straight line indicating the voltage drop rate can be determined. For example, a preferable range of the voltage increase amount and the voltage decrease amount of the peak hold capacitor voltage per period in which 1-bit data continues (a period corresponding to n cycles of the drive clock of the primary coil) is determined.

(Procedure 2: Balance design between voltage rise rate and voltage fall rate)
Then, if the circuit characteristics of the charging circuit CCH and the discharging circuit DCH are determined so that the amount of voltage increase and the amount of voltage drop per period in which 1-bit data continues are balanced (same), Good.

  That is, since the voltage of the peak hold capacitor C1 fluctuates following the peak of the input signal Aout, when the data “1” is received, the voltage of the peak hold capacitor rises and the data “0” is received. When being done, the voltage on the peak hold capacitor will drop. Assuming that data “1” and data “0” are alternately received, the voltage of the peak hold capacitor repeatedly rises and falls, but the voltage rise amount and the voltage fall amount in the 1-bit data period are the same. If so, the voltage level of the peak hold capacitor does not change before and after receiving the series of data (remains in the vicinity of a predetermined bias point).

  In most cases, the occurrence ratio of “1” and “0” included in the received data is almost the same over a long period of time (or the transmission data on the secondary side is intentionally so. Therefore, if the voltage increase amount and the voltage decrease amount in the 1-bit data period are set to be the same, the voltage level of the peak hold capacitor is set to Vpeak1 and Vpeak2 in the demodulation period. Therefore, the reliability of the demodulated binary signal can be ensured. If the amount of voltage rise and the amount of voltage drop are not balanced, even when data “1” and “0” are alternately received, the determination threshold (that is, the voltage of the peak hold capacitor) is changed over time. Shifting to either Vpeak1 or Vpeak2 side, the fluctuation margin decreases accordingly, eventually reaching the peak value, at which point the voltage of the peak hold capacitor is demodulated Cannot be used as the determination threshold.

  Therefore, as described above, when data “1” is received, the voltage of peak follow voltage VC1 of peak hold capacitor C1 during the duration of data “1” (a period corresponding to the n period of the drive clock of the primary coil). Increase amount and voltage drop amount of peak follow-up voltage VC1 of peak hold capacitor C1 during the duration of data “0” (a period corresponding to the n period of the drive clock of the primary coil) when data “0” is received. Therefore, it is preferable to set the characteristic of the charging circuit CCH (charging time constant) and the characteristic of the discharging circuit DCH (discharging time constant).

  As described above, the characteristics of the charging circuit CCH and the characteristics of the discharging circuit DCH can be set to preferable characteristics through the procedure 1 and the procedure 2 described above. For example, when receiving the same m-bit continuous value, the peak follow-up time required for the peak follow-up voltage VC1 (= determination threshold Vth1) of the peak hold capacitor C1 to transition (ΔVpeak / p) is: The peak follow-up voltage VC1 of the peak hold capacitor C1 (== m · n) period of the primary coil drive clock and a 1-bit duration (a period corresponding to the n period of the primary coil drive clock) (= Each characteristic (for example, time constant) of the charging circuit and the discharging circuit is set so that the voltage increase amount and the voltage decrease amount of the determination threshold value Vth1) are balanced (that is, approximately the same, approximately the same, or the same). (It is determined.

(Sixth embodiment)
FIG. 19 is a diagram for explaining an example of the operation of the primary-side electronic device (cradle) and the non-contact power transmission system on which the power transmission device including the demodulation circuit of the present invention is mounted.

  A first intermittent power transmission period TA1 in FIG. 19 is a period corresponding to the standby phase (standby state). In the standby phase, the power transmission device 10 built in the charger (cradle) 500 that is an electronic device on the power transmission side performs intermittent power transmission, and the landing (setting) of the electronic device (for example, a mobile phone) 510 on the power reception side is determined. For example, detection is performed once every 0.3 seconds (step S1). That is, as described above, when the primary coil L1 alone is shifted to a state where the primary coil L1 and the secondary coil L2 are electromagnetically coupled, the resonance characteristics of the resonance circuit change, and the primary coil L1. The voltage level of the coil end signal decreases. This decrease in voltage level is detected using, for example, the peak hold circuit PH included in the demodulation circuit DM of the present invention. For example, after resetting and initializing the peak hold capacitor included in the peak hold circuit PH according to the detection timing, the peak voltage value is acquired, and the acquired peak voltage value is compared with the landing determination threshold value. Landing can be detected. Thereby, the landing (setting) of the power receiving device 510 is detected (step S2). Note that the power transmission control device 20 (see FIG. 4) included in the power transmission device 200 controls the power transmission unit 12 to intermittently drive the primary coil L1 in order to enable landing detection. For example, the primary coil L1 is driven for 5 milliseconds every 0.3 seconds. Similarly, removal of the power receiving device can be detected using the peak hold circuit PH.

  When the landing of the power receiving device 510 is detected, various information exchange (negotiation and setup) is performed between the power transmission device 10 and the power receiving device 40 (step S3). As described above, frequency modulation is used for communication from the power transmission device 10 to the power reception device 40, and load modulation is used for communication from the power reception device 40 to the power transmission device 10. The demodulation circuit DM of the present invention included in the power transmission device 10 demodulates the signal (data) transmitted by the power reception device 40 by load modulation by detecting the amplitude of the differential signal Aout.

  In the negotiation phase, authentication information (including ID information) is exchanged. For example, standard / coil / system conformity confirmation processing is executed based on the received ID information and the like. Further, in the negotiation phase, exchange of safety information (for example, detection parameters for detecting foreign matter, etc. is also executed. The exchange operation of these various information is performed in the temporary power transmission period TB (specifically, It is executed in the authentication period and the foreign object detection period before normal power transmission.

  That is, in the temporary power transmission period TB, the power transmission device 10 performs temporary power transmission. Temporary power transmission is continuous power transmission temporarily executed to enable information exchange or the like before normal power transmission. Then, the power transmission side and the power reception side exchange authentication information such as ID information, and based on the received authentication information (ID information or the like), confirm whether or not the standards / coils / systems and the like are compatible with each other. In addition, for example, the power receiving side transmits safety threshold information for foreign object detection or the like to the power transmission side, and performs safety information exchange. In this negotiation process, whether or not information communication is possible between the power transmission side and the power reception side, whether or not the communicated information is valid, and whether or not the load state on the power reception side is appropriate (foreign matter non-detection) Confirmation is also performed. In the negotiation process, when it is determined that the standards / coils / systems or the like are inconsistent as a result of the exchange of authentication information (ID information or the like) or a time-out error occurs, the power transmitting apparatus 10 performs, for example, a standby phase. Migrate to

  After the negotiation phase, the contactless power transmission system proceeds to the setup phase. In this setup phase, a setup process is executed in which setup information such as information on the corresponding function and setting information for each application is transferred. For example, the transmission condition is specified based on the result of the negotiation process. Specifically, when the power receiving side transmits transmission condition information such as the coil driving voltage and driving frequency to the power transmission side, the power transmission side performs normal power transmission such as the coil driving voltage and driving frequency based on the received transmission condition information. Set the transmission conditions for. In addition, this setup process also exchanges information about supported functions and exchanges of setting information that differs for each higher-level application. Specifically, threshold information for load state detection on the power receiving side after the start of normal power transmission (for example, threshold information for data communication / foreign object detection), or in the command phase after normal power transmission, Information exchange regarding the types of commands that can be issued / executed by the power receiving side and additional corresponding functions such as a communication function and a periodic authentication function is executed in this setup process. This makes it possible to exchange different setting information according to the application such as the type of electronic device (mobile phone, audio device, etc.) and model. In the setup process, when removal of the secondary device 510 is detected (step S8) or a time-out error occurs, for example, the process proceeds to a standby phase. When the secondary device 510 is removed, the voltage level of the coil end signal of the primary coil L1 rises. Therefore, for example, the peak hold circuit PH included in the demodulation circuit DM of the present invention is used to increase the voltage level. By detecting this, removal of the power receiving device (secondary device including the power receiving device) is detected.

  Thus, the negotiation process and the setup process (these processes are processes for confirming (ie, authenticating) the adaptability of the other party based on the exchanged information. In a broad sense, it can be said that the power receiving device 40 is an appropriate power transmission target, and after necessary information is set, normal power transmission (here, a battery or the like is a power supply target). (Referred to as continuous power transmission for power supply to the load) is started (step S4). In the normal power transmission period TC1 (battery charging period), the power transmission device 10 performs continuous power transmission at a power level necessary for charging the battery. When normal power transmission is started, an LED provided on the power receiving side electronic device (cellular phone) 510 is turned on.

  In the normal power transmission period TC1, in parallel with normal power transmission from the power transmission side, periodic authentication communication from the power reception side (communication of predetermined pattern data for detecting foreign object insertion) and packet data communication (for example, a power reception device) Data for notifying the primary side of information such as the operation state of the battery and the load state of the battery). The periodic authentication communication is executed in a periodic authentication period TC2 provided periodically. However, as described above, communication from the power receiving side is performed without stopping power supply to the load 90 (battery) that is a power supply target (always communication (power supply non-stop power supply)). Since the accuracy of data demodulation on the primary side is high, highly reliable communication is ensured even when constant communication is performed. Further, during the normal power transmission period TC1, for example, intermittent detection of removal of the power receiving apparatus is executed, and when removal is detected, the process proceeds to the initial standby phase (step S9).

  Further, when full charge of the battery is detected in the normal power transmission period TC1, a full charge notification is transmitted from the power receiving device 40 to the power transmission device 10, and the power transmission device 10 that has received this notification stops normal power transmission. When the normal power transmission is stopped, the LED provided in the power receiving side electronic device (mobile phone) 510 is turned off. And it transfers to the standby phase (2nd intermittent power transmission period TA3) after full charge detection (step S5).

  The second intermittent power transmission period TA3 is a period corresponding to a standby state after full charge detection. In the second intermittent power transmission period TA3, for example, removal detection is executed once every 5 seconds, and whether or not recharging is necessary is executed once every 10 minutes. When the power-reception-side electronic device (mobile phone) 510 is removed after full charge, the process returns to the initial standby phase (step S6). If it is determined that recharging is necessary after full charging, the process returns to step S3 (step S7).

  In addition, although this embodiment was explained in full detail, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Therefore, all such modifications are included in the present invention.

  The present invention simplifies the configuration of the communication circuit on the primary side, and contributes to the realization of a non-contact power transmission system that supports multi-power transmission. The present invention can be used for a demodulation circuit, a power transmission device, a power transmission control device, a data demodulation method, and the like.

10 power transmission device, 12 power transmission unit, 14 waveform monitor circuit, 20 power transmission control device,
22 power transmission side control unit (power transmission side control circuit), 40 power receiving device, 43 rectification unit,
48 power supply control unit, 46 load modulation unit, 52 power receiving side control unit, 60 frequency detection circuit,
500 Primary side electronic equipment (cradle),
510 secondary side electronic device (mobile phone terminal),
L1 primary coil, CP1 resonant capacitor, DM demodulation circuit,
Aout differential signal, SAMP differential circuit (differential amplifier circuit),
AMT amplitude detection circuit, PH peak hold circuit, DET demodulation decision circuit,
QTC output circuit (circuit that demodulates and outputs 1-bit data),
3 (LPF) Low-pass filter as a correlation detector, COM comparison circuit,
5 (LS) level shift circuit, C1 peak hold capacitor,
R1 Resistance (integral resistance) that determines the peak tracking time constant,
DS rectifier (diode),
The peak voltage value of the difference signal Aout corresponding to Vpeak1 data “0”,
The peak voltage value of the difference signal Aout corresponding to Vpeak2 data “1”,
Vpeak3 The peak voltage value of the differential signal Aout corresponding to the state where the power receiving device is removed,
SW1, SW2 Switches for switching the peak hold circuit to the demodulation determination circuit CCH charging circuit, DCH discharging circuit, SWP discharging switch, R9 discharging resistor,
VC1 peak tracking voltage, binary detection signal of DXdmod H and L (first demodulated signal),
DQdmod Demodulated data (second demodulated signal)

Claims (18)

Provided in the power transmission device of a contactless power transmission system that electromagnetically couples a primary coil and a secondary coil to transmit power from the power transmission device to the power reception device, and demodulates a signal transmitted by the power reception device by load modulation A demodulating circuit,
A differential circuit that outputs a differential signal between a first signal from one end of a resonant capacitor connected to the primary coil and a second signal from the other end of the resonant capacitor;
An amplitude detection circuit for detecting an amplitude level of the differential signal output from the differential circuit;
Including a demodulation circuit. The demodulation circuit according to claim 1, wherein
The amplitude detection circuit has a peak hold circuit;
The demodulating circuit, wherein the peak hold circuit is also used for detecting at least one of removal and landing of the power receiving device. The demodulation circuit according to claim 1, wherein
The amplitude detection circuit includes:
A peak hold circuit;
A demodulation determination circuit that compares the output voltage of the peak hold circuit with a determination threshold and outputs an amplitude detection signal of the differential signal;
A demodulating circuit. The demodulation circuit according to claim 1, wherein
The amplitude detection circuit includes:
An integrating circuit including at least one resistor and a peak hold capacitor;
A comparison circuit that compares the differential signal output from the differential circuit with the voltage of the peak hold capacitor;
A feedback path for feeding back the output signal of the integration circuit to the comparison circuit;
A peak hold circuit having a switch provided between an output node of the comparison circuit and an input node of the integration circuit;
When the switch is off, the peak hold capacitor and the comparison circuit operate as a demodulation determination circuit that outputs an amplitude detection signal of the differential signal. A demodulation circuit according to claim 4, wherein
In the preparation period in which the power receiving device does not perform the load modulation, the switch is turned on, and a peak hold voltage is generated in the peak hold capacitor,
In a demodulation period that is a period for demodulating a signal transmitted by the power receiving apparatus, the switch is turned off, and the peak hold voltage and the difference signal as a determination threshold are set by the comparison circuit included in the demodulation determination circuit. And the comparison circuit outputs an amplitude detection signal of the differential signal. A demodulation circuit according to claim 4 or claim 5, wherein
As the at least one resistor included in the integrating circuit,
A first resistor constituting a charge time constant circuit together with the peak hold capacitor;
Forming a discharge time constant circuit together with the peak hold capacitor, and a second resistance having a resistance value higher than the resistance value of the first resistance;
A demodulating circuit. The demodulation circuit according to claim 1, wherein
The amplitude detection circuit includes:
An integrating circuit including one resistor and a first peak hold capacitor;
A buffer circuit connected to an output node of the first peak hold capacitor;
A second peak hold capacitor that is charged or discharged by the output of the buffer path;
A comparison circuit that compares the differential signal output from the differential circuit with the voltage of the second peak hold capacitor, and whose output node is connected to an input node of the integration circuit;
A peak hold circuit having a switch provided between an output node of the buffer circuit and the second peak hold capacitor;
When the switch is OFF, the second peak hold capacitor and the comparison circuit operate as a demodulation determination circuit that outputs an amplitude detection signal of the differential signal. The demodulation circuit according to claim 7, wherein
In a preparation period in which the power receiving device does not perform the load modulation, the switch is turned on, and a peak hold voltage is generated in the second peak hold capacitor,
In the data demodulation period, which is a period for demodulating the signal transmitted by the power receiving apparatus, the switch is turned off, whereby the first peak hold capacitor and the second peak hold capacitor are disconnected, and the demodulation is performed. The comparison circuit constituting the determination circuit compares the peak hold voltage of the second peak hold capacitor with the difference signal, and outputs an amplitude detection signal of the difference signal from the comparison circuit. Demodulator circuit. The demodulation circuit according to claim 1, wherein
The amplitude detection circuit includes:
With a peak hold capacitor,
A comparison circuit for comparing the voltage of the output node of the peak hold capacitor and the differential signal;
A charging circuit that is provided between the comparison circuit and the peak hold capacitor and charges the peak hold capacitor based on an output signal of the comparison circuit;
The peak voltage of the differential signal is provided between the output node of the peak hold capacitor and a reference potential, discharges the charge of the peak hold capacitor to the reference potential, and the discharge is input to the comparison circuit. A peak hold circuit having a discharge circuit independent of
A demodulation circuit, wherein an output signal of the comparison circuit is extracted as an amplitude detection signal of the differential signal. The demodulation circuit according to claim 9, wherein
The charging circuit has a rectifying element and a charging resistor connected in series,
The discharge circuit is:
One end connected to the output node of the peak hold capacitor, and a discharge switch that periodically turns on to discharge the charge of the peak hold capacitor;
A demodulation circuit comprising: a discharge resistor connected between the other end of the discharge switch and the reference potential. A demodulation circuit according to claim 9 or claim 10, wherein
The duration of 1-bit data transmitted from the power receiving device side is a period corresponding to n cycles (n is an integer of 2 or more) of the AC drive signal of the primary coil,
Further, when the power receiving apparatus transmits binary data by load modulation, the same value of m bits (m is an integer of 2 or more) is allowed to continue,
Further, a peak voltage corresponding to one value of the binary data generated in the peak hold capacitor is set as a first peak hold voltage, corresponds to the other value of the binary data, and When a peak voltage higher than the first peak hold voltage is a second peak hold voltage, and a potential difference between the first peak hold voltage and the second peak hold voltage is ΔVpeak,
The characteristics of the charging circuit and the characteristics of the charging circuit so that the time required for the voltage of the peak hold capacitor to change by ΔVpeak is equal to or longer than the time corresponding to the (m · n) period of the AC drive signal of the primary coil. A demodulation circuit characterized in that the characteristics of the discharge circuit are set. A demodulation circuit according to claim 9 or claim 10, wherein
The duration of 1-bit data transmitted from the power receiving device side is a period corresponding to n cycles (n is an integer of 2 or more) of the AC drive signal of the primary coil,
Further, when the power receiving apparatus transmits binary data by load modulation, the same value of m bits (m is an integer of 2 or more) is allowed to continue,
Further, a peak voltage corresponding to one value of the binary data generated in the peak hold capacitor is set as a first peak hold voltage, corresponds to the other value of the binary data, and A peak voltage higher than the first peak hold voltage is defined as a second peak hold voltage, and a potential difference between the first peak hold voltage and the second peak hold voltage is defined as ΔVpeak.
Further, any one of a potential difference between the voltage of the peak hold capacitor and the first peak hold voltage at the start of demodulation and a potential difference between the voltage of the peak hold capacitor and the second peak hold voltage at the start of demodulation. When the smaller potential difference is (ΔVpeak / p) (where p is a real number greater than 2),
The time required for the voltage of the peak hold capacitor to transit by (ΔVpeak / p) is equal to or longer than the time corresponding to the (m · n) period of the AC drive signal of the primary coil.
In addition, when the voltage of the peak hold capacitor receives 1 bit of one value of the binary data, the voltage drop amount that falls in a period corresponding to n cycles of the primary coil, and the binary data The characteristics of the charging circuit and the characteristics of the discharging circuit are set so that the amount of voltage increase that rises in a period corresponding to the n period of the primary coil is balanced when one bit of the other value is received. A demodulating circuit. A demodulation circuit according to claim 11 or claim 12,
The peak hold circuit is also used for detecting at least one of removal and landing of a power receiving device including the power receiving device, and a peak required for the peak hold circuit at the time of detecting at least one of the removal and landing. A demodulating circuit in which characteristics of the charging circuit and characteristics of the discharging circuit are set so as to satisfy the following characteristic. A demodulation circuit according to any one of claims 4 to 13,
A demodulation circuit, further comprising: an output circuit including a correlation detector that detects a correlation of an amplitude detection signal of the difference signal output from the comparison circuit. A power transmission control device for controlling an operation of the power transmission device provided in the power transmission device of a contactless power transmission system that electromagnetically couples a primary coil and a secondary coil to transmit power from the power transmission device to the power reception device. There,
A demodulation circuit according to any one of claims 1 to 14,
While controlling the operation of the power transmission device, a power transmission side control unit to which the output signal of the demodulation circuit is input,
A power transmission control device comprising: The power transmission device of a contactless power transmission system that electromagnetically couples a primary coil and a secondary coil to transmit power from a power transmission device to a power reception device,
A power transmission unit having a drive unit for AC driving the primary coil;
A power transmission control device according to claim 15;
A power transmission device comprising:   An electronic apparatus comprising: the power transmission device according to claim 16; and a primary coil driven by the power transmission device. The power receiving device of a contactless power transmission system in which a primary coil and a secondary coil are electromagnetically coupled to transmit power from a power transmitting device to a power receiving device, and the power receiving device supplies the power to a load to be fed A data demodulating method in which the power transmission device demodulates data transmitted by load modulation from:
The load modulation in the power receiving device is performed without stopping power feeding to the load to be fed, and the load modulation is performed in synchronization with an AC drive signal of the primary coil, and the power receiving When the duration of 1-bit data transmitted from the device side is a period corresponding to n cycles (n is an integer of 2 or more) of the AC drive signal of the primary coil,
Generating a differential signal between a first signal from one end of a resonant capacitor connected to the primary coil and a second signal from the other end of the resonant capacitor;
Detecting the amplitude of the differential signal for each period of the AC drive signal of the primary coil, and obtaining the amplitude detection signal of the differential signal;
A data demodulating method, wherein a correlation of an amplitude detection signal of the differential signal in a period corresponding to n cycles of the AC drive signal is detected, and 1-bit data is demodulated every n cycles of the AC drive signal. .

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