JP4416574B2 - Substrate manufacturing method and bonding method - Google Patents

Substrate manufacturing method and bonding method Download PDF

Info

Publication number
JP4416574B2
JP4416574B2 JP2004169982A JP2004169982A JP4416574B2 JP 4416574 B2 JP4416574 B2 JP 4416574B2 JP 2004169982 A JP2004169982 A JP 2004169982A JP 2004169982 A JP2004169982 A JP 2004169982A JP 4416574 B2 JP4416574 B2 JP 4416574B2
Authority
JP
Japan
Prior art keywords
bump
substrate
electrode
bumps
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004169982A
Other languages
Japanese (ja)
Other versions
JP2005353670A (en
JP2005353670A5 (en
Inventor
正剛 赤池
治人 小野
研爾 玉森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2004169982A priority Critical patent/JP4416574B2/en
Publication of JP2005353670A publication Critical patent/JP2005353670A/en
Publication of JP2005353670A5 publication Critical patent/JP2005353670A5/ja
Application granted granted Critical
Publication of JP4416574B2 publication Critical patent/JP4416574B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Wire Bonding (AREA)

Description

本発明は基板に設けた微小な(マイクロ)電極同士、すなわちバンプとパッド間の電極同士の接合を基板間の接合で行う方法及び構造に関するものである。   The present invention relates to a method and a structure for bonding minute (micro) electrodes provided on a substrate, that is, bonding between electrodes between a bump and a pad by bonding between the substrates.

近年、MEMS(Micro−Electric−Micro−System)の多機能化と小型軽量化にともなって、素子自体が複雑化しており製作が困難になってきている。このため、電子回路とMEMSをそれぞれ異なる基板に作製し、この後両基板の配線電極同士を電気的に接合し、同時に両基板を一体化する必要性が高まっている。   In recent years, with the increase in functionality and reduction in size and weight of MEMS (Micro-Electric-Micro-System), the elements themselves have become more complex and difficult to manufacture. For this reason, it is necessary to fabricate the electronic circuit and the MEMS on different substrates, and then electrically bond the wiring electrodes of the two substrates to each other and simultaneously integrate the two substrates.

しかしながら、基板間の接合において、両基板に形成した微小な多数の電極同士を全て同時に接合することは困難であった。   However, in bonding between substrates, it was difficult to bond all the minute electrodes formed on both substrates simultaneously.

特許文献1において、面実装型半導体パッケージングとして半田ボールから成るバンプ、及びこのバンプ上面に粒状の高融点金属を散在させたバンプを対向バンプ間で押圧し、粒状金属でバンプ表面の酸化膜を突き破り、加熱によって該バンプ間を接合している。   In Patent Document 1, bumps made of solder balls as surface mounting type semiconductor packaging, and bumps in which granular refractory metal is scattered on the upper surface of the bumps are pressed between opposing bumps, and the oxide film on the bump surface is formed with granular metal. The bumps are pierced and joined by heating.

さらに、特許文献2において錫/鉛共晶はんだを窒素雰囲気リフロー炉内でリフローしてバンプを半球面状に形成し、接合用バンプとして用いている。
特開平9−167773号 特開平11−163036号
Further, in Patent Document 2, tin / lead eutectic solder is reflowed in a nitrogen atmosphere reflow furnace to form a bump into a hemispherical shape and used as a bonding bump.
JP-A-9-167773 JP 11-163036 A

しかしながら、上述した特許文献1に開示している低融点金属のInボールを用いているため、半球状のバンプを形成することは容易であり、かつバンプとパッド間の接合をIn−Pd−Auの合金化によって確実に接合できるとしているが、Inを一旦溶融して半球状のバンプを形成しているため微細寸法のバンプを形成することは容易ではなく、さらに加熱下で接合することは接合後室温までの降温過程で被接合体間の線膨張係数差に起因する内部応力による歪を生じ、寸法精度に影響を及ぼすことも考えられる。   However, since the low melting point metal In ball disclosed in Patent Document 1 described above is used, it is easy to form a hemispherical bump, and the bonding between the bump and the pad is made of In-Pd-Au. However, it is not easy to form bumps with fine dimensions because In is once melted to form hemispherical bumps. It is also possible to join under heating. It is also conceivable that distortion due to internal stress caused by the difference in linear expansion coefficient between the joined bodies is generated in the process of lowering the temperature to room temperature and this affects the dimensional accuracy.

さらに、上述した特許文献2に開示している軟質はんだ合金を用いたバンプ形成も半球状のバンプを加熱溶融手段で形成しているので、特許文献1と同様に微細寸法のバンプを形成することは容易ではなく、さらにバンプ/パッド間の接合も加熱下で行うため線膨張係数差に起因する歪を生じ、寸法精度に影響を及ぼすことも考えられる。   Further, the bump formation using the soft solder alloy disclosed in Patent Document 2 described above also forms hemispherical bumps by heating and melting means. In addition, since the bonding between the bumps / pads is also performed under heating, distortion due to the difference in linear expansion coefficient is generated, which may affect the dimensional accuracy.

そこで、本発明は、面心立方晶金属からなり、バンプ上部の表面の表面積よりもバンプ側面の表面積が大きく、前記バンプ上部の表面中央部に溝が形成された電極バンプがメッキにより形成された基板を用意する工程と、前記電極バンプを上部から平板で押圧し、前記電極バンプの上部の表面を半球面化する工程と、を備えたことを特徴とする電極バンプが形成された基板の製造方法を提供するものである。 Accordingly, the present invention consists face-centered cubic metal, the surface area of the bump side than the surface area of the bump top surface is rather large, electrode bumps grooves in the center part of the surface of the bump top is formed is formed by plating And a step of pressing the electrode bumps from above with a flat plate to make the upper surface of the electrode bumps hemispherical. A manufacturing method is provided.

本発明は配線基板の回路端子にメッキにより形成したAuバンプを押圧板で押圧力を印加する。これによって該バンプ側面から材料固有のすべり系の中で降伏セン断応力より大きなセン断応力の作用するすべり系で転移線を介してすべり変形が生じ、そして該転移線が該バンプ側面及び表面から抜け出る毎に塑性変形が進行する。このため、アスペクト比の大きいバンプの場合、バンプ側面で最も表面積が大きく、転移線は該バンプ側面から抜け出やすく、そしてこのため塑性変形が生じ易くなる。逆にバンプ表面から距離のあるバンプ中央部は、転移線が抜け難いため大きな塑性変形を生じ難く、弾性変形が支配的になる。従って、該バンプに作用していた該押圧力を除去した時、塑性変形はバンプ側面で大きく、逆に該バンプ中央部で小さい。上記から、結果として該バンプは半球面状に形成されることになる。   In the present invention, a pressing force is applied to Au bumps formed by plating on circuit terminals of a wiring board using a pressing plate. This causes slip deformation through a transition line in the slip system in which a shear stress greater than the yield shear stress acts in the slip system inherent to the material from the bump side surface, and the transition line extends from the bump side surface and the surface. Each time it exits, plastic deformation proceeds. For this reason, in the case of a bump having a large aspect ratio, the surface area is the largest on the side surface of the bump, the transition line tends to come out from the side surface of the bump, and plastic deformation is likely to occur. On the contrary, in the bump central portion that is far from the bump surface, it is difficult for the transition line to come off, so that large plastic deformation is difficult to occur, and elastic deformation becomes dominant. Therefore, when the pressing force acting on the bump is removed, the plastic deformation is large on the side surface of the bump, and conversely, it is small at the central portion of the bump. From the above, as a result, the bump is formed in a hemispherical shape.

そして該押圧過程で、バンプ表面の凹凸を及びバンプ中央部に作製上余儀なくされた窪み溝を平坦・平滑化することができる。   In the pressing process, it is possible to flatten and smooth the irregularities on the bump surface and the concave grooves that are inevitably produced in the center of the bump.

上記方法によって、バンプ表面を平滑化し及び半球面化した後、該塑性変形過程で加工硬化したバンプを熱処理により軟化させることから、本接合時に該バンプの塑性変形能を大きくすることができる。   After the bump surface is smoothed and hemispherical by the above method, the bumps that are work-hardened in the plastic deformation process are softened by heat treatment, so that the plastic deformability of the bumps can be increased during the main joining.

そしてバンプとパッドを接触させ、該バンプと該パッド間に押圧力を印加することによって、加熱することなく室温で常温接合を行うことができる。このためバンプを溶融することなく、かつ線膨張係数差に起因する歪を発生することなく、効果的に接合することができる。   By bringing the bump and the pad into contact and applying a pressing force between the bump and the pad, room temperature bonding can be performed at room temperature without heating. For this reason, it is possible to effectively bond the bumps without melting them and without causing distortion due to the difference in linear expansion coefficient.

さらに、常温接合過程において、荷重印加時、バッドとバンプ間の接触は該バンプ半球面の凸部で開始し、印加荷重の増加と共に次第に該バンプの半径方向へと進んでいき、この過程で接合が生じる。   Further, in the normal temperature bonding process, when a load is applied, the contact between the pad and the bump starts from the convex portion of the bump hemisphere, and gradually proceeds in the radial direction of the bump as the applied load increases. Occurs.

このため、バンプ中央部での非接合部を排してバンプ全面での接合を可能にすることから、大きな接合強度を得ることができる。   For this reason, since the non-joining part in the bump center part is eliminated and joining on the entire bump surface is possible, a large joining strength can be obtained.

以下に本発明をより具体的に説明する。   The present invention will be described more specifically below.

図1、図2、図3、図4、図5、図6、図7、図8は本発明の特徴を良く表す図面であり、同図において、1は一方のSi基板、2は一方のSi基板1に形成したSi酸化膜からなる絶縁膜、3は絶縁膜2の上に形成したAlからなる電気的な配線、4は絶縁膜2及び配線3の一部の上に形成した絶縁体からなるパッシベイション膜、5は配線3と電気的に結合しているAuからなるバンプ、6はAuバンプ5の上部にAuメッキによって発生を余儀なくされた溝、7はバンプ5の上部のバンプ表面、8はバンプ5の上部を押圧するための押圧板、9は押圧板に作用する印加荷重、10は押圧板8を押しこんだ後、押圧板を除去するための除去荷重、11は他方のSi基板、12は他方のSi基板11上に形成したAuからなる電極としてのパッド、14はバンプ5を押圧板8で印加荷重9で押し込んだ時に転移線を介して結晶面ですべりを伴った塑性変形が生ずるすべり面を示したものである。   1, 2, 3, 4, 5, 6, 7, and 8 are drawings that clearly illustrate the features of the present invention. In FIG. 1, 1 is one Si substrate and 2 is one. An insulating film made of a Si oxide film formed on the Si substrate 1, 3 is an electrical wiring made of Al formed on the insulating film 2, and 4 is an insulator formed on part of the insulating film 2 and the wiring 3. 5 is a bump made of Au that is electrically coupled to the wiring 3, 6 is a groove that must be generated by Au plating on the top of the Au bump 5, and 7 is a bump on the top of the bump 5. Surface, 8 is a pressing plate for pressing the upper part of the bump 5, 9 is an applied load acting on the pressing plate, 10 is a removing load for removing the pressing plate after pressing the pressing plate 8, and 11 is the other The Si substrate 12 is an electrode made of Au formed on the other Si substrate 11. Head, 14 shows a sliding surface where plastic deformation occurs accompanied by sliding the crystal surface through the transfer line when pushed bump 5 at an applied load of 9 by the pressing plate 8.

次に上記構成において、Auメッキによって形成したバンプ5は、図1に見るように該Auメッキ工程において、パッシべイション膜4の厚さから配線3の厚さを差し引いた厚さに相当する深さの溝6の発生を余儀なくされるので、まずバンプ5上に図2に見るように平板から成る押圧板8を介して印加荷重9を印加する。そして、該印加荷重9をさらに増加していくと、図3に見るようにバンプ5は次第に塑性変形を増す。拘束を受けていないバンプ5の側面表面から、材料内部のすべり面で発生した転移線が抜け易く、該転移線が抜け出る時に塑性変形が生ずる。Auから成るバンプ5は面心立法晶であることから、塑性変形の生ずるすべり系は4つの等価な面{111}と及び3つの等価なすべり方向<110>であることからユニットセル当たり12のすべり系があり、セン断応力によって生じたすべり系を有する結晶面でのすべり面14(図4)のすべりによって、該バンプ5は印加荷重方向に対して直角な方向、すなわちバンプ5の半径を大きくするように塑性変形し、同時に印加荷重方向に対して平行な方向、すなわちバンプ5の高さを短くする方向に大きく塑性変形する。バンプ5において、材料内部で発生した転移線は表面積の大きい側面から抜け出易いことから、該側面近傍での塑性変形能は大きく、逆に該バンプ5の体表面から距離のある内部に行くに従って、すなわち中心部付近に行くに従って、転移線は抜け出にくくなり、塑性変形が困難に成る。   Next, in the above configuration, the bump 5 formed by Au plating has a depth corresponding to the thickness obtained by subtracting the thickness of the wiring 3 from the thickness of the passivation film 4 in the Au plating step as shown in FIG. Since the groove 6 is inevitably generated, an applied load 9 is first applied on the bump 5 via a pressing plate 8 made of a flat plate as shown in FIG. When the applied load 9 is further increased, the bump 5 gradually increases in plastic deformation as seen in FIG. A transition line generated on the slip surface inside the material is easily removed from the side surface of the bump 5 which is not restrained, and plastic deformation occurs when the transition line comes out. Since the bump 5 made of Au is a face-centered cubic crystal, the slip system in which plastic deformation occurs is four equivalent planes {111} and three equivalent slip directions <110>. There is a slip system, and the slip of the slip surface 14 (FIG. 4) on the crystal plane having the slip system caused by the shear stress causes the bump 5 to be in a direction perpendicular to the applied load direction, that is, the radius of the bump 5. Plastic deformation is performed so as to increase, and at the same time, plastic deformation is greatly performed in a direction parallel to the applied load direction, that is, in a direction of shortening the height of the bump 5. In the bump 5, the transition line generated inside the material easily escapes from the side surface with a large surface area, so the plastic deformability in the vicinity of the side surface is large, and conversely, as it goes to the inside with a distance from the body surface of the bump 5, That is, as it goes closer to the center, the transition line becomes difficult to come out, and plastic deformation becomes difficult.

従って上記理由から、図5に見るように押圧板10を除去した時、該バンプ5のバンプ表面7は周辺よりも、比較的弾性変形の多い中心部で弾性歪を回復することになり、結果として図6に見るように弾性歪の回復量の比較的多いバンプ5の中心部で塑性変形量が少ない、逆に該バンプ5の周辺部で塑性変形量が大きい形状に形成される。すなわち半球面化したバンプ形状に形成される。   Therefore, for the reason described above, when the pressing plate 10 is removed as shown in FIG. 5, the bump surface 7 of the bump 5 recovers the elastic strain at the central portion where the elastic deformation is relatively larger than the periphery. As shown in FIG. 6, the bump 5 is formed in a shape having a small plastic deformation amount at the center portion of the bump 5 having a relatively large elastic strain recovery amount, and conversely a large plastic deformation amount at the peripheral portion of the bump 5. That is, it is formed into a hemispherical bump shape.

上記過程を経た後、一方の基板1は塑性変形によって加工硬化したバンプ5を歪取り熱処理により軟化させる。そして、図7に見るように他方の基板に形成したAuパッド12と一方の基板のバンプ5の半球面化した表面7を相対向し、印加荷重9を印加することにより、室温においてバンプ5とパッド12は強固に接合する(図8)。   After going through the above process, one of the substrates 1 softens the bumps 5 that are work-hardened by plastic deformation by strain-removing heat treatment. Then, as shown in FIG. 7, the Au pad 12 formed on the other substrate and the hemispherical surface 7 of the bump 5 of one substrate are opposed to each other, and an applied load 9 is applied so that the bump 5 The pad 12 is firmly bonded (FIG. 8).

本実施例において、Auからなる50μm角及び高さ15μmのバンプ5を半球面化するためにSi基板8で該バンプ5を印加応力300Mpaで押圧し、この後250℃、1時間歪取り熱処理したところバンプ表面7は曲率半径で約30μmの半球面状に形成された。さらに該半球面化したサンプルを熱処理したところビッカース硬度約60以下にすることができた。この半球面化した該バンプ5とAuパッド12との間を常温接合したところ、室温で良好な接合が得られ、この後引張実験したところ約140Mpaの大きな破断応力を有する接合力を得た。   In this example, in order to make a 50 μm square and 15 μm high bump 5 made of Au into a hemispherical surface, the bump 5 was pressed with an applied stress of 300 Mpa with an Si substrate 8, and then subjected to heat treatment for removing strain at 250 ° C. for 1 hour. However, the bump surface 7 was formed in a hemispherical shape having a radius of curvature of about 30 μm. Further, when the hemispherical sample was heat-treated, the Vickers hardness could be reduced to about 60 or less. When this hemispherical bump 5 and Au pad 12 were bonded at room temperature, good bonding was obtained at room temperature. After that, a tensile test was performed to obtain a bonding force having a large breaking stress of about 140 Mpa.

本実施例において、該バンプのアスペクト比は0.3であったが、望ましくはバンプの側面から該転移線が抜け出やすいアスペクト比0.5以上を有するバンプ形状が望ましい。   In this embodiment, the aspect ratio of the bump was 0.3, but it is desirable that the bump shape has an aspect ratio of 0.5 or more at which the transition line can easily escape from the side surface of the bump.

本実施例においては、バンプ5として塑性変形の大きな材料であれば良く、例えばすべり系の多い面心立晶金属が望ましく、好ましくは大気中において酸化膜を有しないAuであり、この他にも、例えばAl、Cu、Snであっても良い。
In the present embodiment may be any material having a large plastic deformation as a bump 5, such as more face-centered elevational Akira Ho metal is preferably a slip system, preferably no oxide film in the atmosphere Au, In addition Also, for example, Al, Cu, or Sn may be used.

図9、図10、図11、図12、図13、図14は本発明の特徴を良く表す図面であり、同図において、1は一方のSi基板、2は一方のSi基板1に形成したSi酸化膜からなる絶縁膜、3は絶縁膜2の上に形成したAlからなる電気的な配線、4は絶縁膜2及び配線3の一部の上に形成した絶縁体からなるパッシベイション膜、5は配線3と電気的に結合したAuからなるバンプ、7は押圧板8で印加荷重9で押圧することによって形成したバンプ5の上部のバンプ表面、8はバンプ5の上部を押圧するための押圧板、9は押圧板に作用する印加荷重、11は他方のSi基板、12は他方のSi基板11上に形成したAuからなる電極としてのパッドである。   9, FIG. 10, FIG. 11, FIG. 12, FIG. 13 and FIG. 14 are drawings that clearly show the features of the present invention. In FIG. 9, 1 is formed on one Si substrate and 2 is formed on one Si substrate 1. Insulating film made of Si oxide film, 3 is an electrical wiring made of Al formed on the insulating film 2, and 4 is a passivation film made of an insulator formed on part of the insulating film 2 and the wiring 3. Reference numeral 5 denotes a bump made of Au electrically coupled to the wiring 3, 7 denotes a bump surface on the upper part of the bump 5 formed by pressing with the applied load 9 with the pressing plate 8, and 8 presses the upper part of the bump 5. , 9 is an applied load acting on the pressing plate, 11 is the other Si substrate, and 12 is a pad as an electrode made of Au formed on the other Si substrate 11.

次に上記構成において、Auメッキによって多数同時に形成されたバンプ5は、実施例1で述べたようにバンプ5の形成時にAuメッキ工程で上表面で溝形成を余儀なくされることから、まず押圧板8をバンプ5上に載置し、印加荷重9を加える。この荷重印加過程でバンプ5は実施例1で述べたように半球面状になる。この半球面状化現象はバンプ5の個数に関係なく生じ、単数のバンプ5においても、複数のバンプ5においても全てのバンプで同時に、かつ同様に生ずる。押圧板8を荷重印加する工程でバンプ5は実施例1で述べたのと同様に半球面化し、そして同時に平滑化され、図11に見るようにバンプ5の高さをほぼ均一化できる。しかしながら、本実施例における我々の行った実験においては、複数のバンプ5を平板からなる押圧板を用いて印加荷重9で押圧した場合、全面に渡って均一な高さではなく、基板1の中心部にあるバンプ5の高さは大きく、基板1の周縁部に進むに従って、すなわち半径方向に進むに従って該バンプ5の高さは次第に小さくなる。しかしながら、該バンプ5のバンプ表面7は半球面状に形成され、かつ同時に最表面層は平滑化された。そして、他方の基板11にパッド12を形成し、この後、図14に見るように基板11に印加荷重9を加えたところ強固な基板間の電極間接合が生じた。   Next, in the above configuration, a large number of bumps 5 formed simultaneously by Au plating are forced to form grooves on the upper surface in the Au plating process when the bumps 5 are formed as described in the first embodiment. 8 is placed on the bump 5 and an applied load 9 is applied. In this load application process, the bump 5 becomes hemispherical as described in the first embodiment. This hemispherical phenomenon occurs regardless of the number of the bumps 5, and occurs in all the bumps at the same time in the single bump 5 or the plurality of bumps 5. In the step of applying a load to the pressing plate 8, the bumps 5 become hemispherical as described in the first embodiment and are smoothed at the same time, and the height of the bumps 5 can be made substantially uniform as seen in FIG. However, in our experiment in this embodiment, when a plurality of bumps 5 are pressed with an applied load 9 using a flat pressing plate, the center of the substrate 1 is not uniform over the entire surface. The height of the bump 5 in the portion is large, and the height of the bump 5 gradually decreases as it goes to the peripheral portion of the substrate 1, that is, in the radial direction. However, the bump surface 7 of the bump 5 was formed in a hemispherical shape, and at the same time, the outermost surface layer was smoothed. Then, a pad 12 was formed on the other substrate 11, and then, as shown in FIG. 14, when an applied load 9 was applied to the substrate 11, strong inter-electrode bonding occurred between the substrates.

本実施例において、2048個の複数からなるバンプ5を平板状押圧板で荷重印加したところ全てのバンプで半球面状に変形した。この後、この半球面状に変形したバンプ5を有すSi基板1を、250℃、1時間歪取りの熱処理を行い、この後Arイオンプラズマエッチングによって両接合表面、すなわちバンプ5及びパッド12の接合表面を洗浄し、この後図14に見るように室温で印加荷重9を加えたところ、バンプ5を有するSi基板1及びパッド12を有するSi基板11は強固に接合した。   In this embodiment, when 2048 bumps 5 consisting of a plurality of bumps were applied with a flat pressing plate, all the bumps were deformed into a hemispherical shape. Thereafter, the Si substrate 1 having the bumps 5 deformed into the hemispherical shape is subjected to heat treatment for removing strain at 250 ° C. for 1 hour, and thereafter, both of the bonding surfaces, that is, the bumps 5 and the pads 12 are formed by Ar ion plasma etching. After the bonding surfaces were cleaned and an applied load 9 was applied at room temperature as shown in FIG. 14, the Si substrate 1 having bumps 5 and the Si substrate 11 having pads 12 were firmly bonded.

本実施例において、バンプ5は2048個であり、寸法においては19μm角の矩形断面、高さ15μmであり、半球面化のために印加荷重9を印加したとき、全てのバンプ5のバンプ表面7は約30μmの曲率半径を有する半球面状に形成されていた。同時に溝6の残留もなく平滑なバンプ表面7を得ることができた。   In this embodiment, the number of bumps 5 is 2048, the size is a rectangular cross section of 19 μm square, the height is 15 μm, and when an applied load 9 is applied for making a hemisphere, the bump surfaces 7 of all the bumps 5 are applied. Was formed in a hemispherical shape having a radius of curvature of about 30 μm. At the same time, a smooth bump surface 7 without residual grooves 6 could be obtained.

尚、本実施例において、バンプの断面形状は矩形であったが、この他にも例えば円形状、多角形状で良い。   In the present embodiment, the cross-sectional shape of the bumps is rectangular.

図15、図16、図17、図18、図19、図20、図21、図22、図23は本発明の特徴を良く表す図面であり、同図において、1は一方のSi基板、5は一方の基板1の配線(図示なし)と電気的に結合したAuからなるバンプ、8はバンプ5の上部を押圧するための押圧板、9は押圧板に作用する印加荷重、13は基板1に形成した補助バンプ、15はバンプ13の高さを調整するために用いる押圧板である。   15, FIG. 16, FIG. 17, FIG. 18, FIG. 19, FIG. 20, FIG. 21, FIG. 22, and FIG. 23 are drawings that clearly show the features of the present invention. Is a bump made of Au electrically coupled to the wiring (not shown) of one substrate 1, 8 is a pressing plate for pressing the upper portion of the bump 5, 9 is an applied load acting on the pressing plate, and 13 is a substrate 1 Auxiliary bumps 15 and 15 are pressing plates used to adjust the height of the bumps 13.

次に上記構成において、Auメッキによって多数同時に形成されたバンプ5及び補助バンプ13は、高さが一定でなく凹凸に富んでいるため、まず始めに図16に見るように押圧板15を用いて印加荷重9で押圧して必要とする高さまで押し込む(図17)。そしてこの後、図18に見るように、バンプ5の上に押圧板8を載置して印加荷重9で押し込んで行き、予め必要とする高さまで高さ調整した補強バンプ13の高さに到達した時、該印加荷重9の押し込みを停止する(図18)。この高さ調整工程によって、図19に見るようにバンプ5の高さは補助バンプ13の高さに成形される。さらに、図20に見るように該補助バンプ13を該補強バンプ13の上に押圧板15を載置し、印加荷重9で押し込んで行き、他方の基板11のパッド12と一方の基板1のバンプ5の接合時に塑性変形するバンプ5の高さよりも、予め低くなるまで押し込む(図21)。そして、実施例1及び実施例2と同様にArイオンプラズマによって各接合表面を清浄し、この後一方の基板1のバンプ5と他方の基板11のパッド12が相対向する位置に整合し、そして重畳し、この後室温においてSi基板1とSi基板11の両Si基板の両側から印加荷重9を印加押することによってパッド12とバンプ5を接合した。   Next, in the above configuration, the bumps 5 and auxiliary bumps 13 formed simultaneously by Au plating are not uniform in height but rich in irregularities. First, as shown in FIG. 16, the pressing plate 15 is used. It is pressed with the applied load 9 to the required height (FIG. 17). Then, as shown in FIG. 18, the pressing plate 8 is placed on the bump 5 and pushed in with the applied load 9 to reach the height of the reinforcing bump 13 whose height has been adjusted to the required height in advance. Then, the pushing of the applied load 9 is stopped (FIG. 18). By this height adjustment step, the height of the bump 5 is formed to the height of the auxiliary bump 13 as shown in FIG. Further, as shown in FIG. 20, a pressing plate 15 is placed on the auxiliary bump 13 on the reinforcing bump 13 and pushed with an applied load 9, and the pad 12 of the other substrate 11 and the bump of one substrate 1 are pressed. The bump 5 is pushed in until it becomes lower than the height of the bump 5 that is plastically deformed at the time of joining (FIG. 21). Then, the bonding surfaces are cleaned with Ar ion plasma in the same manner as in Example 1 and Example 2, and then the bumps 5 of one substrate 1 and the pads 12 of the other substrate 11 are aligned with each other, and Then, the pads 12 and the bumps 5 were joined by applying and applying the applied load 9 from both sides of the Si substrate 1 and the Si substrate 11 at room temperature.

本実施例において、メッキによって作製したバンプ5と補助バンプ13の高さは何れも高さ約15μmあり、補助バンプを用いて上記のようにバンプ5の高さを約13μmに高さ調整し、この後さらに該補助バンプ13の高さを上記方法で5μmに調整し、そして予めパッド12とバンプ5の両表面をArイオンプラズマエッチングにより洗浄し、さらに該両表面を常温接合したところ、強固に接合した。この後、接合強度試験を行ったところ、引張破壊強度180Mpaの大きな接合強度を得た。尚、破面観察したところ、バンプ5とパッド12は全てに渡って接合されていた。そして、Si基板1とSi基板11に形成した引き出し電極(図示なし)を用いて電気的な導通を確認した。   In this example, the height of the bump 5 and the auxiliary bump 13 produced by plating are both about 15 μm in height, and the height of the bump 5 is adjusted to about 13 μm as described above using the auxiliary bump. Thereafter, the height of the auxiliary bump 13 is further adjusted to 5 μm by the above method, and both surfaces of the pad 12 and the bump 5 are previously cleaned by Ar ion plasma etching and further bonded at room temperature, Joined. Thereafter, when a bonding strength test was performed, a large bonding strength of 180 Mpa was obtained. When the fracture surface was observed, the bump 5 and the pad 12 were bonded all over. Then, electrical continuity was confirmed using lead electrodes (not shown) formed on the Si substrate 1 and the Si substrate 11.

以上説明したように本発明は、一方の基板の配線上にメッキによって形成した複数の電極バンプを平板からなる押圧板で押圧することによって、微少な凹凸及びバンプ上部の表面に形成を余儀なくされた溝を平滑化し、かつ該押圧過程によって生ずる塑性変形はバンプの半径方向に進むに従って増して行き、そして該塑性変形により該バンプ上部の表面を半球面化し、同時に平滑化し、この後歪取り熱処理によって該バンプを軟化させ、該両接合表面をArイオンプラズマエッチングによって清浄化し、この後一方のSi基板のバンプと他方のSi基板のパッド間の常温接合において、該バンプと該パッドの接合時の接触は該バンプの半球面状の中心部でまず開始し、次第に該バンプの半径方向へと進んでいき、この過程で該バンプの塑性変形は進行し、同時に接合が行われるため、該バンプ全面に渡って強固に接合が行われる。本接合は室温で行う常温接合であるため、線膨張係数の異なる基板間の接合も可能になる。   As described above, in the present invention, a plurality of electrode bumps formed by plating on the wiring of one substrate are pressed with a pressing plate made of a flat plate, so that it is inevitably formed on the surface of minute bumps and bumps. The plastic deformation caused by the smoothing of the groove and the pressing process increases as it proceeds in the radial direction of the bump, and the surface of the upper part of the bump is made hemispherical by the plastic deformation, and at the same time, smoothed. The bumps are softened, both the bonding surfaces are cleaned by Ar ion plasma etching, and then contact at the time of bonding of the bumps and the pads is performed at room temperature bonding between the bumps of one Si substrate and the pads of the other Si substrate. Starts at the center of the hemispherical surface of the bump and gradually proceeds in the radial direction of the bump. In this process, the plastic deformation of the bump Because proceeds, bonding is performed simultaneously, firmly bonded over the said bump entirely is performed. Since this bonding is room temperature bonding performed at room temperature, bonding between substrates having different linear expansion coefficients is also possible.

本発明の実施例1の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 1 of this invention. 本発明の実施例1の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 1 of this invention. 本発明の実施例1の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 1 of this invention. 本発明の実施例1のバンプ電極を平板で押圧する時、図3におけるバンプ電極側面A部の拡大図である。FIG. 4 is an enlarged view of a bump electrode side surface portion A in FIG. 3 when the bump electrode of Example 1 of the present invention is pressed with a flat plate. 本発明の実施例1の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 1 of this invention. 本発明の実施例1の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 1 of this invention. 本発明の実施例1の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 1 of this invention. 本発明の実施例1の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 1 of this invention. 本発明の実施例2の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 2 of this invention. 本発明の実施例2の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 2 of this invention. 本発明の実施例2の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 2 of this invention. 本発明の実施例2の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 2 of this invention. 本発明の実施例2の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 2 of this invention. 本発明の実施例2の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 2 of this invention. 本発明の実施例3の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 3 of this invention. 本発明の実施例3の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 3 of this invention. 本発明の実施例3の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 3 of this invention. 本発明の実施例3の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 3 of this invention. 本発明の実施例3の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 3 of this invention. 本発明の実施例3の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 3 of this invention. 本発明の実施例3の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 3 of this invention. 本発明の実施例3の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 3 of this invention. 本発明の実施例3の基板間電極間接合方法及び構造を説明する図である。It is a figure explaining the joining method and structure between board | substrate electrodes of Example 3 of this invention.

符号の説明Explanation of symbols

1、11 Si基板
2 絶縁体膜
3 配線
4 パッシべイション膜
5 バンプ
6 溝
7 バンプ表面
8、15 押圧板
9 印加荷重
10 除去荷重
12 パッド
13 補助バンプ
14 すべり面
DESCRIPTION OF SYMBOLS 1, 11 Si substrate 2 Insulator film 3 Wiring 4 Passivation film 5 Bump 6 Groove 7 Bump surface 8, 15 Press plate 9 Applied load 10 Removal load 12 Pad 13 Auxiliary bump 14 Slip surface

Claims (5)

面心立方晶金属からなり、バンプ上部の表面の表面積よりもバンプ側面の表面積が大きく、前記バンプ上部の表面中央部に溝が形成された電極バンプがメッキにより形成された基板を用意する工程と、
前記電極バンプを上部から平板で押圧し、前記電極バンプの上部の表面を半球面化する工程と、を備えたことを特徴とする電極バンプが形成された基板の製造方法。
Consist face-centered cubic metal, the surface area of the bump side than the surface area of the bump top surface is rather large, the step of the bump top surface central electrode bumps grooves are formed in the providing a substrate which is formed by plating When,
And a step of pressing the electrode bump from above with a flat plate to make the upper surface of the electrode bump hemispherical. A method of manufacturing a substrate on which an electrode bump is formed.
前記面心立方晶金属が、Au、Al、Cu、Sn又はこれらの合金の何れかであることを特徴とする請求項1記載の製造方法。 2. The manufacturing method according to claim 1, wherein the face-centered cubic metal is any one of Au, Al, Cu, Sn, and alloys thereof. 前記電極バンプを平板で押圧する工程の後に、前記電極バンプが形成された基板を熱処理することを特徴とする請求項1記載の製造方法。   The manufacturing method according to claim 1, wherein the substrate on which the electrode bump is formed is heat-treated after the step of pressing the electrode bump with a flat plate. 前記電極バンプの半球面化する工程は、前記電極バンプの側面から転移線が抜け出ることによって、前記バンプが塑性変形し、該塑性変形は、前記バンプ側面が前記バンプ中央部よりも大きいことを特徴とする請求項1記載の製造方法。   The step of making the electrode bumps hemispherical is characterized in that the transition line is pulled out from the side surface of the electrode bump, so that the bump is plastically deformed, and the plastic deformation is such that the bump side surface is larger than the bump central portion. The manufacturing method according to claim 1. 面心立方晶金属からなり、バンプ上部の表面の表面積よりもバンプ側面の表面積が大きく、前記バンプ上部の表面中央部に溝が形成された電極バンプがメッキにより形成された基板と、パッドが形成された基板を用意する工程と、
前記電極バンプが形成された基板と前記パッドが形成された基板とを相対向し、前記両基板を押圧することにより、前記電極バンプと前記パッドとを接合する工程とを備え、
前記電極バンプと前記パッドとの接合の前に、前記電極バンプを上部から平板で押圧し、前記電極バンプの上部の表面を半球面化する工程を備えることを特徴とする電極バンプが形成された基板の接合方法。
Consist face-centered cubic metal, the surface area of the bump side than the surface area of the bump top surface is rather large, the substrate on which the electrode bumps grooves in the center part of the surface of the bump top is formed is formed by plating, pad Preparing a formed substrate; and
The substrate on which the electrode bump is formed and the substrate on which the pad is formed are opposed to each other, and by pressing both the substrates, the electrode bump and the pad are joined.
Before the bonding of the electrode bump and the pad, the electrode bump is formed by pressing the electrode bump with a flat plate from above to make the upper surface of the electrode bump hemispherical. Substrate bonding method.
JP2004169982A 2004-06-08 2004-06-08 Substrate manufacturing method and bonding method Expired - Fee Related JP4416574B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004169982A JP4416574B2 (en) 2004-06-08 2004-06-08 Substrate manufacturing method and bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004169982A JP4416574B2 (en) 2004-06-08 2004-06-08 Substrate manufacturing method and bonding method

Publications (3)

Publication Number Publication Date
JP2005353670A JP2005353670A (en) 2005-12-22
JP2005353670A5 JP2005353670A5 (en) 2007-07-19
JP4416574B2 true JP4416574B2 (en) 2010-02-17

Family

ID=35587907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004169982A Expired - Fee Related JP4416574B2 (en) 2004-06-08 2004-06-08 Substrate manufacturing method and bonding method

Country Status (1)

Country Link
JP (1) JP4416574B2 (en)

Also Published As

Publication number Publication date
JP2005353670A (en) 2005-12-22

Similar Documents

Publication Publication Date Title
KR102121176B1 (en) Method for producing semiconductor package
JP4901933B2 (en) Manufacturing method of semiconductor device
WO2012113297A1 (en) Multi-layer hybrid synchronous bonding structure and method for three-dimensional packaging
WO2008109524A2 (en) System and method for increased stand-off height in stud bumping process
JP4036786B2 (en) Electronic component mounting method
JP5117169B2 (en) Semiconductor device
EP1978559A2 (en) Semiconductor device
JP5906022B2 (en) Macropin hybrid interconnect array and manufacturing method thereof
JP5919641B2 (en) Semiconductor device, method for manufacturing the same, and electronic device
US7994638B2 (en) Semiconductor chip and semiconductor device
EP0789392B1 (en) Bumpless method of attaching inner leads to semiconductor integrated circuits
JP4416574B2 (en) Substrate manufacturing method and bonding method
JP4035138B2 (en) Flip chip mounting method
KR101750206B1 (en) Heating header of semiconductor mounting apparatus and bonding method for semiconductor
CN101452901B (en) Micro link lug structure with stress buffer and its producing method
JP2709504B2 (en) Semiconductor element connection structure
KR102181706B1 (en) Method for producing semiconductor chip
JP4154379B2 (en) Interelectrode bonding method and structure between substrates
CN100514615C (en) Producing method of micro link lug structure with stress buffer
JPH03228339A (en) Bonding tool
JPH0350736A (en) Manufacture of bump of semiconductor chip
JP4289912B2 (en) Inter-substrate wiring electrode bonding method
JP2007324211A (en) Method of forming bump-shaped connecting member
US20220399302A1 (en) Substrate bonding
WO2009145196A1 (en) Semiconductor chip, intermediate substrate and semiconductor device

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070531

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070531

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090529

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090602

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090730

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090825

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091021

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20091117

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20091124

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121204

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131204

Year of fee payment: 4

LAPS Cancellation because of no payment of annual fees