JP4410531B2 - Silicon carbide semiconductor substrate and method for manufacturing the same - Google Patents

Description

  The present invention relates to a silicon carbide (SiC) substrate and a manufacturing method thereof, and more particularly to a manufacturing method in which dislocations that are crystal defects are not propagated to a semiconductor element layer (epitaxial layer).

  A SiC single crystal is generally manufactured by a sublimation method, and the manufactured single crystal includes dislocations (edge dislocations, spiral dislocations (including micropipes)). That is, the generation of the SiC substrate proceeds by deposition of sublimated SiC, but the deposition of SiC proceeds along the wall surface. Will occur. This is a dislocation.

  When manufacturing a power device or a high-frequency device, this SiC single crystal is used as a substrate, and an epitaxial layer (semiconductor element layer), which is a region for forming the device, is grown so as to have a structure suitable for the device. If present, the dislocation is inherited by the epitaxial layer grown thereon, and almost the same number of dislocations are formed in the epitaxial layer. It has been reported that when a device (element) is produced in an epitaxial layer having this dislocation, the leakage current of the device is increased and the reverse breakdown voltage is lowered (see FIG. 1).

  For this reason, it is extremely important to reduce this dislocation in order to produce a device.

  As a method for reducing the micropipe of the epitaxial layer, which is the device fabrication region, it was proposed that SiC single crystal as a substrate is treated at high temperature, so that SiC sublimes and precipitates and closes in the micropipe (patent) Reference 1). Also, a method of growing SiC by a CVD (Chemical Vapor Deposition) method, closing an end of a micropipe by heat treatment, exposing a surface blocked by thermal etching, and growing a SiC single crystal using this as a seed crystal There is also (refer patent document 2).

However, in these methods, although the micropipe is partially blocked, it is converted into a large number of dislocations, and the above problem cannot be solved.
JP 2002-179498 A JP 2000-53498 A

  Accordingly, an object of the present invention is to obtain a silicon carbide semiconductor substrate having few dislocations in an epitaxial layer which is a region for producing a device, and to obtain a semiconductor having no defect.

  In view of such a situation, the present inventor has conducted extensive research and found that dislocation to the epitaxial layer is suppressed by providing a buffer layer on the silicon carbide substrate, bending the dislocation, and opening the dislocation by a slit (groove). As a result, the present invention has been completed.

  That is, the present invention provides the following method and the like.

<1> A SiC layer having slits is buffered by forming a SiC layer on the silicon carbide substrate after digging a groove in the silicon carbide substrate on the silicon carbide substrate and providing a growth inhibiting layer in the groove. A method for producing a silicon carbide semiconductor substrate, comprising: providing a SiC layer as a semiconductor element layer on the buffer layer. Dislocations from the substrate are bent by the buffer layer and opened by a slit on the side of the buffer layer or / and a slit on the side of the semiconductor element layer.

< 2 > A step of growing a 3C-SiC layer and a step of growing a 4H-SiC layer are each provided at least once, and at least one 3C-SiC layer and at least one 4H-SiC layer are stacked to The method for producing a silicon carbide semiconductor substrate according to <1 >, wherein the buffer layer is provided.
< 3 > a step of growing a SiC layer into which a doping amount of N ₂ gas having a carrier concentration of 3 × 10 ¹⁸ cm ⁻³ or more is grown, and a doping amount of a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or less. <1 >, wherein the step of growing the SiC layer into which N ₂ gas is introduced is provided at least once, and the buffer layer is provided by superposing at least two types of SiC impurity doped layers having different doping amounts. A method for manufacturing a substrate.

< 4 > Different from silicon carbide substrate, at least one 3C-SiC layer and at least one 4H-SiC layer provided on the silicon carbide substrate, or a carrier concentration threshold of 3 × 10 ¹⁸ cm ⁻³ A buffer layer having a slit having at least two SiC impurity doped layers into which a doping amount of N ₂ gas is introduced, and a SiC layer which is a semiconductor element layer provided on the buffer layer A silicon carbide semiconductor substrate.
< 5 > The silicon carbide semiconductor substrate according to < 4 >, wherein the semiconductor element layer is a SiC layer having a slit continuous with a slit of the SiC layer that is the buffer layer.

< 6 > A silicon carbide semiconductor comprising the silicon carbide semiconductor substrate according to < 4 > or < 5 > and an electrode.

  The semiconductor obtained by the present invention has few dislocations in the epitaxial layer, little device leakage current, and little reduction in reverse breakdown voltage.

  Embodiments to which the present invention is applied will be specifically described below with reference to the drawings. In the present embodiment, for example, a silicon carbide single crystal substrate (SiC single crystal substrate) formed by a sublimation method or the like is applied to a field effect transistor (MOSFET or the like), a junction field effect transistor (JFET), or a Schottky barrier diode. This is applied to a method of manufacturing an epitaxial growth substrate for forming a device.

(First embodiment)
FIG. 2 shows one embodiment of a silicon carbide semiconductor substrate obtained by the method of the present invention.

The manufacturing process is as follows.
First, the SiC substrate 1 is obtained. Examples of the SiC substrate include 4H-SiC wafer surface crystal plane orientation (0001) 8 ° off [-1-120].

(1) In this embodiment, grooves are first formed on the SiC substrate 1.
(2) Next, the growth inhibiting layer 5 is provided in this groove. The growth inhibiting layer 5 is a layer for inhibiting the growth of the buffer layer and the epitaxial layer to be formed later and forming the slit 4, and amorphous SiN is preferable.

(3) The buffer layer 2 is provided on the SiC substrate 1 by the CVD method.
The buffer layer 2 is a layer for bending dislocations from the SiC substrate 1. In order to bend dislocations, there are thermal stress, distortion due to lattice irregularity, defects due to impurity doping, and the like. Specifically, the following methods can be mentioned.

A) Thermal cycle annealing This is a method in which an SiC layer is formed and this is repeated several times at 1000 ° C. and 1600 ° C. in a C ₃ H ₈ and H ₂ atmosphere.

B) Thermal cycle growth In the formation of the buffer layer, after a constant film thickness is grown at a constant temperature, a constant film thickness is grown at a different temperature, and this is repeated.

C) 3C-SiC
A layer thickness of several tens of nanometers is grown at a wafer temperature of 1200 ° C. by CVD. Thereby, a 3C-SiC layer is formed.
Next, a layer thickness of several tens of nm is grown at a wafer temperature of 1600 ° C. Thereby, 4H-SiC is formed.
By repeating these several times, the dislocation is bent while forming the buffer layer.

D) 4H-SiC impurity doping 1) Growing a thickness of several tens of nanometers of SiC by introducing a doping amount of N ₂ gas with a carrier concentration of 3 × 10 ¹⁸ cm ⁻³ or more at a wafer temperature of 1500 ° C. by CVD To do.

Thereby, the impurity doping layer I is formed.
2) A CVD layer is used to grow a SiC layer having a thickness of several tens of nanometers into which a doping amount of N ₂ gas having a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or less is introduced at a wafer temperature of 1500 ° C.
Thereby, the impurity doping layer II is formed.
3) A method of bending or terminating dislocations while forming a buffer layer by repeating 1) and 2) several times.

  In the buffer layer 2 obtained in this way, a slit 4 is formed by the growth inhibiting layer 5. By doing so, dislocations bent by the buffer layer are released by the slits 4, and dislocations propagating to the epitaxial layer (semiconductor element layer) 3 are reduced.

(4) The epitaxial growth layer 3 is provided on the buffer layer 2 by the CVD method. This may be done by conventional methods. This layer also has a slit 4 formed by the growth inhibiting layer 5.
Thus, the silicon carbide semiconductor substrate shown in FIG. 2 is obtained.

( Reference form 1 )
Reference form 1 is a form as shown in FIG. The difference from the first embodiment is that the groove of the SiC substrate is widened and no growth inhibiting layer is provided. In this way, the dislocation may reach the epitaxial layer 3, but if it does not reach the surface, it can be put to practical use. Since no growth inhibiting layer is provided, this step is eliminated and the cost can be reduced.

( Reference form 2 )
As shown in FIG. 4, the reference form 2 is provided with the growth inhibiting layer 5 on the SiC substrate without providing the first groove formed on the SiC substrate 1, and thereafter in the same manner as in the first embodiment. is there. According to this method, the step of forming a groove on the SiC substrate first can be omitted, and the cost can be reduced.

Above, the silicon carbide semiconductor substrate obtained by the first implementation embodiment and Reference Embodiments 1 and 2, as shown in FIG. 7, by arranging the electrodes, the semiconductor element is completed. That is, if the gate electrode 12 is provided in the slit 4, the source electrode 11 is provided on the epitaxial layer 3, and the drain electrode 10 is provided below the SiC substrate 1, a semiconductor element is completed. In Reference Mode 1 , it is preferable to provide an insulating layer such as SiO ₂ at the dislocation portion and provide the gate electrode on the dislocation portion so that the gate electrode does not contact the dislocation portion.

Example 1 (Manufacture of the silicon carbide semiconductor substrate of the first embodiment, see FIG. 5)
(1) Formation of mesa (groove for slit) of SiC substrate As a substrate, 4H-SiC substrate: wafer surface crystal plane orientation (0001) 8 ° off [-1-120] was used.

Slit Forming Method 1) SiO ₂ (film thickness 300 nm) is formed on the surface of the 4H—SiC substrate by plasma CVD (FIG. 5A).
2) A photoresist is formed by a photolithography process so as to open a portion where the slit portion is to be formed (FIG. 5B).
3) Using the photoresist as a mask, the SiO ₂ layer at the opening is etched and removed by dry etching.
4) The photoresist of the SiO ₂ processing mask is removed by an ashing process (such as 0 ₂ plasma).

5) Using the SiO ₂ as an etching mask, the SiC in the SiO ₂ opening is etched by dry etching (FIG. 5C).
6) Only mask SiO ₂ is selectively removed by dry etching or wet etching (HF solution) (FIG. 5D).

(2) Formation of slits (grooves) of amorphous SiN by plasma CVD (FIG. 5E).
1) Amorphous SiN is formed on the surface of the 4H-SiC substrate by plasma CVD.
2) A photoresist is formed by the photolithography process so as to leave amorphous SiN in the slit portion.
3) The amorphous SiN layer in the opening is etched and removed by dry etching using the photoresist as a mask.
4) The photoresist ashing process (such as 0 ₂ plasma), is removed.
(3) Formation of the buffer layer (SiC layer) by the CVD method (FIG. 5F).

The CVD conditions are as follows.
Source gas: SiH ₄ 10 cc / min, C ₃ H ₈ 10 cc / min, carrier gas: H ₂ 10 L / min, conductivity control gas: N ₂ (diluted to 5% N ₂ with H ₂ gas) 100 cc / min, wafer temperature: 1400-1600 ° C.
Next, thermal cycle annealing is performed. As annealing conditions, a wafer temperature of 1000 ° C. to 1600 ° C. is repeated several times in a C ₃ H ₈ + H ₂ atmosphere.
(4) A semiconductor element layer (SiC epitaxial layer) is formed by a CVD method (FIG. 5G). The CVD conditions were the same as (3) except that N ₂ 100 cc was changed to 1 cc / min.

Reference Example 2 (Manufacture of silicon carbide semiconductor substrate of Reference Form 1 , see FIG. 3)
A silicon carbide semiconductor substrate of Reference Mode 1 was obtained in the same manner as in Example 1 except that the step of forming amorphous SiN was omitted.

Example 3 (Semiconductor element structure: manufacturing to SIT (electrostatic induction transistor), FIG. 6)
(1) An insulating film (SiO ₂ or SiN) is formed by a plasma CVD method or the like so as not to directly contact the buffer layer in the slit (groove) portion of the silicon carbide semiconductor substrate obtained in Example 1 (FIG. 6A). .
(2) A resist is formed by a photolithography process so as to open a portion where a source electrode is to be formed while covering the buffer layer portion with an insulating film (SiO ₂ , SiN, etc.) (FIG. 6B).
(3) Open an insulating film (SiO ₂ , SiN, etc.) where a source electrode is to be formed by dry etching or wet etching.
(4) Ni is vapor-deposited on the wafer surface (source electrode formation surface) by sputtering vapor deposition or electron beam vapor deposition as an electrode material capable of obtaining ohmic characteristics.
(5) The Ni vapor deposition film other than the source electrode formation region is removed by dissolving the resist with an organic solvent such as acetone. (Lift-off process) (FIG. 6C)
(6) Ni is vapor-deposited on the wafer back surface (drain electrode formation surface) by sputtering vapor deposition or electron beam vapor deposition as an electrode material that can achieve ohmic characteristics (FIG. 6D).
(7) The ohmic characteristics of the source and drain electrodes are ensured by heating to 1000 ° C. for several minutes in an Ar or H ₂ atmosphere.
(8) A gate electrode (Ti / Al, Ni, or the like) is formed on the wafer surface side (source and gate electrode side) by a sputtering deposition method or an electron beam deposition method.
(9) A photoresist is formed in a pattern shape that forms a lead wiring together with the gate electrode by a photolithography process, and the gate electrode (Ti / Al or Ni) formed in (8) is formed by dry etching or wet etching. The film is processed, and the photoresist is removed by an ashing process (FIG. 6E).

  As described above, the element structure is formed by the process. Usually, in order to lower the electrode resistance, an electrode film is further formed and processed, or a protective film (insulating film) is formed.

Example 4 (Method of bending dislocation: a) Thermal cycle growth)
A silicon carbide semiconductor substrate was obtained in the same manner as in Example 1 except that (3) in Examples 1 and 2 was changed to the following steps.
1) A layer thickness of several tens of nm is grown by a CVD method at a wafer temperature of 1400 ° C.
2) A layer thickness of several tens of nm is grown at a wafer temperature of 1600 ° C.
3) By repeating steps 1) and 2) several times, dislocations were bent while forming a buffer layer.

Example 5 (Method of bending dislocation: c) 3C-SiC layer)
A silicon carbide semiconductor substrate was obtained in the same manner as in Example 1 except that (3) in Examples 1 and 2 was changed to the following steps.
l) A layer thickness of several tens of nm is grown at a wafer temperature of 1200 ° C. by CVD. Thereby, a 3C-SiC layer is formed.
2) A layer thickness of several tens of nm is grown at a wafer temperature of 1600 ° C. Thereby, 4H-SiC is formed.
3) By repeating steps 1) and 2) several times, dislocations were bent while forming a buffer layer.

Example 6 (Method of bending dislocation: d) 4H-SiC impurity doped layer)
A silicon carbide semiconductor substrate was obtained in the same manner as in Example 1 except that (3) in Examples 1 and 2 was changed to the following steps.

1) A SiC layer having a carrier thickness of 3 × 10 ¹⁸ cm ⁻³ or more introduced with a doping amount of N ₂ gas at a wafer temperature of 1500 ° C. is grown by a thickness of several tens of nanometers by CVD. Thereby, the impurity doping layer I is formed.
2) A CVD layer is used to grow a SiC layer having a thickness of several tens of nanometers into which a doping amount of N ₂ gas having a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or less is introduced at a wafer temperature of 1500 ° C. Thereby, the impurity doping layer II is formed.
3) By repeating steps 1) and 2) several times, dislocations were bent or terminated while forming a buffer layer.

Results The defect density of the [3 epitaxial layer] of the conventional substrate grown without providing the buffer layer was 1000 cm −2 or more, but according to the present invention (Examples 1, 2, 4, and 5), the [3 epitaxial layer] The defect density was reduced to 100 cm-2 or less.

  The present invention can be applied to other element structures such as Schottky barrier diodes (FIG. 8), MOSFETs, JFETs, etc. in addition to the above embodiments.

  According to the present invention, a substrate with less dislocations in the semiconductor element layer that increases the leakage current of the device and decreases the reverse breakdown voltage can be obtained.

It is a figure which shows the cross section of the conventional semiconductor element. It is a figure which shows the cross section of the silicon carbide semiconductor substrate of this invention. It is a figure which shows the cross section of the silicon carbide semiconductor substrate of this invention. It is a figure which shows the cross section of the silicon carbide semiconductor substrate of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor substrate of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor of this invention. It is a figure which shows the cross section of the silicon carbide semiconductor of this invention. It is a figure which shows the cross section of the silicon carbide semiconductor of this invention.

Explanation of symbols

1 SiC substrate 2 Buffer layer 3 Epitaxial layer 4 Slit 5 Growth inhibiting layer 6 Dislocation 7 SiO ₂
8 Photoresist 10 Drain electrode 11 Source electrode 12 Gate electrode 13 Insulating layer 14 Anode electrode 15 Cathode electrode

Claims (6)

A SiC layer with slits is provided as a buffer layer by digging a groove in the silicon carbide substrate on the silicon carbide substrate and forming a SiC layer on the silicon carbide substrate after providing a growth inhibiting layer in the groove. And then providing a SiC layer as a semiconductor element layer on the buffer layer. A step of growing a 3C-SiC layer and a step of growing a 4H-SiC layer are each provided at least once, and at least one 3C-SiC layer and at least one 4H-SiC layer are stacked to form the buffer layer. The method for manufacturing a silicon carbide semiconductor substrate according to claim 1 . A step of doping amount of _{N 2} gas carrier concentration of 3 × ¹⁰ 18 ^{cm -3} or more is grown a SiC layer introduced, doping amount of _{N 2} gas carrier concentration of 1 × ¹⁰ 18 ^{cm -3} or less 2. The production of the silicon carbide semiconductor substrate according to claim 1, wherein the step of growing the SiC layer into which silicon is introduced is provided at least once, and the buffer layer is provided by superposing at least two kinds of SiC impurity doped layers having different doping amounts. Method. A silicon carbide substrate and at least one 3C-SiC layer and at least one 4H-SiC layer provided on the silicon carbide substrate, or different doping amounts with a carrier concentration threshold of 3 × 10 ¹⁸ cm ⁻³ A silicon carbide comprising: a buffer layer having a slit having at least two SiC impurity doped layers into which N ₂ gas has been introduced; and a SiC layer which is a semiconductor element layer provided on the buffer layer Semiconductor substrate. The silicon carbide semiconductor substrate according to claim 4 , wherein the semiconductor element layer is a SiC layer having a slit continuous with a slit of the SiC layer that is the buffer layer. A silicon carbide semiconductor comprising the silicon carbide semiconductor substrate according to claim 4 or 5 and an electrode.

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