JP4390728B2 - ネットリスト生成装置 - Google Patents

ネットリスト生成装置 Download PDF

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Publication number
JP4390728B2
JP4390728B2 JP2005048775A JP2005048775A JP4390728B2 JP 4390728 B2 JP4390728 B2 JP 4390728B2 JP 2005048775 A JP2005048775 A JP 2005048775A JP 2005048775 A JP2005048775 A JP 2005048775A JP 4390728 B2 JP4390728 B2 JP 4390728B2
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Japan
Prior art keywords
memory cell
circuit
net list
information
cell array
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Expired - Fee Related
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JP2005048775A
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English (en)
Japanese (ja)
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JP2006235920A5 (enExample
JP2006235920A (ja
Inventor
俊幾 金本
光利 白田
美智子 内村
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Renesas Technology Corp
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Renesas Technology Corp
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Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2005048775A priority Critical patent/JP4390728B2/ja
Priority to TW095104992A priority patent/TW200643753A/zh
Priority to US11/358,101 priority patent/US7398506B2/en
Publication of JP2006235920A publication Critical patent/JP2006235920A/ja
Publication of JP2006235920A5 publication Critical patent/JP2006235920A5/ja
Priority to US12/213,623 priority patent/US7979817B2/en
Application granted granted Critical
Publication of JP4390728B2 publication Critical patent/JP4390728B2/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2005048775A 2005-02-24 2005-02-24 ネットリスト生成装置 Expired - Fee Related JP4390728B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2005048775A JP4390728B2 (ja) 2005-02-24 2005-02-24 ネットリスト生成装置
TW095104992A TW200643753A (en) 2005-02-24 2006-02-15 Net list producing device
US11/358,101 US7398506B2 (en) 2005-02-24 2006-02-22 Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing
US12/213,623 US7979817B2 (en) 2005-02-24 2008-06-23 Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005048775A JP4390728B2 (ja) 2005-02-24 2005-02-24 ネットリスト生成装置

Publications (3)

Publication Number Publication Date
JP2006235920A JP2006235920A (ja) 2006-09-07
JP2006235920A5 JP2006235920A5 (enExample) 2008-01-10
JP4390728B2 true JP4390728B2 (ja) 2009-12-24

Family

ID=36914335

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005048775A Expired - Fee Related JP4390728B2 (ja) 2005-02-24 2005-02-24 ネットリスト生成装置

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US (2) US7398506B2 (enExample)
JP (1) JP4390728B2 (enExample)
TW (1) TW200643753A (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7890892B2 (en) * 2007-11-15 2011-02-15 International Business Machines Corporation Balanced and bi-directional bit line paths for memory arrays with programmable memory cells
US7913216B2 (en) 2008-02-16 2011-03-22 International Business Machines Corporation Accurate parasitics estimation for hierarchical customized VLSI design
US7962877B2 (en) * 2008-08-05 2011-06-14 International Business Machines Corporation Port assignment in hierarchical designs by abstracting macro logic

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11186398A (ja) 1997-12-19 1999-07-09 Sharp Corp 半導体集積回路の回路シミュレーションを行うためのデータ作成方法及びデータ作成システム
JP2002009260A (ja) 2000-06-26 2002-01-11 Hitachi Ltd 半導体装置の設計方法
US6405351B1 (en) * 2000-06-27 2002-06-11 Texas Instruments Incorporated System for verifying leaf-cell circuit properties
US6865726B1 (en) * 2001-10-22 2005-03-08 Cadence Design Systems, Inc. IC layout system employing a hierarchical database by updating cell library
JP2004094402A (ja) 2002-08-29 2004-03-25 Matsushita Electric Ind Co Ltd 遅延シミュレーション用ネットリスト生成システムおよび遅延シミュレーション用ネットリスト生成方法

Also Published As

Publication number Publication date
US7398506B2 (en) 2008-07-08
US20060190898A1 (en) 2006-08-24
US20080270967A1 (en) 2008-10-30
US7979817B2 (en) 2011-07-12
JP2006235920A (ja) 2006-09-07
TW200643753A (en) 2006-12-16

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